APC405.h 18 KB

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  1. /*
  2. * (C) Copyright 2005-2008
  3. * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  4. *
  5. * (C) Copyright 2001-2004
  6. * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * board/config.h - configuration options, board specific
  28. */
  29. #ifndef __CONFIG_H
  30. #define __CONFIG_H
  31. /*
  32. * High Level Configuration Options
  33. * (easy to change)
  34. */
  35. #define CONFIG_405GP 1 /* This is a PPC405 CPU */
  36. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  37. #define CONFIG_APCG405 1 /* ...on a APC405 board */
  38. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  39. #define CONFIG_BOARD_EARLY_INIT_R 1
  40. #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
  41. #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
  42. #define CONFIG_BOARD_TYPES 1 /* support board types */
  43. #define CONFIG_BAUDRATE 115200
  44. #define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */
  45. #define CONFIG_BOOTCOUNT_LIMIT 1
  46. #undef CONFIG_BOOTARGS
  47. #define CONFIG_SYS_USB_LOAD_COMMAND "fatload usb 0 200000 pImage;" \
  48. "fatload usb 0 300000 pImage.initrd"
  49. #define CONFIG_SYS_USB_SELF_COMMAND "usb start;run usb_load;usb stop;" \
  50. "run ramargs addip addcon usbargs;" \
  51. "bootm 200000 300000"
  52. #define CONFIG_SYS_USB_ARGS "setenv bootargs $(bootargs) usbboot=1"
  53. #define CONFIG_SYS_BOOTLIMIT "3"
  54. #define CONFIG_SYS_ALT_BOOTCOMMAND "run usb_self;reset"
  55. #define CONFIG_EXTRA_ENV_SETTINGS \
  56. "hostname=abg405\0" \
  57. "bd_type=abg405\0" \
  58. "serial#=AA0000\0" \
  59. "kernel_addr=fe000000\0" \
  60. "ramdisk_addr=fe100000\0" \
  61. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  62. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  63. "nfsroot=$(serverip):$(rootpath)\0" \
  64. "addip=setenv bootargs $(bootargs) " \
  65. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  66. ":$(hostname)::off panic=1\0" \
  67. "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)" \
  68. " $(optargs)\0" \
  69. "flash_self=run ramargs addip addcon;" \
  70. "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  71. "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;" \
  72. "bootm\0" \
  73. "rootpath=/tftpboot/abg405/target_root\0" \
  74. "img=/tftpboot/abg405/pImage\0" \
  75. "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0" \
  76. "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
  77. "cp.b 100000 fff80000 80000\0" \
  78. "ipaddr=10.0.111.111\0" \
  79. "netmask=255.255.0.0\0" \
  80. "serverip=10.0.0.190\0" \
  81. "splashimage=ffe80000\0" \
  82. "usb_load="CONFIG_SYS_USB_LOAD_COMMAND"\0" \
  83. "usb_self="CONFIG_SYS_USB_SELF_COMMAND"\0" \
  84. "usbargs="CONFIG_SYS_USB_ARGS"\0" \
  85. "bootlimit="CONFIG_SYS_BOOTLIMIT"\0" \
  86. "altbootcmd="CONFIG_SYS_ALT_BOOTCOMMAND"\0" \
  87. ""
  88. #define CONFIG_BOOTCOMMAND "run flash_self;reset"
  89. #define CONFIG_ETHADDR 00:02:27:8e:00:00
  90. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  91. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  92. #define CONFIG_NET_MULTI 1
  93. #undef CONFIG_HAS_ETH1
  94. #define CONFIG_MII 1 /* MII PHY management */
  95. #define CONFIG_PHY_ADDR 0 /* PHY address */
  96. #define CONFIG_LXT971_NO_SLEEP 1
  97. #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
  98. #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  99. /*
  100. * BOOTP options
  101. */
  102. #define CONFIG_BOOTP_BOOTFILESIZE
  103. #define CONFIG_BOOTP_BOOTPATH
  104. #define CONFIG_BOOTP_GATEWAY
  105. #define CONFIG_BOOTP_HOSTNAME
  106. /*
  107. * Command line configuration.
  108. */
  109. #include <config_cmd_default.h>
  110. #define CONFIG_CMD_DATE
  111. #define CONFIG_CMD_DHCP
  112. #define CONFIG_CMD_EEPROM
  113. #define CONFIG_CMD_ELF
  114. #define CONFIG_CMD_FAT
  115. #define CONFIG_CMD_I2C
  116. #define CONFIG_CMD_IDE
  117. #define CONFIG_CMD_IRQ
  118. #define CONFIG_CMD_MII
  119. #define CONFIG_CMD_PCI
  120. #define CONFIG_CMD_PING
  121. #define CONFIG_CMD_SOURCE
  122. #define CONFIG_CMD_USB
  123. #define CONFIG_MAC_PARTITION
  124. #define CONFIG_DOS_PARTITION
  125. #define CONFIG_SUPPORT_VFAT
  126. #define CONFIG_AUTO_UPDATE 1 /* autoupdate via CF or USB */
  127. #undef CONFIG_WATCHDOG /* watchdog disabled */
  128. #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
  129. #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
  130. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  131. /*
  132. * Miscellaneous configurable options
  133. */
  134. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  135. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  136. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  137. #if defined(CONFIG_CMD_KGDB)
  138. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  139. #else
  140. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  141. #endif
  142. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  143. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  144. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  145. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  146. #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  147. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  148. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  149. #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
  150. /* The following table includes the supported baudrates */
  151. #define CONFIG_SYS_BAUDRATE_TABLE \
  152. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  153. 57600, 115200, 230400, 460800, 921600 }
  154. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  155. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  156. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  157. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  158. /* Only interrupt boot if space is pressed */
  159. /* If a long serial cable is connected but */
  160. /* other end is dead, garbage will be read */
  161. #define CONFIG_AUTOBOOT_KEYED 1
  162. #define CONFIG_AUTOBOOT_PROMPT \
  163. "Press SPACE to abort autoboot in %d seconds\n", bootdelay
  164. #undef CONFIG_AUTOBOOT_DELAY_STR
  165. #define CONFIG_AUTOBOOT_STOP_STR " "
  166. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  167. #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
  168. /*
  169. * PCI stuff
  170. */
  171. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  172. #define PCI_HOST_FORCE 1 /* configure as pci host */
  173. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  174. #define CONFIG_PCI /* include pci support */
  175. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  176. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  177. /* resource configuration */
  178. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  179. #define CONFIG_PCI_SKIP_HOST_BRIDGE 1
  180. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
  181. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
  182. #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
  183. #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
  184. #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
  185. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  186. #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
  187. #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
  188. #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  189. /*
  190. * IDE/ATA stuff
  191. */
  192. #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
  193. #undef CONFIG_IDE_LED /* no led for ide supported */
  194. #define CONFIG_IDE_RESET 1 /* reset for ide supported */
  195. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
  196. #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS) /* max. 1 drives per IDE bus */
  197. #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
  198. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  199. #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
  200. #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
  201. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
  202. /*
  203. * Start addresses for the final memory configuration
  204. * (Set up by the startup code)
  205. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  206. */
  207. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  208. #define CONFIG_SYS_MONITOR_BASE 0xFFF80000
  209. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
  210. #define CONFIG_SYS_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */
  211. /*
  212. * For booting Linux, the board info and command line data
  213. * have to be in the first 8 MB of memory, since this is
  214. * the maximum mapped by the Linux kernel during initialization.
  215. */
  216. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init. Memory map for Linux */
  217. /*
  218. * FLASH organization
  219. */
  220. #ifndef __ASSEMBLY__
  221. extern int flash_banks;
  222. #endif
  223. #define CONFIG_SYS_FLASH_BASE 0xFE000000
  224. #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
  225. #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
  226. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
  227. #define CONFIG_SYS_MAX_FLASH_BANKS flash_banks /* max num of flash banks */
  228. /* updated in board_early_init_r */
  229. #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
  230. #define CONFIG_SYS_FLASH_QUIET_TEST 1
  231. #define CONFIG_SYS_FLASH_INCREMENT 0x01000000
  232. #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
  233. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { \
  234. {0xfe000000, 0x500000}, \
  235. {0xffe80000, 0x180000} \
  236. }
  237. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  238. #define CONFIG_SYS_FLASH_BANKS_LIST { \
  239. CONFIG_SYS_FLASH_BASE, \
  240. CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT \
  241. }
  242. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  243. /*
  244. * Environment Variable setup
  245. */
  246. #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  247. #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the */
  248. /* beginning of the EEPROM */
  249. #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
  250. #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting vendor vars */
  251. #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
  252. #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
  253. /*
  254. * I2C EEPROM (CAT24WC16) for environment
  255. */
  256. #define CONFIG_HARD_I2C /* I2c with hardware support */
  257. #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
  258. #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
  259. #define CONFIG_SYS_I2C_SLAVE 0x7F
  260. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
  261. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  262. /* mask of address bits that overflow into the "EEPROM chip address" */
  263. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  264. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
  265. /* 16 byte page write mode using*/
  266. /* last 4 bits of the address */
  267. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  268. /*
  269. * External Bus Controller (EBC) Setup
  270. */
  271. #define FLASH0_BA (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT) /* FLASH 0 BA */
  272. #define FLASH1_BA CONFIG_SYS_FLASH_BASE /* FLASH 1 Base Address */
  273. #define CAN_BA 0xF0000000 /* CAN Base Address */
  274. #define DUART0_BA 0xF0000400 /* DUART Base Address */
  275. #define DUART1_BA 0xF0000408 /* DUART Base Address */
  276. #define RTC_BA 0xF0000500 /* RTC Base Address */
  277. #define PS2_BA 0xF0000600 /* PS/2 Base Address */
  278. #define CF_BA 0xF0100000 /* CompactFlash Base Address */
  279. #define FPGA_BA 0xF0100100 /* FPGA internal Base Address */
  280. #define FUJI_BA 0xF0100200 /* Fuji internal Base Address */
  281. #define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */
  282. #define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */
  283. #define VGA_BA 0xF1000000 /* Epson VGA Base Address */
  284. #define CONFIG_SYS_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */
  285. /* Memory Bank 0 (Flash Bank 0) initialization */
  286. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  287. #define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
  288. #define CONFIG_SYS_EBC_PB0AP_HWREV8 CONFIG_SYS_EBC_PB0AP
  289. #define CONFIG_SYS_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */
  290. /* Memory Bank 1 (Flash Bank 1) initialization */
  291. #define CONFIG_SYS_EBC_PB1AP 0x92015480
  292. #define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
  293. /* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization */
  294. #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  295. #define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  296. /* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
  297. #define CONFIG_SYS_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  298. #define CONFIG_SYS_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
  299. /* Memory Bank 4 (PCMCIA Slot 1) initialization */
  300. #define CONFIG_SYS_EBC_PB4AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  301. #define CONFIG_SYS_EBC_PB4CR PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
  302. /* Memory Bank 5 (Epson VGA) initialization */
  303. #define CONFIG_SYS_EBC_PB5AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
  304. #define CONFIG_SYS_EBC_PB5CR VGA_BA | 0x5A000 /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
  305. /* Memory Bank 6 (PCMCIA Slot 2) initialization */
  306. #define CONFIG_SYS_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  307. #define CONFIG_SYS_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
  308. /*
  309. * FPGA stuff
  310. */
  311. /* FPGA internal regs */
  312. #define CONFIG_SYS_FPGA_CTRL 0x008
  313. #define CONFIG_SYS_FPGA_CTRL2 0x00a
  314. /* FPGA Control Reg */
  315. #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
  316. #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
  317. #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
  318. #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
  319. #define CONFIG_SYS_FPGA_MAX_SIZE 80*1024 /* 80kByte is enough for XC2S50 */
  320. /* FPGA program pin configuration */
  321. #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
  322. #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
  323. #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
  324. #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
  325. #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
  326. /*
  327. * LCD Setup
  328. */
  329. #define CONFIG_SYS_LCD_BIG_MEM (VGA_BA + 0x200000) /* S1D13806 Mem Base */
  330. #define CONFIG_SYS_LCD_BIG_REG VGA_BA /* S1D13806 Reg Base */
  331. #define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */
  332. /* Image information... */
  333. #define CONFIG_LCD_USED CONFIG_LCD_BIG
  334. #define CONFIG_SYS_LCD_MEM CONFIG_SYS_LCD_BIG_MEM
  335. #define CONFIG_SYS_LCD_REG CONFIG_SYS_LCD_BIG_REG
  336. #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
  337. /*
  338. * Definitions for initial stack pointer and data area (in data cache)
  339. */
  340. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  341. #define CONFIG_SYS_TEMP_STACK_OCM 1
  342. /* On Chip Memory location */
  343. #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  344. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  345. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
  346. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
  347. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved bytes for initial data */
  348. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  349. /* reserve some memory for BOOT limit info */
  350. #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
  351. #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
  352. #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8)
  353. #endif
  354. /*
  355. * Internal Definitions
  356. *
  357. * Boot Flags
  358. */
  359. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  360. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  361. /*
  362. * PCI OHCI controller
  363. */
  364. #define CONFIG_USB_OHCI_NEW 1
  365. #define CONFIG_PCI_OHCI 1
  366. #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
  367. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  368. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
  369. #define CONFIG_USB_STORAGE 1
  370. #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
  371. #endif /* __CONFIG_H */