lowlevel_init.S 12 KB

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  1. /*
  2. * Most of this taken from Redboot hal_platform_setup.h with cleanup
  3. *
  4. * NOTE: I haven't clean this up considerably, just enough to get it
  5. * running. See hal_platform_setup.h for the source. See
  6. * board/cradle/lowlevel_init.S for another PXA250 setup that is
  7. * much cleaner.
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <config.h>
  28. #include <version.h>
  29. #include <asm/arch/pxa-regs.h>
  30. DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
  31. /* wait for coprocessor write complete */
  32. .macro CPWAIT reg
  33. mrc p15,0,\reg,c2,c0,0
  34. mov \reg,\reg
  35. sub pc,pc,#4
  36. .endm
  37. .globl lowlevel_init
  38. lowlevel_init:
  39. mov r10, lr
  40. /* Set up GPIO pins first ----------------------------------------- */
  41. ldr r0,=GPSR0
  42. ldr r1,=CONFIG_SYS_GPSR0_VAL
  43. str r1,[r0]
  44. ldr r0,=GPSR1
  45. ldr r1,=CONFIG_SYS_GPSR1_VAL
  46. str r1,[r0]
  47. ldr r0,=GPSR2
  48. ldr r1,=CONFIG_SYS_GPSR2_VAL
  49. str r1,[r0]
  50. ldr r0,=GPCR0
  51. ldr r1,=CONFIG_SYS_GPCR0_VAL
  52. str r1,[r0]
  53. ldr r0,=GPCR1
  54. ldr r1,=CONFIG_SYS_GPCR1_VAL
  55. str r1,[r0]
  56. ldr r0,=GPCR2
  57. ldr r1,=CONFIG_SYS_GPCR2_VAL
  58. str r1,[r0]
  59. ldr r0,=GPDR0
  60. ldr r1,=CONFIG_SYS_GPDR0_VAL
  61. str r1,[r0]
  62. ldr r0,=GPDR1
  63. ldr r1,=CONFIG_SYS_GPDR1_VAL
  64. str r1,[r0]
  65. ldr r0,=GPDR2
  66. ldr r1,=CONFIG_SYS_GPDR2_VAL
  67. str r1,[r0]
  68. ldr r0,=GAFR0_L
  69. ldr r1,=CONFIG_SYS_GAFR0_L_VAL
  70. str r1,[r0]
  71. ldr r0,=GAFR0_U
  72. ldr r1,=CONFIG_SYS_GAFR0_U_VAL
  73. str r1,[r0]
  74. ldr r0,=GAFR1_L
  75. ldr r1,=CONFIG_SYS_GAFR1_L_VAL
  76. str r1,[r0]
  77. ldr r0,=GAFR1_U
  78. ldr r1,=CONFIG_SYS_GAFR1_U_VAL
  79. str r1,[r0]
  80. ldr r0,=GAFR2_L
  81. ldr r1,=CONFIG_SYS_GAFR2_L_VAL
  82. str r1,[r0]
  83. ldr r0,=GAFR2_U
  84. ldr r1,=CONFIG_SYS_GAFR2_U_VAL
  85. str r1,[r0]
  86. ldr r0,=PSSR /* enable GPIO pins */
  87. ldr r1,=CONFIG_SYS_PSSR_VAL
  88. str r1,[r0]
  89. /* ---------------------------------------------------------------- */
  90. /* Enable memory interface */
  91. /* */
  92. /* The sequence below is based on the recommended init steps */
  93. /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
  94. /* Chapter 10. */
  95. /* ---------------------------------------------------------------- */
  96. /* ---------------------------------------------------------------- */
  97. /* Step 1: Wait for at least 200 microsedonds to allow internal */
  98. /* clocks to settle. Only necessary after hard reset... */
  99. /* FIXME: can be optimized later */
  100. /* ---------------------------------------------------------------- */
  101. ldr r3, =OSCR /* reset the OS Timer Count to zero */
  102. mov r2, #0
  103. str r2, [r3]
  104. ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
  105. /* so 0x300 should be plenty */
  106. 1:
  107. ldr r2, [r3]
  108. cmp r4, r2
  109. bgt 1b
  110. mem_init:
  111. ldr r1,=MEMC_BASE /* get memory controller base addr. */
  112. /* ---------------------------------------------------------------- */
  113. /* Step 2a: Initialize Asynchronous static memory controller */
  114. /* ---------------------------------------------------------------- */
  115. /* MSC registers: timing, bus width, mem type */
  116. /* MSC0: nCS(0,1) */
  117. ldr r2,=CONFIG_SYS_MSC0_VAL
  118. str r2,[r1, #MSC0_OFFSET]
  119. ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */
  120. /* MSC1: nCS(2,3) */
  121. ldr r2,=CONFIG_SYS_MSC1_VAL
  122. str r2,[r1, #MSC1_OFFSET]
  123. ldr r2,[r1, #MSC1_OFFSET]
  124. /* MSC2: nCS(4,5) */
  125. ldr r2,=CONFIG_SYS_MSC2_VAL
  126. str r2,[r1, #MSC2_OFFSET]
  127. ldr r2,[r1, #MSC2_OFFSET]
  128. /* ---------------------------------------------------------------- */
  129. /* Step 2b: Initialize Card Interface */
  130. /* ---------------------------------------------------------------- */
  131. /* MECR: Memory Expansion Card Register */
  132. ldr r2,=CONFIG_SYS_MECR_VAL
  133. str r2,[r1, #MECR_OFFSET]
  134. ldr r2,[r1, #MECR_OFFSET]
  135. /* MCMEM0: Card Interface slot 0 timing */
  136. ldr r2,=CONFIG_SYS_MCMEM0_VAL
  137. str r2,[r1, #MCMEM0_OFFSET]
  138. ldr r2,[r1, #MCMEM0_OFFSET]
  139. /* MCMEM1: Card Interface slot 1 timing */
  140. ldr r2,=CONFIG_SYS_MCMEM1_VAL
  141. str r2,[r1, #MCMEM1_OFFSET]
  142. ldr r2,[r1, #MCMEM1_OFFSET]
  143. /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
  144. ldr r2,=CONFIG_SYS_MCATT0_VAL
  145. str r2,[r1, #MCATT0_OFFSET]
  146. ldr r2,[r1, #MCATT0_OFFSET]
  147. /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
  148. ldr r2,=CONFIG_SYS_MCATT1_VAL
  149. str r2,[r1, #MCATT1_OFFSET]
  150. ldr r2,[r1, #MCATT1_OFFSET]
  151. /* MCIO0: Card Interface I/O Space Timing, slot 0 */
  152. ldr r2,=CONFIG_SYS_MCIO0_VAL
  153. str r2,[r1, #MCIO0_OFFSET]
  154. ldr r2,[r1, #MCIO0_OFFSET]
  155. /* MCIO1: Card Interface I/O Space Timing, slot 1 */
  156. ldr r2,=CONFIG_SYS_MCIO1_VAL
  157. str r2,[r1, #MCIO1_OFFSET]
  158. ldr r2,[r1, #MCIO1_OFFSET]
  159. /* ---------------------------------------------------------------- */
  160. /* Step 2c: Write FLYCNFG FIXME: what's that??? */
  161. /* ---------------------------------------------------------------- */
  162. /* ---------------------------------------------------------------- */
  163. /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
  164. /* ---------------------------------------------------------------- */
  165. @ get the mdrefr settings
  166. ldr r4,=CONFIG_SYS_MDREFR_VAL
  167. @ write back mdrefr
  168. str r4,[r1, #MDREFR_OFFSET]
  169. ldr r4,[r1, #MDREFR_OFFSET]
  170. /* ---------------------------------------------------------------- */
  171. /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
  172. /* ---------------------------------------------------------------- */
  173. /* Initialize SXCNFG register. Assert the enable bits */
  174. /* Write SXMRS to cause an MRS command to all enabled banks of */
  175. /* synchronous static memory. Note that SXLCR need not be written */
  176. /* at this time. */
  177. /* FIXME: we use async mode for now */
  178. /* ---------------------------------------------------------------- */
  179. /* Step 4: Initialize SDRAM */
  180. /* ---------------------------------------------------------------- */
  181. @ set K1RUN for bank 0
  182. @
  183. orr r4, r4, #MDREFR_K1RUN
  184. @ write back mdrefr
  185. @
  186. str r4, [r1, #MDREFR_OFFSET]
  187. ldr r4, [r1, #MDREFR_OFFSET]
  188. @ deassert SLFRSH
  189. @
  190. bic r4, r4, #MDREFR_SLFRSH
  191. @ write back mdrefr
  192. @
  193. str r4, [r1, #MDREFR_OFFSET]
  194. ldr r4, [r1, #MDREFR_OFFSET]
  195. @ assert E1PIN
  196. @ if E0PIN is also used: #(MDREFR_E1PIN|MDREFR_E0PIN)
  197. orr r4, r4, #(MDREFR_E1PIN)
  198. @ write back mdrefr
  199. @
  200. str r4, [r1, #MDREFR_OFFSET]
  201. ldr r4, [r1, #MDREFR_OFFSET]
  202. nop
  203. nop
  204. /* Step 4d: */
  205. /* fetch platform value of mdcnfg */
  206. @
  207. ldr r2, =CONFIG_SYS_MDCNFG_VAL
  208. @ disable all sdram banks
  209. @
  210. bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
  211. bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
  212. @ program banks 0/1 for bus width
  213. @
  214. bic r2, r2, #MDCNFG_DWID0 @0=32-bit
  215. @ write initial value of mdcnfg, w/o enabling sdram banks
  216. @
  217. str r2, [r1, #MDCNFG_OFFSET]
  218. /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
  219. /* 100..200 µsec. */
  220. ldr r3, =OSCR /* reset the OS Timer Count to zero */
  221. mov r2, #0
  222. str r2, [r3]
  223. ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
  224. /* so 0x300 should be plenty */
  225. 1:
  226. ldr r2, [r3]
  227. cmp r4, r2
  228. bgt 1b
  229. /* Step 4f: Trigger a number (usually 8) refresh cycles by */
  230. /* attempting non-burst read or write accesses to disabled */
  231. /* SDRAM, as commonly specified in the power up sequence */
  232. /* documented in SDRAM data sheets. The address(es) used */
  233. /* for this purpose must not be cacheable. */
  234. ldr r3, =CONFIG_SYS_DRAM_BASE
  235. str r2, [r3]
  236. str r2, [r3]
  237. str r2, [r3]
  238. str r2, [r3]
  239. str r2, [r3]
  240. str r2, [r3]
  241. str r2, [r3]
  242. str r2, [r3]
  243. str r2, [r3]
  244. /* Step 4g: Write MDCNFG with enable bits asserted */
  245. /* get memory controller base address */
  246. ldr r1, =MEMC_BASE
  247. @fetch current mdcnfg value
  248. @
  249. ldr r3, [r1, #MDCNFG_OFFSET]
  250. @enable sdram bank 0 if installed (must do for any populated bank)
  251. @
  252. orr r3, r3, #MDCNFG_DE0
  253. @write back mdcnfg, enabling the sdram bank(s)
  254. @
  255. str r3, [r1, #MDCNFG_OFFSET]
  256. /* Step 4h: Write MDMRS. */
  257. ldr r2, =CONFIG_SYS_MDMRS_VAL
  258. str r2, [r1, #MDMRS_OFFSET]
  259. /* We are finished with Intel's memory controller initialisation */
  260. /* ---------------------------------------------------------------- */
  261. /* Disable (mask) all interrupts at interrupt controller */
  262. /* ---------------------------------------------------------------- */
  263. initirqs:
  264. mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
  265. ldr r2, =ICLR
  266. str r1, [r2]
  267. ldr r1, =CONFIG_SYS_ICMR_VAL /* mask all interrupts at the controller */
  268. ldr r2, =ICMR
  269. str r1, [r2]
  270. /* ---------------------------------------------------------------- */
  271. /* Clock initialisation */
  272. /* ---------------------------------------------------------------- */
  273. initclks:
  274. /* Disable the peripheral clocks, and set the core clock frequency */
  275. /* (hard-coding at 398.12MHz for now). */
  276. /* Turn Off ALL on-chip peripheral clocks for re-configuration */
  277. /* Note: See label 'ENABLECLKS' for the re-enabling */
  278. ldr r1, =CKEN
  279. mov r2, #0
  280. str r2, [r1]
  281. /* default value */
  282. ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
  283. /* ... and write the core clock config register */
  284. ldr r1, =CCCR
  285. str r2, [r1]
  286. #ifdef RTC
  287. /* enable the 32Khz oscillator for RTC and PowerManager */
  288. ldr r1, =OSCC
  289. mov r2, #OSCC_OON
  290. str r2, [r1]
  291. /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
  292. /* has settled. */
  293. 60:
  294. ldr r2, [r1]
  295. ands r2, r2, #1
  296. beq 60b
  297. #endif
  298. @ Turn on needed clocks
  299. @
  300. test:
  301. ldr r1, =CKEN
  302. ldr r2, =CONFIG_SYS_CKEN_VAL
  303. str r2, [r1]
  304. /* ---------------------------------------------------------------- */
  305. /* */
  306. /* ---------------------------------------------------------------- */
  307. /* Save SDRAM size ?*/
  308. ldr r1, =DRAM_SIZE
  309. str r8, [r1]
  310. /* FIXME */
  311. #define NODEBUG
  312. #ifdef NODEBUG
  313. /*Disable software and data breakpoints */
  314. mov r0,#0
  315. mcr p15,0,r0,c14,c8,0 /* ibcr0 */
  316. mcr p15,0,r0,c14,c9,0 /* ibcr1 */
  317. mcr p15,0,r0,c14,c4,0 /* dbcon */
  318. /*Enable all debug functionality */
  319. mov r0,#0x80000000
  320. mcr p14,0,r0,c10,c0,0 /* dcsr */
  321. #endif
  322. /* ---------------------------------------------------------------- */
  323. /* End lowlevel_init */
  324. /* ---------------------------------------------------------------- */
  325. endlowlevel_init:
  326. mov pc, lr