board_f.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2002-2006
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Marius Groeger <mgroeger@sysgo.de>
  10. */
  11. #include <common.h>
  12. #include <bloblist.h>
  13. #include <console.h>
  14. #include <cpu.h>
  15. #include <dm.h>
  16. #include <env.h>
  17. #include <env_internal.h>
  18. #include <fdtdec.h>
  19. #include <fs.h>
  20. #include <i2c.h>
  21. #include <initcall.h>
  22. #include <lcd.h>
  23. #include <malloc.h>
  24. #include <mapmem.h>
  25. #include <os.h>
  26. #include <post.h>
  27. #include <relocate.h>
  28. #ifdef CONFIG_SPL
  29. #include <spl.h>
  30. #endif
  31. #include <status_led.h>
  32. #include <sysreset.h>
  33. #include <timer.h>
  34. #include <trace.h>
  35. #include <video.h>
  36. #include <watchdog.h>
  37. #ifdef CONFIG_MACH_TYPE
  38. #include <asm/mach-types.h>
  39. #endif
  40. #if defined(CONFIG_MP) && defined(CONFIG_PPC)
  41. #include <asm/mp.h>
  42. #endif
  43. #include <asm/io.h>
  44. #include <asm/sections.h>
  45. #include <dm/root.h>
  46. #include <linux/errno.h>
  47. /*
  48. * Pointer to initial global data area
  49. *
  50. * Here we initialize it if needed.
  51. */
  52. #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
  53. #undef XTRN_DECLARE_GLOBAL_DATA_PTR
  54. #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
  55. DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
  56. #else
  57. DECLARE_GLOBAL_DATA_PTR;
  58. #endif
  59. /*
  60. * TODO(sjg@chromium.org): IMO this code should be
  61. * refactored to a single function, something like:
  62. *
  63. * void led_set_state(enum led_colour_t colour, int on);
  64. */
  65. /************************************************************************
  66. * Coloured LED functionality
  67. ************************************************************************
  68. * May be supplied by boards if desired
  69. */
  70. __weak void coloured_LED_init(void) {}
  71. __weak void red_led_on(void) {}
  72. __weak void red_led_off(void) {}
  73. __weak void green_led_on(void) {}
  74. __weak void green_led_off(void) {}
  75. __weak void yellow_led_on(void) {}
  76. __weak void yellow_led_off(void) {}
  77. __weak void blue_led_on(void) {}
  78. __weak void blue_led_off(void) {}
  79. /*
  80. * Why is gd allocated a register? Prior to reloc it might be better to
  81. * just pass it around to each function in this file?
  82. *
  83. * After reloc one could argue that it is hardly used and doesn't need
  84. * to be in a register. Or if it is it should perhaps hold pointers to all
  85. * global data for all modules, so that post-reloc we can avoid the massive
  86. * literal pool we get on ARM. Or perhaps just encourage each module to use
  87. * a structure...
  88. */
  89. #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
  90. static int init_func_watchdog_init(void)
  91. {
  92. # if defined(CONFIG_HW_WATCHDOG) && \
  93. (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
  94. defined(CONFIG_SH) || \
  95. defined(CONFIG_DESIGNWARE_WATCHDOG) || \
  96. defined(CONFIG_IMX_WATCHDOG))
  97. hw_watchdog_init();
  98. puts(" Watchdog enabled\n");
  99. # endif
  100. WATCHDOG_RESET();
  101. return 0;
  102. }
  103. int init_func_watchdog_reset(void)
  104. {
  105. WATCHDOG_RESET();
  106. return 0;
  107. }
  108. #endif /* CONFIG_WATCHDOG */
  109. __weak void board_add_ram_info(int use_default)
  110. {
  111. /* please define platform specific board_add_ram_info() */
  112. }
  113. static int init_baud_rate(void)
  114. {
  115. gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
  116. return 0;
  117. }
  118. static int display_text_info(void)
  119. {
  120. #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
  121. ulong bss_start, bss_end, text_base;
  122. bss_start = (ulong)&__bss_start;
  123. bss_end = (ulong)&__bss_end;
  124. #ifdef CONFIG_SYS_TEXT_BASE
  125. text_base = CONFIG_SYS_TEXT_BASE;
  126. #else
  127. text_base = CONFIG_SYS_MONITOR_BASE;
  128. #endif
  129. debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
  130. text_base, bss_start, bss_end);
  131. #endif
  132. return 0;
  133. }
  134. #ifdef CONFIG_SYSRESET
  135. static int print_resetinfo(void)
  136. {
  137. struct udevice *dev;
  138. char status[256];
  139. int ret;
  140. ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
  141. if (ret) {
  142. debug("%s: No sysreset device found (error: %d)\n",
  143. __func__, ret);
  144. /* Not all boards have sysreset drivers available during early
  145. * boot, so don't fail if one can't be found.
  146. */
  147. return 0;
  148. }
  149. if (!sysreset_get_status(dev, status, sizeof(status)))
  150. printf("%s", status);
  151. return 0;
  152. }
  153. #endif
  154. #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
  155. static int print_cpuinfo(void)
  156. {
  157. struct udevice *dev;
  158. char desc[512];
  159. int ret;
  160. ret = uclass_first_device_err(UCLASS_CPU, &dev);
  161. if (ret) {
  162. debug("%s: Could not get CPU device (err = %d)\n",
  163. __func__, ret);
  164. return ret;
  165. }
  166. ret = cpu_get_desc(dev, desc, sizeof(desc));
  167. if (ret) {
  168. debug("%s: Could not get CPU description (err = %d)\n",
  169. dev->name, ret);
  170. return ret;
  171. }
  172. printf("CPU: %s\n", desc);
  173. return 0;
  174. }
  175. #endif
  176. static int announce_dram_init(void)
  177. {
  178. puts("DRAM: ");
  179. return 0;
  180. }
  181. static int show_dram_config(void)
  182. {
  183. unsigned long long size;
  184. #ifdef CONFIG_NR_DRAM_BANKS
  185. int i;
  186. debug("\nRAM Configuration:\n");
  187. for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  188. size += gd->bd->bi_dram[i].size;
  189. debug("Bank #%d: %llx ", i,
  190. (unsigned long long)(gd->bd->bi_dram[i].start));
  191. #ifdef DEBUG
  192. print_size(gd->bd->bi_dram[i].size, "\n");
  193. #endif
  194. }
  195. debug("\nDRAM: ");
  196. #else
  197. size = gd->ram_size;
  198. #endif
  199. print_size(size, "");
  200. board_add_ram_info(0);
  201. putc('\n');
  202. return 0;
  203. }
  204. __weak int dram_init_banksize(void)
  205. {
  206. #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
  207. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  208. gd->bd->bi_dram[0].size = get_effective_memsize();
  209. #endif
  210. return 0;
  211. }
  212. #if defined(CONFIG_SYS_I2C)
  213. static int init_func_i2c(void)
  214. {
  215. puts("I2C: ");
  216. #ifdef CONFIG_SYS_I2C
  217. i2c_init_all();
  218. #else
  219. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  220. #endif
  221. puts("ready\n");
  222. return 0;
  223. }
  224. #endif
  225. #if defined(CONFIG_VID)
  226. __weak int init_func_vid(void)
  227. {
  228. return 0;
  229. }
  230. #endif
  231. static int setup_mon_len(void)
  232. {
  233. #if defined(__ARM__) || defined(__MICROBLAZE__)
  234. gd->mon_len = (ulong)&__bss_end - (ulong)_start;
  235. #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
  236. gd->mon_len = (ulong)&_end - (ulong)_init;
  237. #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
  238. gd->mon_len = CONFIG_SYS_MONITOR_LEN;
  239. #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
  240. gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
  241. #elif defined(CONFIG_SYS_MONITOR_BASE)
  242. /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
  243. gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
  244. #endif
  245. return 0;
  246. }
  247. static int setup_spl_handoff(void)
  248. {
  249. #if CONFIG_IS_ENABLED(HANDOFF)
  250. gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
  251. sizeof(struct spl_handoff));
  252. debug("Found SPL hand-off info %p\n", gd->spl_handoff);
  253. #endif
  254. return 0;
  255. }
  256. __weak int arch_cpu_init(void)
  257. {
  258. return 0;
  259. }
  260. __weak int mach_cpu_init(void)
  261. {
  262. return 0;
  263. }
  264. /* Get the top of usable RAM */
  265. __weak ulong board_get_usable_ram_top(ulong total_size)
  266. {
  267. #ifdef CONFIG_SYS_SDRAM_BASE
  268. /*
  269. * Detect whether we have so much RAM that it goes past the end of our
  270. * 32-bit address space. If so, clip the usable RAM so it doesn't.
  271. */
  272. if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
  273. /*
  274. * Will wrap back to top of 32-bit space when reservations
  275. * are made.
  276. */
  277. return 0;
  278. #endif
  279. return gd->ram_top;
  280. }
  281. static int setup_dest_addr(void)
  282. {
  283. debug("Monitor len: %08lX\n", gd->mon_len);
  284. /*
  285. * Ram is setup, size stored in gd !!
  286. */
  287. debug("Ram size: %08lX\n", (ulong)gd->ram_size);
  288. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  289. /*
  290. * Subtract specified amount of memory to hide so that it won't
  291. * get "touched" at all by U-Boot. By fixing up gd->ram_size
  292. * the Linux kernel should now get passed the now "corrected"
  293. * memory size and won't touch it either. This should work
  294. * for arch/ppc and arch/powerpc. Only Linux board ports in
  295. * arch/powerpc with bootwrapper support, that recalculate the
  296. * memory size from the SDRAM controller setup will have to
  297. * get fixed.
  298. */
  299. gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
  300. #endif
  301. #ifdef CONFIG_SYS_SDRAM_BASE
  302. gd->ram_base = CONFIG_SYS_SDRAM_BASE;
  303. #endif
  304. gd->ram_top = gd->ram_base + get_effective_memsize();
  305. gd->ram_top = board_get_usable_ram_top(gd->mon_len);
  306. gd->relocaddr = gd->ram_top;
  307. debug("Ram top: %08lX\n", (ulong)gd->ram_top);
  308. #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
  309. /*
  310. * We need to make sure the location we intend to put secondary core
  311. * boot code is reserved and not used by any part of u-boot
  312. */
  313. if (gd->relocaddr > determine_mp_bootpg(NULL)) {
  314. gd->relocaddr = determine_mp_bootpg(NULL);
  315. debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
  316. }
  317. #endif
  318. return 0;
  319. }
  320. #ifdef CONFIG_PRAM
  321. /* reserve protected RAM */
  322. static int reserve_pram(void)
  323. {
  324. ulong reg;
  325. reg = env_get_ulong("pram", 10, CONFIG_PRAM);
  326. gd->relocaddr -= (reg << 10); /* size is in kB */
  327. debug("Reserving %ldk for protected RAM at %08lx\n", reg,
  328. gd->relocaddr);
  329. return 0;
  330. }
  331. #endif /* CONFIG_PRAM */
  332. /* Round memory pointer down to next 4 kB limit */
  333. static int reserve_round_4k(void)
  334. {
  335. gd->relocaddr &= ~(4096 - 1);
  336. return 0;
  337. }
  338. #ifdef CONFIG_ARM
  339. __weak int reserve_mmu(void)
  340. {
  341. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  342. /* reserve TLB table */
  343. gd->arch.tlb_size = PGTABLE_SIZE;
  344. gd->relocaddr -= gd->arch.tlb_size;
  345. /* round down to next 64 kB limit */
  346. gd->relocaddr &= ~(0x10000 - 1);
  347. gd->arch.tlb_addr = gd->relocaddr;
  348. debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  349. gd->arch.tlb_addr + gd->arch.tlb_size);
  350. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  351. /*
  352. * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
  353. * with location within secure ram.
  354. */
  355. gd->arch.tlb_allocated = gd->arch.tlb_addr;
  356. #endif
  357. #endif
  358. return 0;
  359. }
  360. #endif
  361. static int reserve_video(void)
  362. {
  363. #ifdef CONFIG_DM_VIDEO
  364. ulong addr;
  365. int ret;
  366. addr = gd->relocaddr;
  367. ret = video_reserve(&addr);
  368. if (ret)
  369. return ret;
  370. gd->relocaddr = addr;
  371. #elif defined(CONFIG_LCD)
  372. # ifdef CONFIG_FB_ADDR
  373. gd->fb_base = CONFIG_FB_ADDR;
  374. # else
  375. /* reserve memory for LCD display (always full pages) */
  376. gd->relocaddr = lcd_setmem(gd->relocaddr);
  377. gd->fb_base = gd->relocaddr;
  378. # endif /* CONFIG_FB_ADDR */
  379. #endif
  380. return 0;
  381. }
  382. static int reserve_trace(void)
  383. {
  384. #ifdef CONFIG_TRACE
  385. gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
  386. gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
  387. debug("Reserving %luk for trace data at: %08lx\n",
  388. (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
  389. #endif
  390. return 0;
  391. }
  392. static int reserve_uboot(void)
  393. {
  394. if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
  395. /*
  396. * reserve memory for U-Boot code, data & bss
  397. * round down to next 4 kB limit
  398. */
  399. gd->relocaddr -= gd->mon_len;
  400. gd->relocaddr &= ~(4096 - 1);
  401. #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
  402. /* round down to next 64 kB limit so that IVPR stays aligned */
  403. gd->relocaddr &= ~(65536 - 1);
  404. #endif
  405. debug("Reserving %ldk for U-Boot at: %08lx\n",
  406. gd->mon_len >> 10, gd->relocaddr);
  407. }
  408. gd->start_addr_sp = gd->relocaddr;
  409. return 0;
  410. }
  411. /* reserve memory for malloc() area */
  412. static int reserve_malloc(void)
  413. {
  414. gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
  415. debug("Reserving %dk for malloc() at: %08lx\n",
  416. TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
  417. return 0;
  418. }
  419. /* (permanently) allocate a Board Info struct */
  420. static int reserve_board(void)
  421. {
  422. if (!gd->bd) {
  423. gd->start_addr_sp -= sizeof(bd_t);
  424. gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
  425. memset(gd->bd, '\0', sizeof(bd_t));
  426. debug("Reserving %zu Bytes for Board Info at: %08lx\n",
  427. sizeof(bd_t), gd->start_addr_sp);
  428. }
  429. return 0;
  430. }
  431. static int setup_machine(void)
  432. {
  433. #ifdef CONFIG_MACH_TYPE
  434. gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
  435. #endif
  436. return 0;
  437. }
  438. static int reserve_global_data(void)
  439. {
  440. gd->start_addr_sp -= sizeof(gd_t);
  441. gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
  442. debug("Reserving %zu Bytes for Global Data at: %08lx\n",
  443. sizeof(gd_t), gd->start_addr_sp);
  444. return 0;
  445. }
  446. static int reserve_fdt(void)
  447. {
  448. #ifndef CONFIG_OF_EMBED
  449. /*
  450. * If the device tree is sitting immediately above our image then we
  451. * must relocate it. If it is embedded in the data section, then it
  452. * will be relocated with other data.
  453. */
  454. if (gd->fdt_blob) {
  455. gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
  456. gd->start_addr_sp -= gd->fdt_size;
  457. gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
  458. debug("Reserving %lu Bytes for FDT at: %08lx\n",
  459. gd->fdt_size, gd->start_addr_sp);
  460. }
  461. #endif
  462. return 0;
  463. }
  464. static int reserve_bootstage(void)
  465. {
  466. #ifdef CONFIG_BOOTSTAGE
  467. int size = bootstage_get_size();
  468. gd->start_addr_sp -= size;
  469. gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
  470. debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
  471. gd->start_addr_sp);
  472. #endif
  473. return 0;
  474. }
  475. __weak int arch_reserve_stacks(void)
  476. {
  477. return 0;
  478. }
  479. static int reserve_stacks(void)
  480. {
  481. /* make stack pointer 16-byte aligned */
  482. gd->start_addr_sp -= 16;
  483. gd->start_addr_sp &= ~0xf;
  484. /*
  485. * let the architecture-specific code tailor gd->start_addr_sp and
  486. * gd->irq_sp
  487. */
  488. return arch_reserve_stacks();
  489. }
  490. static int reserve_bloblist(void)
  491. {
  492. #ifdef CONFIG_BLOBLIST
  493. gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE;
  494. gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
  495. #endif
  496. return 0;
  497. }
  498. static int display_new_sp(void)
  499. {
  500. debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
  501. return 0;
  502. }
  503. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  504. defined(CONFIG_SH)
  505. static int setup_board_part1(void)
  506. {
  507. bd_t *bd = gd->bd;
  508. /*
  509. * Save local variables to board info struct
  510. */
  511. bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
  512. bd->bi_memsize = gd->ram_size; /* size in bytes */
  513. #ifdef CONFIG_SYS_SRAM_BASE
  514. bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
  515. bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
  516. #endif
  517. #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
  518. bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
  519. #endif
  520. #if defined(CONFIG_M68K)
  521. bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
  522. #endif
  523. #if defined(CONFIG_MPC83xx)
  524. bd->bi_immrbar = CONFIG_SYS_IMMR;
  525. #endif
  526. return 0;
  527. }
  528. #endif
  529. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  530. static int setup_board_part2(void)
  531. {
  532. bd_t *bd = gd->bd;
  533. bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
  534. bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
  535. #if defined(CONFIG_CPM2)
  536. bd->bi_cpmfreq = gd->arch.cpm_clk;
  537. bd->bi_brgfreq = gd->arch.brg_clk;
  538. bd->bi_sccfreq = gd->arch.scc_clk;
  539. bd->bi_vco = gd->arch.vco_out;
  540. #endif /* CONFIG_CPM2 */
  541. #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
  542. bd->bi_pcifreq = gd->pci_clk;
  543. #endif
  544. #if defined(CONFIG_EXTRA_CLOCK)
  545. bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
  546. bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
  547. bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
  548. #endif
  549. return 0;
  550. }
  551. #endif
  552. #ifdef CONFIG_POST
  553. static int init_post(void)
  554. {
  555. post_bootmode_init();
  556. post_run(NULL, POST_ROM | post_bootmode_get(0));
  557. return 0;
  558. }
  559. #endif
  560. static int reloc_fdt(void)
  561. {
  562. #ifndef CONFIG_OF_EMBED
  563. if (gd->flags & GD_FLG_SKIP_RELOC)
  564. return 0;
  565. if (gd->new_fdt) {
  566. memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
  567. gd->fdt_blob = gd->new_fdt;
  568. }
  569. #endif
  570. return 0;
  571. }
  572. static int reloc_bootstage(void)
  573. {
  574. #ifdef CONFIG_BOOTSTAGE
  575. if (gd->flags & GD_FLG_SKIP_RELOC)
  576. return 0;
  577. if (gd->new_bootstage) {
  578. int size = bootstage_get_size();
  579. debug("Copying bootstage from %p to %p, size %x\n",
  580. gd->bootstage, gd->new_bootstage, size);
  581. memcpy(gd->new_bootstage, gd->bootstage, size);
  582. gd->bootstage = gd->new_bootstage;
  583. }
  584. #endif
  585. return 0;
  586. }
  587. static int reloc_bloblist(void)
  588. {
  589. #ifdef CONFIG_BLOBLIST
  590. if (gd->flags & GD_FLG_SKIP_RELOC)
  591. return 0;
  592. if (gd->new_bloblist) {
  593. int size = CONFIG_BLOBLIST_SIZE;
  594. debug("Copying bloblist from %p to %p, size %x\n",
  595. gd->bloblist, gd->new_bloblist, size);
  596. memcpy(gd->new_bloblist, gd->bloblist, size);
  597. gd->bloblist = gd->new_bloblist;
  598. }
  599. #endif
  600. return 0;
  601. }
  602. static int setup_reloc(void)
  603. {
  604. if (gd->flags & GD_FLG_SKIP_RELOC) {
  605. debug("Skipping relocation due to flag\n");
  606. return 0;
  607. }
  608. #ifdef CONFIG_SYS_TEXT_BASE
  609. #ifdef ARM
  610. gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
  611. #elif defined(CONFIG_M68K)
  612. /*
  613. * On all ColdFire arch cpu, monitor code starts always
  614. * just after the default vector table location, so at 0x400
  615. */
  616. gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
  617. #elif !defined(CONFIG_SANDBOX)
  618. gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
  619. #endif
  620. #endif
  621. memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
  622. debug("Relocation Offset is: %08lx\n", gd->reloc_off);
  623. debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
  624. gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
  625. gd->start_addr_sp);
  626. return 0;
  627. }
  628. #ifdef CONFIG_OF_BOARD_FIXUP
  629. static int fix_fdt(void)
  630. {
  631. return board_fix_fdt((void *)gd->fdt_blob);
  632. }
  633. #endif
  634. /* ARM calls relocate_code from its crt0.S */
  635. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  636. !CONFIG_IS_ENABLED(X86_64)
  637. static int jump_to_copy(void)
  638. {
  639. if (gd->flags & GD_FLG_SKIP_RELOC)
  640. return 0;
  641. /*
  642. * x86 is special, but in a nice way. It uses a trampoline which
  643. * enables the dcache if possible.
  644. *
  645. * For now, other archs use relocate_code(), which is implemented
  646. * similarly for all archs. When we do generic relocation, hopefully
  647. * we can make all archs enable the dcache prior to relocation.
  648. */
  649. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  650. /*
  651. * SDRAM and console are now initialised. The final stack can now
  652. * be setup in SDRAM. Code execution will continue in Flash, but
  653. * with the stack in SDRAM and Global Data in temporary memory
  654. * (CPU cache)
  655. */
  656. arch_setup_gd(gd->new_gd);
  657. board_init_f_r_trampoline(gd->start_addr_sp);
  658. #else
  659. relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
  660. #endif
  661. return 0;
  662. }
  663. #endif
  664. /* Record the board_init_f() bootstage (after arch_cpu_init()) */
  665. static int initf_bootstage(void)
  666. {
  667. bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
  668. IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
  669. int ret;
  670. ret = bootstage_init(!from_spl);
  671. if (ret)
  672. return ret;
  673. if (from_spl) {
  674. const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
  675. CONFIG_BOOTSTAGE_STASH_SIZE);
  676. ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
  677. if (ret && ret != -ENOENT) {
  678. debug("Failed to unstash bootstage: err=%d\n", ret);
  679. return ret;
  680. }
  681. }
  682. bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
  683. return 0;
  684. }
  685. static int initf_console_record(void)
  686. {
  687. #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  688. return console_record_init();
  689. #else
  690. return 0;
  691. #endif
  692. }
  693. static int initf_dm(void)
  694. {
  695. #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  696. int ret;
  697. bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
  698. ret = dm_init_and_scan(true);
  699. bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
  700. if (ret)
  701. return ret;
  702. #endif
  703. #ifdef CONFIG_TIMER_EARLY
  704. ret = dm_timer_init();
  705. if (ret)
  706. return ret;
  707. #endif
  708. return 0;
  709. }
  710. /* Architecture-specific memory reservation */
  711. __weak int reserve_arch(void)
  712. {
  713. return 0;
  714. }
  715. __weak int arch_cpu_init_dm(void)
  716. {
  717. return 0;
  718. }
  719. static const init_fnc_t init_sequence_f[] = {
  720. setup_mon_len,
  721. #ifdef CONFIG_OF_CONTROL
  722. fdtdec_setup,
  723. #endif
  724. #ifdef CONFIG_TRACE_EARLY
  725. trace_early_init,
  726. #endif
  727. initf_malloc,
  728. log_init,
  729. initf_bootstage, /* uses its own timer, so does not need DM */
  730. #ifdef CONFIG_BLOBLIST
  731. bloblist_init,
  732. #endif
  733. setup_spl_handoff,
  734. initf_console_record,
  735. #if defined(CONFIG_HAVE_FSP)
  736. arch_fsp_init,
  737. #endif
  738. arch_cpu_init, /* basic arch cpu dependent setup */
  739. mach_cpu_init, /* SoC/machine dependent CPU setup */
  740. initf_dm,
  741. arch_cpu_init_dm,
  742. #if defined(CONFIG_BOARD_EARLY_INIT_F)
  743. board_early_init_f,
  744. #endif
  745. #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
  746. /* get CPU and bus clocks according to the environment variable */
  747. get_clocks, /* get CPU and bus clocks (etc.) */
  748. #endif
  749. #if !defined(CONFIG_M68K)
  750. timer_init, /* initialize timer */
  751. #endif
  752. #if defined(CONFIG_BOARD_POSTCLK_INIT)
  753. board_postclk_init,
  754. #endif
  755. env_init, /* initialize environment */
  756. init_baud_rate, /* initialze baudrate settings */
  757. serial_init, /* serial communications setup */
  758. console_init_f, /* stage 1 init of console */
  759. display_options, /* say that we are here */
  760. display_text_info, /* show debugging info if required */
  761. #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
  762. checkcpu,
  763. #endif
  764. #if defined(CONFIG_SYSRESET)
  765. print_resetinfo,
  766. #endif
  767. #if defined(CONFIG_DISPLAY_CPUINFO)
  768. print_cpuinfo, /* display cpu info (and speed) */
  769. #endif
  770. #if defined(CONFIG_DTB_RESELECT)
  771. embedded_dtb_select,
  772. #endif
  773. #if defined(CONFIG_DISPLAY_BOARDINFO)
  774. show_board_info,
  775. #endif
  776. INIT_FUNC_WATCHDOG_INIT
  777. #if defined(CONFIG_MISC_INIT_F)
  778. misc_init_f,
  779. #endif
  780. INIT_FUNC_WATCHDOG_RESET
  781. #if defined(CONFIG_SYS_I2C)
  782. init_func_i2c,
  783. #endif
  784. #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
  785. init_func_vid,
  786. #endif
  787. announce_dram_init,
  788. dram_init, /* configure available RAM banks */
  789. #ifdef CONFIG_POST
  790. post_init_f,
  791. #endif
  792. INIT_FUNC_WATCHDOG_RESET
  793. #if defined(CONFIG_SYS_DRAM_TEST)
  794. testdram,
  795. #endif /* CONFIG_SYS_DRAM_TEST */
  796. INIT_FUNC_WATCHDOG_RESET
  797. #ifdef CONFIG_POST
  798. init_post,
  799. #endif
  800. INIT_FUNC_WATCHDOG_RESET
  801. /*
  802. * Now that we have DRAM mapped and working, we can
  803. * relocate the code and continue running from DRAM.
  804. *
  805. * Reserve memory at end of RAM for (top down in that order):
  806. * - area that won't get touched by U-Boot and Linux (optional)
  807. * - kernel log buffer
  808. * - protected RAM
  809. * - LCD framebuffer
  810. * - monitor code
  811. * - board info struct
  812. */
  813. setup_dest_addr,
  814. #ifdef CONFIG_PRAM
  815. reserve_pram,
  816. #endif
  817. reserve_round_4k,
  818. #ifdef CONFIG_ARM
  819. reserve_mmu,
  820. #endif
  821. reserve_video,
  822. reserve_trace,
  823. reserve_uboot,
  824. reserve_malloc,
  825. reserve_board,
  826. setup_machine,
  827. reserve_global_data,
  828. reserve_fdt,
  829. reserve_bootstage,
  830. reserve_bloblist,
  831. reserve_arch,
  832. reserve_stacks,
  833. dram_init_banksize,
  834. show_dram_config,
  835. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  836. defined(CONFIG_SH)
  837. setup_board_part1,
  838. #endif
  839. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  840. INIT_FUNC_WATCHDOG_RESET
  841. setup_board_part2,
  842. #endif
  843. display_new_sp,
  844. #ifdef CONFIG_OF_BOARD_FIXUP
  845. fix_fdt,
  846. #endif
  847. INIT_FUNC_WATCHDOG_RESET
  848. reloc_fdt,
  849. reloc_bootstage,
  850. reloc_bloblist,
  851. setup_reloc,
  852. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  853. copy_uboot_to_ram,
  854. do_elf_reloc_fixups,
  855. clear_bss,
  856. #endif
  857. #if defined(CONFIG_XTENSA)
  858. clear_bss,
  859. #endif
  860. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  861. !CONFIG_IS_ENABLED(X86_64)
  862. jump_to_copy,
  863. #endif
  864. NULL,
  865. };
  866. void board_init_f(ulong boot_flags)
  867. {
  868. gd->flags = boot_flags;
  869. gd->have_console = 0;
  870. if (initcall_run_list(init_sequence_f))
  871. hang();
  872. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  873. !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
  874. !defined(CONFIG_ARC)
  875. /* NOTREACHED - jump_to_copy() does not return */
  876. hang();
  877. #endif
  878. }
  879. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  880. /*
  881. * For now this code is only used on x86.
  882. *
  883. * init_sequence_f_r is the list of init functions which are run when
  884. * U-Boot is executing from Flash with a semi-limited 'C' environment.
  885. * The following limitations must be considered when implementing an
  886. * '_f_r' function:
  887. * - 'static' variables are read-only
  888. * - Global Data (gd->xxx) is read/write
  889. *
  890. * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
  891. * supported). It _should_, if possible, copy global data to RAM and
  892. * initialise the CPU caches (to speed up the relocation process)
  893. *
  894. * NOTE: At present only x86 uses this route, but it is intended that
  895. * all archs will move to this when generic relocation is implemented.
  896. */
  897. static const init_fnc_t init_sequence_f_r[] = {
  898. #if !CONFIG_IS_ENABLED(X86_64)
  899. init_cache_f_r,
  900. #endif
  901. NULL,
  902. };
  903. void board_init_f_r(void)
  904. {
  905. if (initcall_run_list(init_sequence_f_r))
  906. hang();
  907. /*
  908. * The pre-relocation drivers may be using memory that has now gone
  909. * away. Mark serial as unavailable - this will fall back to the debug
  910. * UART if available.
  911. *
  912. * Do the same with log drivers since the memory may not be available.
  913. */
  914. gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
  915. #ifdef CONFIG_TIMER
  916. gd->timer = NULL;
  917. #endif
  918. /*
  919. * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
  920. * Transfer execution from Flash to RAM by calculating the address
  921. * of the in-RAM copy of board_init_r() and calling it
  922. */
  923. (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
  924. /* NOTREACHED - board_init_r() does not return */
  925. hang();
  926. }
  927. #endif /* CONFIG_X86 */