lager.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/lager/lager.c
  4. * This file is lager board support.
  5. *
  6. * Copyright (C) 2013 Renesas Electronics Corporation
  7. * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <env_internal.h>
  12. #include <malloc.h>
  13. #include <netdev.h>
  14. #include <dm.h>
  15. #include <dm/platform_data/serial_sh.h>
  16. #include <asm/processor.h>
  17. #include <asm/mach-types.h>
  18. #include <asm/io.h>
  19. #include <linux/errno.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/gpio.h>
  22. #include <asm/arch/rmobile.h>
  23. #include <asm/arch/rcar-mstp.h>
  24. #include <asm/arch/mmc.h>
  25. #include <asm/arch/sh_sdhi.h>
  26. #include <miiphy.h>
  27. #include <i2c.h>
  28. #include <mmc.h>
  29. #include "qos.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define CLK2MHZ(clk) (clk / 1000 / 1000)
  32. void s_init(void)
  33. {
  34. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  35. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  36. /* Watchdog init */
  37. writel(0xA5A5A500, &rwdt->rwtcsra);
  38. writel(0xA5A5A500, &swdt->swtcsra);
  39. /* CPU frequency setting. Set to 1.4GHz */
  40. if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
  41. u32 stat = 0;
  42. u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
  43. << PLL0_STC_BIT;
  44. clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  45. do {
  46. stat = readl(PLLECR) & PLL0ST;
  47. } while (stat == 0x0);
  48. }
  49. /* QoS(Quality-of-Service) Init */
  50. qos_init();
  51. }
  52. #define TMU0_MSTP125 BIT(25)
  53. #define SD1CKCR 0xE6150078
  54. #define SD2CKCR 0xE615026C
  55. #define SD_97500KHZ 0x7
  56. int board_early_init_f(void)
  57. {
  58. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  59. /*
  60. * SD0 clock is set to 97.5MHz by default.
  61. * Set SD1 and SD2 to the 97.5MHz as well.
  62. */
  63. writel(SD_97500KHZ, SD1CKCR);
  64. writel(SD_97500KHZ, SD2CKCR);
  65. return 0;
  66. }
  67. #define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */
  68. int board_init(void)
  69. {
  70. /* adress of boot parameters */
  71. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  72. /* Force ethernet PHY out of reset */
  73. gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  74. gpio_direction_output(ETHERNET_PHY_RESET, 0);
  75. mdelay(10);
  76. gpio_direction_output(ETHERNET_PHY_RESET, 1);
  77. return 0;
  78. }
  79. int dram_init(void)
  80. {
  81. if (fdtdec_setup_mem_size_base() != 0)
  82. return -EINVAL;
  83. return 0;
  84. }
  85. int dram_init_banksize(void)
  86. {
  87. fdtdec_setup_memory_banksize();
  88. return 0;
  89. }
  90. /* KSZ8041NL/RNL */
  91. #define PHY_CONTROL1 0x1E
  92. #define PHY_LED_MODE 0xC000
  93. #define PHY_LED_MODE_ACK 0x4000
  94. int board_phy_config(struct phy_device *phydev)
  95. {
  96. int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
  97. ret &= ~PHY_LED_MODE;
  98. ret |= PHY_LED_MODE_ACK;
  99. ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
  100. return 0;
  101. }
  102. void reset_cpu(ulong addr)
  103. {
  104. struct udevice *dev;
  105. const u8 pmic_bus = 2;
  106. const u8 pmic_addr = 0x58;
  107. u8 data;
  108. int ret;
  109. ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
  110. if (ret)
  111. hang();
  112. ret = dm_i2c_read(dev, 0x13, &data, 1);
  113. if (ret)
  114. hang();
  115. data |= BIT(1);
  116. ret = dm_i2c_write(dev, 0x13, &data, 1);
  117. if (ret)
  118. hang();
  119. }
  120. enum env_location env_get_location(enum env_operation op, int prio)
  121. {
  122. const u32 load_magic = 0xb33fc0de;
  123. /* Block environment access if loaded using JTAG */
  124. if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
  125. (op != ENVOP_INIT))
  126. return ENVL_UNKNOWN;
  127. if (prio)
  128. return ENVL_UNKNOWN;
  129. return ENVL_SPI_FLASH;
  130. }