lx2160a.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018-2019 NXP
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <dm/platform_data/serial_pl01x.h>
  8. #include <i2c.h>
  9. #include <malloc.h>
  10. #include <errno.h>
  11. #include <netdev.h>
  12. #include <fsl_ddr.h>
  13. #include <fsl_sec.h>
  14. #include <asm/io.h>
  15. #include <fdt_support.h>
  16. #include <linux/libfdt.h>
  17. #include <fsl-mc/fsl_mc.h>
  18. #include <env_internal.h>
  19. #include <efi_loader.h>
  20. #include <asm/arch/mmu.h>
  21. #include <hwconfig.h>
  22. #include <asm/arch/fsl_serdes.h>
  23. #include <asm/arch/soc.h>
  24. #include "../common/qixis.h"
  25. #include "../common/vid.h"
  26. #include <fsl_immap.h>
  27. #ifdef CONFIG_EMC2305
  28. #include "../common/emc2305.h"
  29. #endif
  30. #ifdef CONFIG_TARGET_LX2160AQDS
  31. #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
  32. #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
  33. #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
  34. #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
  35. #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
  36. #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
  37. #define SDHC1_BASE_PMUX_DSPI 2
  38. #define SDHC2_BASE_PMUX_DSPI 2
  39. #define IIC5_PMUX_SPI3 3
  40. #endif /* CONFIG_TARGET_LX2160AQDS */
  41. DECLARE_GLOBAL_DATA_PTR;
  42. static struct pl01x_serial_platdata serial0 = {
  43. #if CONFIG_CONS_INDEX == 0
  44. .base = CONFIG_SYS_SERIAL0,
  45. #elif CONFIG_CONS_INDEX == 1
  46. .base = CONFIG_SYS_SERIAL1,
  47. #else
  48. #error "Unsupported console index value."
  49. #endif
  50. .type = TYPE_PL011,
  51. };
  52. U_BOOT_DEVICE(nxp_serial0) = {
  53. .name = "serial_pl01x",
  54. .platdata = &serial0,
  55. };
  56. static struct pl01x_serial_platdata serial1 = {
  57. .base = CONFIG_SYS_SERIAL1,
  58. .type = TYPE_PL011,
  59. };
  60. U_BOOT_DEVICE(nxp_serial1) = {
  61. .name = "serial_pl01x",
  62. .platdata = &serial1,
  63. };
  64. int select_i2c_ch_pca9547(u8 ch)
  65. {
  66. int ret;
  67. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  68. if (ret) {
  69. puts("PCA: failed to select proper channel\n");
  70. return ret;
  71. }
  72. return 0;
  73. }
  74. static void uart_get_clock(void)
  75. {
  76. serial0.clock = get_serial_clock();
  77. serial1.clock = get_serial_clock();
  78. }
  79. int board_early_init_f(void)
  80. {
  81. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  82. i2c_early_init_f();
  83. #endif
  84. /* get required clock for UART IP */
  85. uart_get_clock();
  86. #ifdef CONFIG_EMC2305
  87. select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
  88. emc2305_init();
  89. set_fan_speed(I2C_EMC2305_PWM);
  90. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  91. #endif
  92. fsl_lsch3_early_init_f();
  93. return 0;
  94. }
  95. #if defined(CONFIG_TARGET_LX2160AQDS)
  96. void esdhc_dspi_status_fixup(void *blob)
  97. {
  98. const char esdhc0_path[] = "/soc/esdhc@2140000";
  99. const char esdhc1_path[] = "/soc/esdhc@2150000";
  100. const char dspi0_path[] = "/soc/dspi@2100000";
  101. const char dspi1_path[] = "/soc/dspi@2110000";
  102. const char dspi2_path[] = "/soc/dspi@2120000";
  103. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  104. u32 sdhc1_base_pmux;
  105. u32 sdhc2_base_pmux;
  106. u32 iic5_pmux;
  107. /* Check RCW field sdhc1_base_pmux to enable/disable
  108. * esdhc0/dspi0 DT node
  109. */
  110. sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  111. & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
  112. sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
  113. if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
  114. do_fixup_by_path(blob, dspi0_path, "status", "okay",
  115. sizeof("okay"), 1);
  116. do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
  117. sizeof("disabled"), 1);
  118. } else {
  119. do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  120. sizeof("okay"), 1);
  121. do_fixup_by_path(blob, dspi0_path, "status", "disabled",
  122. sizeof("disabled"), 1);
  123. }
  124. /* Check RCW field sdhc2_base_pmux to enable/disable
  125. * esdhc1/dspi1 DT node
  126. */
  127. sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
  128. & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
  129. sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
  130. if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
  131. do_fixup_by_path(blob, dspi1_path, "status", "okay",
  132. sizeof("okay"), 1);
  133. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  134. sizeof("disabled"), 1);
  135. } else {
  136. do_fixup_by_path(blob, esdhc1_path, "status", "okay",
  137. sizeof("okay"), 1);
  138. do_fixup_by_path(blob, dspi1_path, "status", "disabled",
  139. sizeof("disabled"), 1);
  140. }
  141. /* Check RCW field IIC5 to enable dspi2 DT node */
  142. iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  143. & FSL_CHASSIS3_IIC5_PMUX_MASK;
  144. iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
  145. if (iic5_pmux == IIC5_PMUX_SPI3) {
  146. do_fixup_by_path(blob, dspi2_path, "status", "okay",
  147. sizeof("okay"), 1);
  148. }
  149. }
  150. #endif
  151. int esdhc_status_fixup(void *blob, const char *compat)
  152. {
  153. #if defined(CONFIG_TARGET_LX2160AQDS)
  154. /* Enable esdhc and dspi DT nodes based on RCW fields */
  155. esdhc_dspi_status_fixup(blob);
  156. #else
  157. /* Enable both esdhc DT nodes for LX2160ARDB */
  158. do_fixup_by_compat(blob, compat, "status", "okay",
  159. sizeof("okay"), 1);
  160. #endif
  161. return 0;
  162. }
  163. #if defined(CONFIG_VID)
  164. int i2c_multiplexer_select_vid_channel(u8 channel)
  165. {
  166. return select_i2c_ch_pca9547(channel);
  167. }
  168. int init_func_vid(void)
  169. {
  170. if (adjust_vdd(0) < 0)
  171. printf("core voltage not adjusted\n");
  172. return 0;
  173. }
  174. #endif
  175. int checkboard(void)
  176. {
  177. enum boot_src src = get_boot_src();
  178. char buf[64];
  179. u8 sw;
  180. #ifdef CONFIG_TARGET_LX2160AQDS
  181. int clock;
  182. static const char *const freq[] = {"100", "125", "156.25",
  183. "161.13", "322.26", "", "", "",
  184. "", "", "", "", "", "", "",
  185. "100 separate SSCG"};
  186. #endif
  187. cpu_name(buf);
  188. #ifdef CONFIG_TARGET_LX2160AQDS
  189. printf("Board: %s-QDS, ", buf);
  190. #else
  191. printf("Board: %s-RDB, ", buf);
  192. #endif
  193. sw = QIXIS_READ(arch);
  194. printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
  195. if (src == BOOT_SOURCE_SD_MMC) {
  196. puts("SD\n");
  197. } else {
  198. sw = QIXIS_READ(brdcfg[0]);
  199. sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
  200. switch (sw) {
  201. case 0:
  202. case 4:
  203. puts("FlexSPI DEV#0\n");
  204. break;
  205. case 1:
  206. puts("FlexSPI DEV#1\n");
  207. break;
  208. case 2:
  209. case 3:
  210. puts("FlexSPI EMU\n");
  211. break;
  212. default:
  213. printf("invalid setting, xmap: %d\n", sw);
  214. break;
  215. }
  216. }
  217. #ifdef CONFIG_TARGET_LX2160AQDS
  218. printf("FPGA: v%d (%s), build %d",
  219. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  220. (int)qixis_read_minor());
  221. /* the timestamp string contains "\n" at the end */
  222. printf(" on %s", qixis_read_time(buf));
  223. puts("SERDES1 Reference : ");
  224. sw = QIXIS_READ(brdcfg[2]);
  225. clock = sw >> 4;
  226. printf("Clock1 = %sMHz ", freq[clock]);
  227. clock = sw & 0x0f;
  228. printf("Clock2 = %sMHz", freq[clock]);
  229. sw = QIXIS_READ(brdcfg[3]);
  230. puts("\nSERDES2 Reference : ");
  231. clock = sw >> 4;
  232. printf("Clock1 = %sMHz ", freq[clock]);
  233. clock = sw & 0x0f;
  234. printf("Clock2 = %sMHz", freq[clock]);
  235. sw = QIXIS_READ(brdcfg[12]);
  236. puts("\nSERDES3 Reference : ");
  237. clock = sw >> 4;
  238. printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
  239. #else
  240. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  241. puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
  242. puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
  243. puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
  244. #endif
  245. return 0;
  246. }
  247. #ifdef CONFIG_TARGET_LX2160AQDS
  248. /*
  249. * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
  250. */
  251. u8 qixis_esdhc_detect_quirk(void)
  252. {
  253. /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
  254. * SDHC1 Card ID:
  255. * Specifies the type of card installed in the SDHC1 adapter slot.
  256. * 000= (reserved)
  257. * 001= eMMC V4.5 adapter is installed.
  258. * 010= SD/MMC 3.3V adapter is installed.
  259. * 011= eMMC V4.4 adapter is installed.
  260. * 100= eMMC V5.0 adapter is installed.
  261. * 101= MMC card/Legacy (3.3V) adapter is installed.
  262. * 110= SDCard V2/V3 adapter installed.
  263. * 111= no adapter is installed.
  264. */
  265. return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
  266. QIXIS_ESDHC_NO_ADAPTER);
  267. }
  268. int config_board_mux(void)
  269. {
  270. u8 reg11, reg5, reg13;
  271. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  272. u32 sdhc1_base_pmux;
  273. u32 sdhc2_base_pmux;
  274. u32 iic5_pmux;
  275. /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
  276. * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
  277. * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
  278. * Qixis and remote systems are isolated from the I2C1 bus.
  279. * Processor connections are still available.
  280. * SPI2 CS2_B controls EN25S64 SPI memory device.
  281. * SPI3 CS2_B controls EN25S64 SPI memory device.
  282. * EC2 connects to PHY #2 using RGMII protocol.
  283. * CLK_OUT connects to FPGA for clock measurement.
  284. */
  285. reg5 = QIXIS_READ(brdcfg[5]);
  286. reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
  287. QIXIS_WRITE(brdcfg[5], reg5);
  288. /* Check RCW field sdhc1_base_pmux
  289. * esdhc0 : sdhc1_base_pmux = 0
  290. * dspi0 : sdhc1_base_pmux = 2
  291. */
  292. sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  293. & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
  294. sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
  295. if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
  296. reg11 = QIXIS_READ(brdcfg[11]);
  297. reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
  298. QIXIS_WRITE(brdcfg[11], reg11);
  299. } else {
  300. /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
  301. * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
  302. * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
  303. */
  304. reg11 = QIXIS_READ(brdcfg[11]);
  305. reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
  306. QIXIS_WRITE(brdcfg[11], reg11);
  307. }
  308. /* Check RCW field sdhc2_base_pmux
  309. * esdhc1 : sdhc2_base_pmux = 0 (default)
  310. * dspi1 : sdhc2_base_pmux = 2
  311. */
  312. sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
  313. & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
  314. sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
  315. if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
  316. reg13 = QIXIS_READ(brdcfg[13]);
  317. reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
  318. QIXIS_WRITE(brdcfg[13], reg13);
  319. } else {
  320. reg13 = QIXIS_READ(brdcfg[13]);
  321. reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
  322. QIXIS_WRITE(brdcfg[13], reg13);
  323. }
  324. /* Check RCW field IIC5 to enable dspi2 DT nodei
  325. * dspi2: IIC5 = 3
  326. */
  327. iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  328. & FSL_CHASSIS3_IIC5_PMUX_MASK;
  329. iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
  330. if (iic5_pmux == IIC5_PMUX_SPI3) {
  331. /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
  332. reg11 = QIXIS_READ(brdcfg[11]);
  333. reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
  334. QIXIS_WRITE(brdcfg[11], reg11);
  335. /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
  336. * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
  337. * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
  338. */
  339. reg11 = QIXIS_READ(brdcfg[11]);
  340. reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
  341. QIXIS_WRITE(brdcfg[11], reg11);
  342. } else {
  343. /* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
  344. reg11 = QIXIS_READ(brdcfg[11]);
  345. reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
  346. QIXIS_WRITE(brdcfg[11], reg11);
  347. /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
  348. * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
  349. * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
  350. */
  351. reg11 = QIXIS_READ(brdcfg[11]);
  352. reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
  353. QIXIS_WRITE(brdcfg[11], reg11);
  354. }
  355. return 0;
  356. }
  357. #else
  358. int config_board_mux(void)
  359. {
  360. return 0;
  361. }
  362. #endif
  363. unsigned long get_board_sys_clk(void)
  364. {
  365. #ifdef CONFIG_TARGET_LX2160AQDS
  366. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  367. switch (sysclk_conf & 0x03) {
  368. case QIXIS_SYSCLK_100:
  369. return 100000000;
  370. case QIXIS_SYSCLK_125:
  371. return 125000000;
  372. case QIXIS_SYSCLK_133:
  373. return 133333333;
  374. }
  375. return 100000000;
  376. #else
  377. return 100000000;
  378. #endif
  379. }
  380. unsigned long get_board_ddr_clk(void)
  381. {
  382. #ifdef CONFIG_TARGET_LX2160AQDS
  383. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  384. switch ((ddrclk_conf & 0x30) >> 4) {
  385. case QIXIS_DDRCLK_100:
  386. return 100000000;
  387. case QIXIS_DDRCLK_125:
  388. return 125000000;
  389. case QIXIS_DDRCLK_133:
  390. return 133333333;
  391. }
  392. return 100000000;
  393. #else
  394. return 100000000;
  395. #endif
  396. }
  397. int board_init(void)
  398. {
  399. #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
  400. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  401. #endif
  402. #ifdef CONFIG_ENV_IS_NOWHERE
  403. gd->env_addr = (ulong)&default_environment[0];
  404. #endif
  405. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  406. #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
  407. /* invert AQR107 IRQ pins polarity */
  408. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
  409. #endif
  410. #ifdef CONFIG_FSL_CAAM
  411. sec_init();
  412. #endif
  413. return 0;
  414. }
  415. void detail_board_ddr_info(void)
  416. {
  417. int i;
  418. u64 ddr_size = 0;
  419. puts("\nDDR ");
  420. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  421. ddr_size += gd->bd->bi_dram[i].size;
  422. print_size(ddr_size, "");
  423. print_ddr_info(0);
  424. }
  425. #if defined(CONFIG_ARCH_MISC_INIT)
  426. int arch_misc_init(void)
  427. {
  428. config_board_mux();
  429. return 0;
  430. }
  431. #endif
  432. #ifdef CONFIG_FSL_MC_ENET
  433. extern int fdt_fixup_board_phy(void *fdt);
  434. void fdt_fixup_board_enet(void *fdt)
  435. {
  436. int offset;
  437. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  438. if (offset < 0)
  439. offset = fdt_path_offset(fdt, "/fsl-mc");
  440. if (offset < 0) {
  441. printf("%s: fsl-mc node not found in device tree (error %d)\n",
  442. __func__, offset);
  443. return;
  444. }
  445. if (get_mc_boot_status() == 0 &&
  446. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
  447. fdt_status_okay(fdt, offset);
  448. fdt_fixup_board_phy(fdt);
  449. } else {
  450. fdt_status_fail(fdt, offset);
  451. }
  452. }
  453. void board_quiesce_devices(void)
  454. {
  455. fsl_mc_ldpaa_exit(gd->bd);
  456. }
  457. #endif
  458. #ifdef CONFIG_OF_BOARD_SETUP
  459. int ft_board_setup(void *blob, bd_t *bd)
  460. {
  461. int i;
  462. u64 base[CONFIG_NR_DRAM_BANKS];
  463. u64 size[CONFIG_NR_DRAM_BANKS];
  464. ft_cpu_setup(blob, bd);
  465. /* fixup DT for the three GPP DDR banks */
  466. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  467. base[i] = gd->bd->bi_dram[i].start;
  468. size[i] = gd->bd->bi_dram[i].size;
  469. }
  470. #ifdef CONFIG_RESV_RAM
  471. /* reduce size if reserved memory is within this bank */
  472. if (gd->arch.resv_ram >= base[0] &&
  473. gd->arch.resv_ram < base[0] + size[0])
  474. size[0] = gd->arch.resv_ram - base[0];
  475. else if (gd->arch.resv_ram >= base[1] &&
  476. gd->arch.resv_ram < base[1] + size[1])
  477. size[1] = gd->arch.resv_ram - base[1];
  478. else if (gd->arch.resv_ram >= base[2] &&
  479. gd->arch.resv_ram < base[2] + size[2])
  480. size[2] = gd->arch.resv_ram - base[2];
  481. #endif
  482. fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
  483. #ifdef CONFIG_USB
  484. fsl_fdt_fixup_dr_usb(blob, bd);
  485. #endif
  486. #ifdef CONFIG_FSL_MC_ENET
  487. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  488. fdt_fixup_board_enet(blob);
  489. #endif
  490. return 0;
  491. }
  492. #endif
  493. void qixis_dump_switch(void)
  494. {
  495. int i, nr_of_cfgsw;
  496. QIXIS_WRITE(cms[0], 0x00);
  497. nr_of_cfgsw = QIXIS_READ(cms[1]);
  498. puts("DIP switch settings dump:\n");
  499. for (i = 1; i <= nr_of_cfgsw; i++) {
  500. QIXIS_WRITE(cms[0], i);
  501. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  502. }
  503. }