ls2080aqds.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <malloc.h>
  8. #include <errno.h>
  9. #include <netdev.h>
  10. #include <fsl_ifc.h>
  11. #include <fsl_ddr.h>
  12. #include <asm/io.h>
  13. #include <fdt_support.h>
  14. #include <linux/libfdt.h>
  15. #include <fsl-mc/fsl_mc.h>
  16. #include <env_internal.h>
  17. #include <i2c.h>
  18. #include <rtc.h>
  19. #include <asm/arch/soc.h>
  20. #include <hwconfig.h>
  21. #include <fsl_sec.h>
  22. #include <asm/arch/ppa.h>
  23. #include "../common/qixis.h"
  24. #include "ls2080aqds_qixis.h"
  25. #include "../common/vid.h"
  26. #define PIN_MUX_SEL_SDHC 0x00
  27. #define PIN_MUX_SEL_DSPI 0x0a
  28. #define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
  29. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  30. DECLARE_GLOBAL_DATA_PTR;
  31. enum {
  32. MUX_TYPE_SDHC,
  33. MUX_TYPE_DSPI,
  34. };
  35. unsigned long long get_qixis_addr(void)
  36. {
  37. unsigned long long addr;
  38. if (gd->flags & GD_FLG_RELOC)
  39. addr = QIXIS_BASE_PHYS;
  40. else
  41. addr = QIXIS_BASE_PHYS_EARLY;
  42. /*
  43. * IFC address under 256MB is mapped to 0x30000000, any address above
  44. * is mapped to 0x5_10000000 up to 4GB.
  45. */
  46. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  47. return addr;
  48. }
  49. int checkboard(void)
  50. {
  51. char buf[64];
  52. u8 sw;
  53. static const char *const freq[] = {"100", "125", "156.25",
  54. "100 separate SSCG"};
  55. int clock;
  56. cpu_name(buf);
  57. printf("Board: %s-QDS, ", buf);
  58. sw = QIXIS_READ(arch);
  59. printf("Board Arch: V%d, ", sw >> 4);
  60. printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  61. memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  62. sw = QIXIS_READ(brdcfg[0]);
  63. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  64. if (sw < 0x8)
  65. printf("vBank: %d\n", sw);
  66. else if (sw == 0x8)
  67. puts("PromJet\n");
  68. else if (sw == 0x9)
  69. puts("NAND\n");
  70. else if (sw == 0xf)
  71. puts("QSPI\n");
  72. else if (sw == 0x15)
  73. printf("IFCCard\n");
  74. else
  75. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  76. printf("FPGA: v%d (%s), build %d",
  77. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  78. (int)qixis_read_minor());
  79. /* the timestamp string contains "\n" at the end */
  80. printf(" on %s", qixis_read_time(buf));
  81. /*
  82. * Display the actual SERDES reference clocks as configured by the
  83. * dip switches on the board. Note that the SWx registers could
  84. * technically be set to force the reference clocks to match the
  85. * values that the SERDES expects (or vice versa). For now, however,
  86. * we just display both values and hope the user notices when they
  87. * don't match.
  88. */
  89. puts("SERDES1 Reference : ");
  90. sw = QIXIS_READ(brdcfg[2]);
  91. clock = (sw >> 6) & 3;
  92. printf("Clock1 = %sMHz ", freq[clock]);
  93. clock = (sw >> 4) & 3;
  94. printf("Clock2 = %sMHz", freq[clock]);
  95. puts("\nSERDES2 Reference : ");
  96. clock = (sw >> 2) & 3;
  97. printf("Clock1 = %sMHz ", freq[clock]);
  98. clock = (sw >> 0) & 3;
  99. printf("Clock2 = %sMHz\n", freq[clock]);
  100. return 0;
  101. }
  102. unsigned long get_board_sys_clk(void)
  103. {
  104. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  105. switch (sysclk_conf & 0x0F) {
  106. case QIXIS_SYSCLK_83:
  107. return 83333333;
  108. case QIXIS_SYSCLK_100:
  109. return 100000000;
  110. case QIXIS_SYSCLK_125:
  111. return 125000000;
  112. case QIXIS_SYSCLK_133:
  113. return 133333333;
  114. case QIXIS_SYSCLK_150:
  115. return 150000000;
  116. case QIXIS_SYSCLK_160:
  117. return 160000000;
  118. case QIXIS_SYSCLK_166:
  119. return 166666666;
  120. }
  121. return 66666666;
  122. }
  123. unsigned long get_board_ddr_clk(void)
  124. {
  125. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  126. switch ((ddrclk_conf & 0x30) >> 4) {
  127. case QIXIS_DDRCLK_100:
  128. return 100000000;
  129. case QIXIS_DDRCLK_125:
  130. return 125000000;
  131. case QIXIS_DDRCLK_133:
  132. return 133333333;
  133. }
  134. return 66666666;
  135. }
  136. int select_i2c_ch_pca9547(u8 ch)
  137. {
  138. int ret;
  139. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  140. if (ret) {
  141. puts("PCA: failed to select proper channel\n");
  142. return ret;
  143. }
  144. return 0;
  145. }
  146. int config_board_mux(int ctrl_type)
  147. {
  148. u8 reg5;
  149. reg5 = QIXIS_READ(brdcfg[5]);
  150. switch (ctrl_type) {
  151. case MUX_TYPE_SDHC:
  152. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
  153. break;
  154. case MUX_TYPE_DSPI:
  155. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
  156. break;
  157. default:
  158. printf("Wrong mux interface type\n");
  159. return -1;
  160. }
  161. QIXIS_WRITE(brdcfg[5], reg5);
  162. return 0;
  163. }
  164. int board_init(void)
  165. {
  166. char *env_hwconfig;
  167. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  168. u32 val;
  169. init_final_memctl_regs();
  170. val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
  171. env_hwconfig = env_get("hwconfig");
  172. if (hwconfig_f("dspi", env_hwconfig) &&
  173. DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
  174. config_board_mux(MUX_TYPE_DSPI);
  175. else
  176. config_board_mux(MUX_TYPE_SDHC);
  177. #if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
  178. val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  179. if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  180. QIXIS_WRITE(brdcfg[9],
  181. (QIXIS_READ(brdcfg[9]) & 0xf8) |
  182. FSL_QIXIS_BRDCFG9_QSPI);
  183. #endif
  184. #ifdef CONFIG_ENV_IS_NOWHERE
  185. gd->env_addr = (ulong)&default_environment[0];
  186. #endif
  187. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  188. rtc_enable_32khz_output();
  189. #ifdef CONFIG_FSL_CAAM
  190. sec_init();
  191. #endif
  192. #ifdef CONFIG_FSL_LS_PPA
  193. ppa_init();
  194. #endif
  195. return 0;
  196. }
  197. int board_early_init_f(void)
  198. {
  199. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  200. i2c_early_init_f();
  201. #endif
  202. fsl_lsch3_early_init_f();
  203. #ifdef CONFIG_FSL_QSPI
  204. /* input clk: 1/2 platform clk, output: input/20 */
  205. out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
  206. #endif
  207. return 0;
  208. }
  209. int misc_init_r(void)
  210. {
  211. if (adjust_vdd(0))
  212. printf("Warning: Adjusting core voltage failed.\n");
  213. return 0;
  214. }
  215. void detail_board_ddr_info(void)
  216. {
  217. puts("\nDDR ");
  218. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  219. print_ddr_info(0);
  220. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  221. if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
  222. puts("\nDP-DDR ");
  223. print_size(gd->bd->bi_dram[2].size, "");
  224. print_ddr_info(CONFIG_DP_DDR_CTRL);
  225. }
  226. #endif
  227. }
  228. #if defined(CONFIG_ARCH_MISC_INIT)
  229. int arch_misc_init(void)
  230. {
  231. return 0;
  232. }
  233. #endif
  234. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  235. void fdt_fixup_board_enet(void *fdt)
  236. {
  237. int offset;
  238. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  239. if (offset < 0)
  240. offset = fdt_path_offset(fdt, "/fsl-mc");
  241. if (offset < 0) {
  242. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  243. __func__, offset);
  244. return;
  245. }
  246. if (get_mc_boot_status() == 0 &&
  247. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  248. fdt_status_okay(fdt, offset);
  249. else
  250. fdt_status_fail(fdt, offset);
  251. }
  252. void board_quiesce_devices(void)
  253. {
  254. fsl_mc_ldpaa_exit(gd->bd);
  255. }
  256. #endif
  257. #ifdef CONFIG_OF_BOARD_SETUP
  258. int ft_board_setup(void *blob, bd_t *bd)
  259. {
  260. u64 base[CONFIG_NR_DRAM_BANKS];
  261. u64 size[CONFIG_NR_DRAM_BANKS];
  262. ft_cpu_setup(blob, bd);
  263. /* fixup DT for the two GPP DDR banks */
  264. base[0] = gd->bd->bi_dram[0].start;
  265. size[0] = gd->bd->bi_dram[0].size;
  266. base[1] = gd->bd->bi_dram[1].start;
  267. size[1] = gd->bd->bi_dram[1].size;
  268. #ifdef CONFIG_RESV_RAM
  269. /* reduce size if reserved memory is within this bank */
  270. if (gd->arch.resv_ram >= base[0] &&
  271. gd->arch.resv_ram < base[0] + size[0])
  272. size[0] = gd->arch.resv_ram - base[0];
  273. else if (gd->arch.resv_ram >= base[1] &&
  274. gd->arch.resv_ram < base[1] + size[1])
  275. size[1] = gd->arch.resv_ram - base[1];
  276. #endif
  277. fdt_fixup_memory_banks(blob, base, size, 2);
  278. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  279. fsl_fdt_fixup_dr_usb(blob, bd);
  280. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  281. fdt_fixup_board_enet(blob);
  282. #endif
  283. return 0;
  284. }
  285. #endif
  286. void qixis_dump_switch(void)
  287. {
  288. int i, nr_of_cfgsw;
  289. QIXIS_WRITE(cms[0], 0x00);
  290. nr_of_cfgsw = QIXIS_READ(cms[1]);
  291. puts("DIP switch settings dump:\n");
  292. for (i = 1; i <= nr_of_cfgsw; i++) {
  293. QIXIS_WRITE(cms[0], i);
  294. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  295. }
  296. }