ls1028a.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <errno.h>
  8. #include <fsl_ddr.h>
  9. #include <asm/io.h>
  10. #include <hwconfig.h>
  11. #include <fdt_support.h>
  12. #include <linux/libfdt.h>
  13. #include <env_internal.h>
  14. #include <asm/arch-fsl-layerscape/soc.h>
  15. #include <i2c.h>
  16. #include <asm/arch/soc.h>
  17. #ifdef CONFIG_FSL_LS_PPA
  18. #include <asm/arch/ppa.h>
  19. #endif
  20. #include <fsl_immap.h>
  21. #include <netdev.h>
  22. #include <fdtdec.h>
  23. #include <miiphy.h>
  24. #include "../common/qixis.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. int config_board_mux(void)
  27. {
  28. #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  29. u8 reg;
  30. reg = QIXIS_READ(brdcfg[13]);
  31. /* Field| Function
  32. * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
  33. * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  34. * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
  35. * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  36. */
  37. reg &= ~(0xf0);
  38. reg |= 0xb0;
  39. QIXIS_WRITE(brdcfg[13], reg);
  40. reg = QIXIS_READ(brdcfg[15]);
  41. /* Field| Function
  42. * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  43. * CAN1 | 0= CAN #1 transceiver enabled
  44. * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  45. * CAN2 | 0= CAN #2 transceiver enabled
  46. */
  47. reg &= ~(0xc0);
  48. QIXIS_WRITE(brdcfg[15], reg);
  49. #endif
  50. return 0;
  51. }
  52. int board_init(void)
  53. {
  54. #ifdef CONFIG_ENV_IS_NOWHERE
  55. gd->env_addr = (ulong)&default_environment[0];
  56. #endif
  57. #ifdef CONFIG_FSL_LS_PPA
  58. ppa_init();
  59. #endif
  60. #ifndef CONFIG_SYS_EARLY_PCI_INIT
  61. pci_init();
  62. #endif
  63. #if defined(CONFIG_TARGET_LS1028ARDB)
  64. u8 val = I2C_MUX_CH_DEFAULT;
  65. i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  66. #endif
  67. return 0;
  68. }
  69. int board_eth_init(bd_t *bis)
  70. {
  71. return pci_eth_init(bis);
  72. }
  73. #if defined(CONFIG_ARCH_MISC_INIT)
  74. int arch_misc_init(void)
  75. {
  76. config_board_mux();
  77. return 0;
  78. }
  79. #endif
  80. int board_early_init_f(void)
  81. {
  82. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  83. i2c_early_init_f();
  84. #endif
  85. fsl_lsch3_early_init_f();
  86. return 0;
  87. }
  88. void detail_board_ddr_info(void)
  89. {
  90. puts("\nDDR ");
  91. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  92. print_ddr_info(0);
  93. }
  94. #ifdef CONFIG_OF_BOARD_SETUP
  95. int ft_board_setup(void *blob, bd_t *bd)
  96. {
  97. u64 base[CONFIG_NR_DRAM_BANKS];
  98. u64 size[CONFIG_NR_DRAM_BANKS];
  99. ft_cpu_setup(blob, bd);
  100. /* fixup DT for the two GPP DDR banks */
  101. base[0] = gd->bd->bi_dram[0].start;
  102. size[0] = gd->bd->bi_dram[0].size;
  103. base[1] = gd->bd->bi_dram[1].start;
  104. size[1] = gd->bd->bi_dram[1].size;
  105. #ifdef CONFIG_RESV_RAM
  106. /* reduce size if reserved memory is within this bank */
  107. if (gd->arch.resv_ram >= base[0] &&
  108. gd->arch.resv_ram < base[0] + size[0])
  109. size[0] = gd->arch.resv_ram - base[0];
  110. else if (gd->arch.resv_ram >= base[1] &&
  111. gd->arch.resv_ram < base[1] + size[1])
  112. size[1] = gd->arch.resv_ram - base[1];
  113. #endif
  114. fdt_fixup_memory_banks(blob, base, size, 2);
  115. return 0;
  116. }
  117. #endif
  118. #ifdef CONFIG_FSL_QIXIS
  119. int checkboard(void)
  120. {
  121. #ifdef CONFIG_TFABOOT
  122. enum boot_src src = get_boot_src();
  123. #endif
  124. u8 sw;
  125. int clock;
  126. char *board;
  127. char buf[64] = {0};
  128. static const char *freq[6] = {"100.00", "125.00", "156.25",
  129. "161.13", "322.26", "100.00 SS"};
  130. cpu_name(buf);
  131. /* find the board details */
  132. sw = QIXIS_READ(id);
  133. switch (sw) {
  134. case 0x46:
  135. board = "QDS";
  136. break;
  137. case 0x47:
  138. board = "RDB";
  139. break;
  140. case 0x49:
  141. board = "HSSI";
  142. break;
  143. default:
  144. board = "unknown";
  145. break;
  146. }
  147. sw = QIXIS_READ(arch);
  148. printf("Board: %s-%s, Version: %c, boot from ",
  149. buf, board, (sw & 0xf) + 'A' - 1);
  150. sw = QIXIS_READ(brdcfg[0]);
  151. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  152. #ifdef CONFIG_TFABOOT
  153. if (src == BOOT_SOURCE_SD_MMC) {
  154. puts("SD\n");
  155. } else if (src == BOOT_SOURCE_SD_MMC2) {
  156. puts("eMMC\n");
  157. } else {
  158. #endif
  159. #ifdef CONFIG_SD_BOOT
  160. puts("SD\n");
  161. #elif defined(CONFIG_EMMC_BOOT)
  162. puts("eMMC\n");
  163. #else
  164. switch (sw) {
  165. case 0:
  166. case 4:
  167. printf("NOR\n");
  168. break;
  169. case 1:
  170. printf("NAND\n");
  171. break;
  172. default:
  173. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  174. break;
  175. }
  176. #endif
  177. #ifdef CONFIG_TFABOOT
  178. }
  179. #endif
  180. printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
  181. puts("SERDES1 Reference : ");
  182. sw = QIXIS_READ(brdcfg[2]);
  183. #ifdef CONFIG_TARGET_LS1028ARDB
  184. clock = (sw >> 6) & 3;
  185. #else
  186. clock = (sw >> 4) & 0xf;
  187. #endif
  188. printf("Clock1 = %sMHz ", freq[clock]);
  189. #ifdef CONFIG_TARGET_LS1028ARDB
  190. clock = (sw >> 4) & 3;
  191. #else
  192. clock = sw & 0xf;
  193. #endif
  194. printf("Clock2 = %sMHz\n", freq[clock]);
  195. return 0;
  196. }
  197. #endif