ls1012aqds.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <fdt_support.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #ifdef CONFIG_FSL_LS_PPA
  12. #include <asm/arch/ppa.h>
  13. #endif
  14. #include <asm/arch/fdt.h>
  15. #include <asm/arch/mmu.h>
  16. #include <asm/arch/soc.h>
  17. #include <ahci.h>
  18. #include <hwconfig.h>
  19. #include <mmc.h>
  20. #include <env_internal.h>
  21. #include <scsi.h>
  22. #include <fm_eth.h>
  23. #include <fsl_esdhc.h>
  24. #include <fsl_mmdc.h>
  25. #include <spl.h>
  26. #include <netdev.h>
  27. #include <fsl_sec.h>
  28. #include "../common/qixis.h"
  29. #include "ls1012aqds_qixis.h"
  30. #include "ls1012aqds_pfe.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. int checkboard(void)
  33. {
  34. char buf[64];
  35. u8 sw;
  36. sw = QIXIS_READ(arch);
  37. printf("Board Arch: V%d, ", sw >> 4);
  38. printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  39. sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
  40. if (sw & QIXIS_LBMAP_ALTBANK)
  41. printf("flash: 2\n");
  42. else
  43. printf("flash: 1\n");
  44. printf("FPGA: v%d (%s), build %d",
  45. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  46. (int)qixis_read_minor());
  47. /* the timestamp string contains "\n" at the end */
  48. printf(" on %s", qixis_read_time(buf));
  49. return 0;
  50. }
  51. #ifdef CONFIG_TFABOOT
  52. int dram_init(void)
  53. {
  54. gd->ram_size = tfa_get_dram_size();
  55. if (!gd->ram_size)
  56. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  57. return 0;
  58. }
  59. #else
  60. int dram_init(void)
  61. {
  62. static const struct fsl_mmdc_info mparam = {
  63. 0x05180000, /* mdctl */
  64. 0x00030035, /* mdpdc */
  65. 0x12554000, /* mdotc */
  66. 0xbabf7954, /* mdcfg0 */
  67. 0xdb328f64, /* mdcfg1 */
  68. 0x01ff00db, /* mdcfg2 */
  69. 0x00001680, /* mdmisc */
  70. 0x0f3c8000, /* mdref */
  71. 0x00002000, /* mdrwd */
  72. 0x00bf1023, /* mdor */
  73. 0x0000003f, /* mdasp */
  74. 0x0000022a, /* mpodtctrl */
  75. 0xa1390003, /* mpzqhwctrl */
  76. };
  77. mmdc_init(&mparam);
  78. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  79. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  80. /* This will break-before-make MMU for DDR */
  81. update_early_mmu_table();
  82. #endif
  83. return 0;
  84. }
  85. #endif
  86. int board_early_init_f(void)
  87. {
  88. fsl_lsch2_early_init_f();
  89. return 0;
  90. }
  91. #ifdef CONFIG_MISC_INIT_R
  92. int misc_init_r(void)
  93. {
  94. u8 mux_sdhc_cd = 0x80;
  95. i2c_set_bus_num(0);
  96. i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
  97. return 0;
  98. }
  99. #endif
  100. int board_init(void)
  101. {
  102. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  103. CONFIG_SYS_CCI400_OFFSET);
  104. /* Set CCI-400 control override register to enable barrier
  105. * transaction */
  106. if (current_el() == 3)
  107. out_le32(&cci->ctrl_ord,
  108. CCI400_CTRLORD_EN_BARRIER);
  109. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  110. erratum_a010315();
  111. #endif
  112. #ifdef CONFIG_ENV_IS_NOWHERE
  113. gd->env_addr = (ulong)&default_environment[0];
  114. #endif
  115. #ifdef CONFIG_FSL_CAAM
  116. sec_init();
  117. #endif
  118. #ifdef CONFIG_FSL_LS_PPA
  119. ppa_init();
  120. #endif
  121. return 0;
  122. }
  123. int esdhc_status_fixup(void *blob, const char *compat)
  124. {
  125. char esdhc0_path[] = "/soc/esdhc@1560000";
  126. char esdhc1_path[] = "/soc/esdhc@1580000";
  127. u8 card_id;
  128. do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  129. sizeof("okay"), 1);
  130. /*
  131. * The Presence Detect 2 register detects the installation
  132. * of cards in various PCI Express or SGMII slots.
  133. *
  134. * STAT_PRS2[7:5]: Specifies the type of card installed in the
  135. * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
  136. */
  137. card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
  138. /* If no adapter is installed in SDHC2, disable SDHC2 */
  139. if (card_id == 0x7)
  140. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  141. sizeof("disabled"), 1);
  142. else
  143. do_fixup_by_path(blob, esdhc1_path, "status", "okay",
  144. sizeof("okay"), 1);
  145. return 0;
  146. }
  147. static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
  148. char *enet_path, char *mdio_path)
  149. {
  150. do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
  151. &prop_val.busid, PFE_PROP_LEN, 1);
  152. do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
  153. &prop_val.phyid, PFE_PROP_LEN, 1);
  154. do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
  155. &prop_val.mux_val, PFE_PROP_LEN, 1);
  156. do_fixup_by_path(set_blob, enet_path, "phy-mode",
  157. prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
  158. do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
  159. &prop_val.phy_mask, PFE_PROP_LEN, 1);
  160. return 0;
  161. }
  162. static void fdt_fsl_fixup_of_pfe(void *blob)
  163. {
  164. int i = 0;
  165. struct pfe_prop_val prop_val;
  166. void *l_blob = blob;
  167. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  168. unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
  169. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  170. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  171. for (i = 0; i < NUM_ETH_NODE; i++) {
  172. switch (srds_s1) {
  173. case SERDES_1_G_PROTOCOL:
  174. if (i == 0) {
  175. prop_val.busid = cpu_to_fdt32(
  176. ETH_1_1G_BUS_ID);
  177. prop_val.phyid = cpu_to_fdt32(
  178. ETH_1_1G_PHY_ID);
  179. prop_val.mux_val = cpu_to_fdt32(
  180. ETH_1_1G_MDIO_MUX);
  181. prop_val.phy_mask = cpu_to_fdt32(
  182. ETH_1G_MDIO_PHY_MASK);
  183. prop_val.phy_mode = "sgmii";
  184. pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
  185. ETH_1_MDIO);
  186. } else {
  187. prop_val.busid = cpu_to_fdt32(
  188. ETH_2_1G_BUS_ID);
  189. prop_val.phyid = cpu_to_fdt32(
  190. ETH_2_1G_PHY_ID);
  191. prop_val.mux_val = cpu_to_fdt32(
  192. ETH_2_1G_MDIO_MUX);
  193. prop_val.phy_mask = cpu_to_fdt32(
  194. ETH_1G_MDIO_PHY_MASK);
  195. prop_val.phy_mode = "rgmii";
  196. pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
  197. ETH_2_MDIO);
  198. }
  199. break;
  200. case SERDES_2_5_G_PROTOCOL:
  201. if (i == 0) {
  202. prop_val.busid = cpu_to_fdt32(
  203. ETH_1_2_5G_BUS_ID);
  204. prop_val.phyid = cpu_to_fdt32(
  205. ETH_1_2_5G_PHY_ID);
  206. prop_val.mux_val = cpu_to_fdt32(
  207. ETH_1_2_5G_MDIO_MUX);
  208. prop_val.phy_mask = cpu_to_fdt32(
  209. ETH_2_5G_MDIO_PHY_MASK);
  210. prop_val.phy_mode = "sgmii-2500";
  211. pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
  212. ETH_1_MDIO);
  213. } else {
  214. prop_val.busid = cpu_to_fdt32(
  215. ETH_2_2_5G_BUS_ID);
  216. prop_val.phyid = cpu_to_fdt32(
  217. ETH_2_2_5G_PHY_ID);
  218. prop_val.mux_val = cpu_to_fdt32(
  219. ETH_2_2_5G_MDIO_MUX);
  220. prop_val.phy_mask = cpu_to_fdt32(
  221. ETH_2_5G_MDIO_PHY_MASK);
  222. prop_val.phy_mode = "sgmii-2500";
  223. pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
  224. ETH_2_MDIO);
  225. }
  226. break;
  227. default:
  228. printf("serdes:[%d]\n", srds_s1);
  229. }
  230. }
  231. }
  232. #ifdef CONFIG_OF_BOARD_SETUP
  233. int ft_board_setup(void *blob, bd_t *bd)
  234. {
  235. arch_fixup_fdt(blob);
  236. ft_cpu_setup(blob, bd);
  237. fdt_fsl_fixup_of_pfe(blob);
  238. return 0;
  239. }
  240. #endif