board.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Bosch Guardian
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  9. */
  10. #include <common.h>
  11. #include <cpsw.h>
  12. #include <dm.h>
  13. #include <env_internal.h>
  14. #include <errno.h>
  15. #include <i2c.h>
  16. #include <miiphy.h>
  17. #include <panel.h>
  18. #include <power/tps65217.h>
  19. #include <power/tps65910.h>
  20. #include <spl.h>
  21. #include <watchdog.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/cpu.h>
  24. #include <asm/arch/ddr_defs.h>
  25. #include <asm/arch/gpio.h>
  26. #include <asm/arch/hardware.h>
  27. #include <asm/arch/mem.h>
  28. #include <asm/arch/mmc_host_def.h>
  29. #include <asm/arch/omap.h>
  30. #include <asm/arch/sys_proto.h>
  31. #include <asm/emif.h>
  32. #include <asm/gpio.h>
  33. #include <asm/io.h>
  34. #include "board.h"
  35. DECLARE_GLOBAL_DATA_PTR;
  36. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  37. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  38. static const struct ddr_data ddr3_data = {
  39. .datardsratio0 = MT41K128M16JT125K_RD_DQS,
  40. .datawdsratio0 = MT41K128M16JT125K_WR_DQS,
  41. .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
  42. .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
  43. };
  44. static const struct cmd_control ddr3_cmd_ctrl_data = {
  45. .cmd0csratio = MT41K128M16JT125K_RATIO,
  46. .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  47. .cmd1csratio = MT41K128M16JT125K_RATIO,
  48. .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  49. .cmd2csratio = MT41K128M16JT125K_RATIO,
  50. .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  51. };
  52. static struct emif_regs ddr3_emif_reg_data = {
  53. .sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
  54. .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
  55. .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
  56. .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
  57. .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
  58. .zq_config = MT41K128M16JT125K_ZQ_CFG,
  59. .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
  60. };
  61. #define OSC (V_OSCK / 1000000)
  62. const struct dpll_params dpll_ddr = {
  63. 400, OSC - 1, 1, -1, -1, -1, -1};
  64. void am33xx_spl_board_init(void)
  65. {
  66. int mpu_vdd;
  67. int usb_cur_lim;
  68. /* Get the frequency */
  69. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  70. if (i2c_probe(TPS65217_CHIP_PM))
  71. return;
  72. /*
  73. * Increase USB current limit to 1300mA or 1800mA and set
  74. * the MPU voltage controller as needed.
  75. */
  76. if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  77. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  78. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  79. } else {
  80. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  81. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  82. }
  83. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  84. TPS65217_POWER_PATH,
  85. usb_cur_lim,
  86. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  87. puts("tps65217_reg_write failure\n");
  88. /* Set DCDC3 (CORE) voltage to 1.125V */
  89. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  90. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  91. puts("tps65217_voltage_update failure\n");
  92. return;
  93. }
  94. /* Set CORE Frequencies to OPP100 */
  95. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  96. /* Set DCDC2 (MPU) voltage */
  97. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  98. puts("tps65217_voltage_update failure\n");
  99. return;
  100. }
  101. /*
  102. * Set LDO3 to 1.8V and LDO4 to 3.3V
  103. */
  104. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  105. TPS65217_DEFLS1,
  106. TPS65217_LDO_VOLTAGE_OUT_1_8,
  107. TPS65217_LDO_MASK))
  108. puts("tps65217_reg_write failure\n");
  109. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  110. TPS65217_DEFLS2,
  111. TPS65217_LDO_VOLTAGE_OUT_3_3,
  112. TPS65217_LDO_MASK))
  113. puts("tps65217_reg_write failure\n");
  114. /* Set MPU Frequency to what we detected now that voltages are set */
  115. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  116. }
  117. const struct dpll_params *get_dpll_ddr_params(void)
  118. {
  119. enable_i2c0_pin_mux();
  120. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  121. return &dpll_ddr;
  122. }
  123. void set_uart_mux_conf(void)
  124. {
  125. enable_uart0_pin_mux();
  126. }
  127. void set_mux_conf_regs(void)
  128. {
  129. enable_board_pin_mux();
  130. }
  131. const struct ctrl_ioregs ioregs = {
  132. .cm0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  133. .cm1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  134. .cm2ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  135. .dt0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  136. .dt1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  137. };
  138. void sdram_init(void)
  139. {
  140. config_ddr(400, &ioregs,
  141. &ddr3_data,
  142. &ddr3_cmd_ctrl_data,
  143. &ddr3_emif_reg_data, 0);
  144. }
  145. #endif
  146. int board_init(void)
  147. {
  148. #if defined(CONFIG_HW_WATCHDOG)
  149. hw_watchdog_init();
  150. #endif
  151. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  152. #ifdef CONFIG_NAND
  153. gpmc_init();
  154. #endif
  155. return 0;
  156. }