cpu.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <asm/io.h>
  10. #include <linux/errno.h>
  11. #include <asm/system.h>
  12. #include <fm_eth.h>
  13. #include <asm/armv8/mmu.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/fsl_serdes.h>
  16. #include <asm/arch/soc.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/speed.h>
  19. #include <fsl_immap.h>
  20. #include <asm/arch/mp.h>
  21. #include <efi_loader.h>
  22. #include <fsl-mc/fsl_mc.h>
  23. #ifdef CONFIG_FSL_ESDHC
  24. #include <fsl_esdhc.h>
  25. #endif
  26. #include <asm/armv8/sec_firmware.h>
  27. #ifdef CONFIG_SYS_FSL_DDR
  28. #include <fsl_ddr.h>
  29. #endif
  30. #include <asm/arch/clock.h>
  31. #include <hwconfig.h>
  32. #include <fsl_qbman.h>
  33. #ifdef CONFIG_TFABOOT
  34. #include <env_internal.h>
  35. #ifdef CONFIG_CHAIN_OF_TRUST
  36. #include <fsl_validate.h>
  37. #endif
  38. #endif
  39. DECLARE_GLOBAL_DATA_PTR;
  40. static struct cpu_type cpu_type_list[] = {
  41. CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  42. CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  43. CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  44. CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  45. CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  46. CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  47. CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  48. CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  49. CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  50. CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  51. CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
  52. CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  53. CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
  54. CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  55. CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  56. CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  57. CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  58. CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
  59. CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  60. CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  61. CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  62. CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  63. CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
  64. CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
  65. CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
  66. };
  67. #define EARLY_PGTABLE_SIZE 0x5000
  68. static struct mm_region early_map[] = {
  69. #ifdef CONFIG_FSL_LSCH3
  70. { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  71. CONFIG_SYS_FSL_CCSR_SIZE,
  72. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  73. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  74. },
  75. { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  76. SYS_FSL_OCRAM_SPACE_SIZE,
  77. PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  78. },
  79. { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  80. CONFIG_SYS_FSL_QSPI_SIZE1,
  81. PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
  82. #ifdef CONFIG_FSL_IFC
  83. /* For IFC Region #1, only the first 4MB is cache-enabled */
  84. { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  85. CONFIG_SYS_FSL_IFC_SIZE1_1,
  86. PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  87. },
  88. { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  89. CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  90. CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
  91. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  92. },
  93. { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
  94. CONFIG_SYS_FSL_IFC_SIZE1,
  95. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  96. },
  97. #endif
  98. { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  99. CONFIG_SYS_FSL_DRAM_SIZE1,
  100. #if defined(CONFIG_TFABOOT) || \
  101. (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
  102. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  103. #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
  104. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
  105. #endif
  106. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  107. },
  108. #ifdef CONFIG_FSL_IFC
  109. /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
  110. { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
  111. CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
  112. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  113. },
  114. #endif
  115. { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
  116. CONFIG_SYS_FSL_DCSR_SIZE,
  117. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  118. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  119. },
  120. { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  121. CONFIG_SYS_FSL_DRAM_SIZE2,
  122. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
  123. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  124. },
  125. #ifdef CONFIG_SYS_FSL_DRAM_BASE3
  126. { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
  127. CONFIG_SYS_FSL_DRAM_SIZE3,
  128. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
  129. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  130. },
  131. #endif
  132. #elif defined(CONFIG_FSL_LSCH2)
  133. { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  134. CONFIG_SYS_FSL_CCSR_SIZE,
  135. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  136. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  137. },
  138. { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  139. SYS_FSL_OCRAM_SPACE_SIZE,
  140. PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  141. },
  142. { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
  143. CONFIG_SYS_FSL_DCSR_SIZE,
  144. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  145. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  146. },
  147. { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
  148. CONFIG_SYS_FSL_QSPI_SIZE,
  149. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  150. },
  151. #ifdef CONFIG_FSL_IFC
  152. { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
  153. CONFIG_SYS_FSL_IFC_SIZE,
  154. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  155. },
  156. #endif
  157. { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  158. CONFIG_SYS_FSL_DRAM_SIZE1,
  159. #if defined(CONFIG_TFABOOT) || \
  160. (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
  161. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  162. #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
  163. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
  164. #endif
  165. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  166. },
  167. { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  168. CONFIG_SYS_FSL_DRAM_SIZE2,
  169. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
  170. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  171. },
  172. #endif
  173. {}, /* list terminator */
  174. };
  175. static struct mm_region final_map[] = {
  176. #ifdef CONFIG_FSL_LSCH3
  177. { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  178. CONFIG_SYS_FSL_CCSR_SIZE,
  179. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  180. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  181. },
  182. { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  183. SYS_FSL_OCRAM_SPACE_SIZE,
  184. PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  185. },
  186. { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  187. CONFIG_SYS_FSL_DRAM_SIZE1,
  188. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  189. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  190. },
  191. { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  192. CONFIG_SYS_FSL_QSPI_SIZE1,
  193. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  194. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  195. },
  196. { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
  197. CONFIG_SYS_FSL_QSPI_SIZE2,
  198. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  199. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  200. },
  201. #ifdef CONFIG_FSL_IFC
  202. { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
  203. CONFIG_SYS_FSL_IFC_SIZE2,
  204. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  205. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  206. },
  207. #endif
  208. { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
  209. CONFIG_SYS_FSL_DCSR_SIZE,
  210. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  211. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  212. },
  213. { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
  214. CONFIG_SYS_FSL_MC_SIZE,
  215. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  216. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  217. },
  218. { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
  219. CONFIG_SYS_FSL_NI_SIZE,
  220. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  221. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  222. },
  223. /* For QBMAN portal, only the first 64MB is cache-enabled */
  224. { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
  225. CONFIG_SYS_FSL_QBMAN_SIZE_1,
  226. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  227. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
  228. },
  229. { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
  230. CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
  231. CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
  232. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  233. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  234. },
  235. { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
  236. CONFIG_SYS_PCIE1_PHYS_SIZE,
  237. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  238. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  239. },
  240. { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
  241. CONFIG_SYS_PCIE2_PHYS_SIZE,
  242. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  243. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  244. },
  245. #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
  246. { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
  247. CONFIG_SYS_PCIE3_PHYS_SIZE,
  248. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  249. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  250. },
  251. #endif
  252. #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
  253. { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
  254. CONFIG_SYS_PCIE4_PHYS_SIZE,
  255. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  256. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  257. },
  258. #endif
  259. #ifdef SYS_PCIE5_PHYS_ADDR
  260. { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
  261. SYS_PCIE5_PHYS_SIZE,
  262. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  263. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  264. },
  265. #endif
  266. #ifdef SYS_PCIE6_PHYS_ADDR
  267. { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
  268. SYS_PCIE6_PHYS_SIZE,
  269. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  270. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  271. },
  272. #endif
  273. { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
  274. CONFIG_SYS_FSL_WRIOP1_SIZE,
  275. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  276. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  277. },
  278. { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
  279. CONFIG_SYS_FSL_AIOP1_SIZE,
  280. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  281. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  282. },
  283. { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
  284. CONFIG_SYS_FSL_PEBUF_SIZE,
  285. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  286. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  287. },
  288. { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  289. CONFIG_SYS_FSL_DRAM_SIZE2,
  290. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  291. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  292. },
  293. #ifdef CONFIG_SYS_FSL_DRAM_BASE3
  294. { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
  295. CONFIG_SYS_FSL_DRAM_SIZE3,
  296. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  297. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  298. },
  299. #endif
  300. #elif defined(CONFIG_FSL_LSCH2)
  301. { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
  302. CONFIG_SYS_FSL_BOOTROM_SIZE,
  303. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  304. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  305. },
  306. { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  307. CONFIG_SYS_FSL_CCSR_SIZE,
  308. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  309. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  310. },
  311. { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  312. SYS_FSL_OCRAM_SPACE_SIZE,
  313. PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  314. },
  315. { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
  316. CONFIG_SYS_FSL_DCSR_SIZE,
  317. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  318. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  319. },
  320. { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
  321. CONFIG_SYS_FSL_QSPI_SIZE,
  322. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  323. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  324. },
  325. #ifdef CONFIG_FSL_IFC
  326. { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
  327. CONFIG_SYS_FSL_IFC_SIZE,
  328. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  329. },
  330. #endif
  331. { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  332. CONFIG_SYS_FSL_DRAM_SIZE1,
  333. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  334. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  335. },
  336. { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
  337. CONFIG_SYS_FSL_QBMAN_SIZE,
  338. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  339. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  340. },
  341. { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  342. CONFIG_SYS_FSL_DRAM_SIZE2,
  343. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  344. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  345. },
  346. { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
  347. CONFIG_SYS_PCIE1_PHYS_SIZE,
  348. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  349. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  350. },
  351. { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
  352. CONFIG_SYS_PCIE2_PHYS_SIZE,
  353. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  354. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  355. },
  356. #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
  357. { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
  358. CONFIG_SYS_PCIE3_PHYS_SIZE,
  359. PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  360. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  361. },
  362. #endif
  363. { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
  364. CONFIG_SYS_FSL_DRAM_SIZE3,
  365. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  366. PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
  367. },
  368. #endif
  369. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  370. {}, /* space holder for secure mem */
  371. #endif
  372. {},
  373. };
  374. struct mm_region *mem_map = early_map;
  375. void cpu_name(char *name)
  376. {
  377. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  378. unsigned int i, svr, ver;
  379. svr = gur_in32(&gur->svr);
  380. ver = SVR_SOC_VER(svr);
  381. for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  382. if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
  383. strcpy(name, cpu_type_list[i].name);
  384. #ifdef CONFIG_ARCH_LX2160A
  385. if (IS_C_PROCESSOR(svr))
  386. strcat(name, "C");
  387. #endif
  388. if (IS_E_PROCESSOR(svr))
  389. strcat(name, "E");
  390. sprintf(name + strlen(name), " Rev%d.%d",
  391. SVR_MAJ(svr), SVR_MIN(svr));
  392. break;
  393. }
  394. if (i == ARRAY_SIZE(cpu_type_list))
  395. strcpy(name, "unknown");
  396. }
  397. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  398. /*
  399. * To start MMU before DDR is available, we create MMU table in SRAM.
  400. * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
  401. * levels of translation tables here to cover 40-bit address space.
  402. * We use 4KB granule size, with 40 bits physical address, T0SZ=24
  403. * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
  404. * Note, the debug print in cache_v8.c is not usable for debugging
  405. * these early MMU tables because UART is not yet available.
  406. */
  407. static inline void early_mmu_setup(void)
  408. {
  409. unsigned int el = current_el();
  410. /* global data is already setup, no allocation yet */
  411. if (el == 3)
  412. gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
  413. else
  414. gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
  415. gd->arch.tlb_fillptr = gd->arch.tlb_addr;
  416. gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
  417. /* Create early page tables */
  418. setup_pgtables();
  419. /* point TTBR to the new table */
  420. set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
  421. get_tcr(el, NULL, NULL) &
  422. ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
  423. MEMORY_ATTRIBUTES);
  424. set_sctlr(get_sctlr() | CR_M);
  425. }
  426. static void fix_pcie_mmu_map(void)
  427. {
  428. #ifdef CONFIG_ARCH_LS2080A
  429. unsigned int i;
  430. u32 svr, ver;
  431. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  432. svr = gur_in32(&gur->svr);
  433. ver = SVR_SOC_VER(svr);
  434. /* Fix PCIE base and size for LS2088A */
  435. if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
  436. (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
  437. (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
  438. for (i = 0; i < ARRAY_SIZE(final_map); i++) {
  439. switch (final_map[i].phys) {
  440. case CONFIG_SYS_PCIE1_PHYS_ADDR:
  441. final_map[i].phys = 0x2000000000ULL;
  442. final_map[i].virt = 0x2000000000ULL;
  443. final_map[i].size = 0x800000000ULL;
  444. break;
  445. case CONFIG_SYS_PCIE2_PHYS_ADDR:
  446. final_map[i].phys = 0x2800000000ULL;
  447. final_map[i].virt = 0x2800000000ULL;
  448. final_map[i].size = 0x800000000ULL;
  449. break;
  450. #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
  451. case CONFIG_SYS_PCIE3_PHYS_ADDR:
  452. final_map[i].phys = 0x3000000000ULL;
  453. final_map[i].virt = 0x3000000000ULL;
  454. final_map[i].size = 0x800000000ULL;
  455. break;
  456. #endif
  457. #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
  458. case CONFIG_SYS_PCIE4_PHYS_ADDR:
  459. final_map[i].phys = 0x3800000000ULL;
  460. final_map[i].virt = 0x3800000000ULL;
  461. final_map[i].size = 0x800000000ULL;
  462. break;
  463. #endif
  464. default:
  465. break;
  466. }
  467. }
  468. }
  469. #endif
  470. }
  471. /*
  472. * The final tables look similar to early tables, but different in detail.
  473. * These tables are in DRAM. Sub tables are added to enable cache for
  474. * QBMan and OCRAM.
  475. *
  476. * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
  477. * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
  478. */
  479. static inline void final_mmu_setup(void)
  480. {
  481. u64 tlb_addr_save = gd->arch.tlb_addr;
  482. unsigned int el = current_el();
  483. int index;
  484. /* fix the final_map before filling in the block entries */
  485. fix_pcie_mmu_map();
  486. mem_map = final_map;
  487. /* Update mapping for DDR to actual size */
  488. for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
  489. /*
  490. * Find the entry for DDR mapping and update the address and
  491. * size. Zero-sized mapping will be skipped when creating MMU
  492. * table.
  493. */
  494. switch (final_map[index].virt) {
  495. case CONFIG_SYS_FSL_DRAM_BASE1:
  496. final_map[index].virt = gd->bd->bi_dram[0].start;
  497. final_map[index].phys = gd->bd->bi_dram[0].start;
  498. final_map[index].size = gd->bd->bi_dram[0].size;
  499. break;
  500. #ifdef CONFIG_SYS_FSL_DRAM_BASE2
  501. case CONFIG_SYS_FSL_DRAM_BASE2:
  502. #if (CONFIG_NR_DRAM_BANKS >= 2)
  503. final_map[index].virt = gd->bd->bi_dram[1].start;
  504. final_map[index].phys = gd->bd->bi_dram[1].start;
  505. final_map[index].size = gd->bd->bi_dram[1].size;
  506. #else
  507. final_map[index].size = 0;
  508. #endif
  509. break;
  510. #endif
  511. #ifdef CONFIG_SYS_FSL_DRAM_BASE3
  512. case CONFIG_SYS_FSL_DRAM_BASE3:
  513. #if (CONFIG_NR_DRAM_BANKS >= 3)
  514. final_map[index].virt = gd->bd->bi_dram[2].start;
  515. final_map[index].phys = gd->bd->bi_dram[2].start;
  516. final_map[index].size = gd->bd->bi_dram[2].size;
  517. #else
  518. final_map[index].size = 0;
  519. #endif
  520. break;
  521. #endif
  522. default:
  523. break;
  524. }
  525. }
  526. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  527. if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
  528. if (el == 3) {
  529. /*
  530. * Only use gd->arch.secure_ram if the address is
  531. * recalculated. Align to 4KB for MMU table.
  532. */
  533. /* put page tables in secure ram */
  534. index = ARRAY_SIZE(final_map) - 2;
  535. gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
  536. final_map[index].virt = gd->arch.secure_ram & ~0x3;
  537. final_map[index].phys = final_map[index].virt;
  538. final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
  539. final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
  540. gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
  541. tlb_addr_save = gd->arch.tlb_addr;
  542. } else {
  543. /* Use allocated (board_f.c) memory for TLB */
  544. tlb_addr_save = gd->arch.tlb_allocated;
  545. gd->arch.tlb_addr = tlb_addr_save;
  546. }
  547. }
  548. #endif
  549. /* Reset the fill ptr */
  550. gd->arch.tlb_fillptr = tlb_addr_save;
  551. /* Create normal system page tables */
  552. setup_pgtables();
  553. /* Create emergency page tables */
  554. gd->arch.tlb_addr = gd->arch.tlb_fillptr;
  555. gd->arch.tlb_emerg = gd->arch.tlb_addr;
  556. setup_pgtables();
  557. gd->arch.tlb_addr = tlb_addr_save;
  558. /* Disable cache and MMU */
  559. dcache_disable(); /* TLBs are invalidated */
  560. invalidate_icache_all();
  561. /* point TTBR to the new table */
  562. set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
  563. MEMORY_ATTRIBUTES);
  564. set_sctlr(get_sctlr() | CR_M);
  565. }
  566. u64 get_page_table_size(void)
  567. {
  568. return 0x10000;
  569. }
  570. int arch_cpu_init(void)
  571. {
  572. /*
  573. * This function is called before U-Boot relocates itself to speed up
  574. * on system running. It is not necessary to run if performance is not
  575. * critical. Skip if MMU is already enabled by SPL or other means.
  576. */
  577. if (get_sctlr() & CR_M)
  578. return 0;
  579. icache_enable();
  580. __asm_invalidate_dcache_all();
  581. __asm_invalidate_tlb_all();
  582. early_mmu_setup();
  583. set_sctlr(get_sctlr() | CR_C);
  584. return 0;
  585. }
  586. void mmu_setup(void)
  587. {
  588. final_mmu_setup();
  589. }
  590. /*
  591. * This function is called from common/board_r.c.
  592. * It recreates MMU table in main memory.
  593. */
  594. void enable_caches(void)
  595. {
  596. mmu_setup();
  597. __asm_invalidate_tlb_all();
  598. icache_enable();
  599. dcache_enable();
  600. }
  601. #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  602. #ifdef CONFIG_TFABOOT
  603. enum boot_src __get_boot_src(u32 porsr1)
  604. {
  605. enum boot_src src = BOOT_SOURCE_RESERVED;
  606. u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
  607. #if !defined(CONFIG_NXP_LSCH3_2)
  608. u32 val;
  609. #endif
  610. debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
  611. #if defined(CONFIG_FSL_LSCH3)
  612. #if defined(CONFIG_NXP_LSCH3_2)
  613. switch (rcw_src) {
  614. case RCW_SRC_SDHC1_VAL:
  615. src = BOOT_SOURCE_SD_MMC;
  616. break;
  617. case RCW_SRC_SDHC2_VAL:
  618. src = BOOT_SOURCE_SD_MMC2;
  619. break;
  620. case RCW_SRC_I2C1_VAL:
  621. src = BOOT_SOURCE_I2C1_EXTENDED;
  622. break;
  623. case RCW_SRC_FLEXSPI_NAND2K_VAL:
  624. src = BOOT_SOURCE_XSPI_NAND;
  625. break;
  626. case RCW_SRC_FLEXSPI_NAND4K_VAL:
  627. src = BOOT_SOURCE_XSPI_NAND;
  628. break;
  629. case RCW_SRC_RESERVED_1_VAL:
  630. src = BOOT_SOURCE_RESERVED;
  631. break;
  632. case RCW_SRC_FLEXSPI_NOR_24B:
  633. src = BOOT_SOURCE_XSPI_NOR;
  634. break;
  635. default:
  636. src = BOOT_SOURCE_RESERVED;
  637. }
  638. #else
  639. val = rcw_src & RCW_SRC_TYPE_MASK;
  640. if (val == RCW_SRC_NOR_VAL) {
  641. val = rcw_src & NOR_TYPE_MASK;
  642. switch (val) {
  643. case NOR_16B_VAL:
  644. case NOR_32B_VAL:
  645. src = BOOT_SOURCE_IFC_NOR;
  646. break;
  647. default:
  648. src = BOOT_SOURCE_RESERVED;
  649. }
  650. } else {
  651. /* RCW SRC Serial Flash */
  652. val = rcw_src & RCW_SRC_SERIAL_MASK;
  653. switch (val) {
  654. case RCW_SRC_QSPI_VAL:
  655. /* RCW SRC Serial NOR (QSPI) */
  656. src = BOOT_SOURCE_QSPI_NOR;
  657. break;
  658. case RCW_SRC_SD_CARD_VAL:
  659. /* RCW SRC SD Card */
  660. src = BOOT_SOURCE_SD_MMC;
  661. break;
  662. case RCW_SRC_EMMC_VAL:
  663. /* RCW SRC EMMC */
  664. src = BOOT_SOURCE_SD_MMC;
  665. break;
  666. case RCW_SRC_I2C1_VAL:
  667. /* RCW SRC I2C1 Extended */
  668. src = BOOT_SOURCE_I2C1_EXTENDED;
  669. break;
  670. default:
  671. src = BOOT_SOURCE_RESERVED;
  672. }
  673. }
  674. #endif
  675. #elif defined(CONFIG_FSL_LSCH2)
  676. /* RCW SRC NAND */
  677. val = rcw_src & RCW_SRC_NAND_MASK;
  678. if (val == RCW_SRC_NAND_VAL) {
  679. val = rcw_src & NAND_RESERVED_MASK;
  680. if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
  681. src = BOOT_SOURCE_IFC_NAND;
  682. } else {
  683. /* RCW SRC NOR */
  684. val = rcw_src & RCW_SRC_NOR_MASK;
  685. if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
  686. src = BOOT_SOURCE_IFC_NOR;
  687. } else {
  688. switch (rcw_src) {
  689. case QSPI_VAL1:
  690. case QSPI_VAL2:
  691. src = BOOT_SOURCE_QSPI_NOR;
  692. break;
  693. case SD_VAL:
  694. src = BOOT_SOURCE_SD_MMC;
  695. break;
  696. default:
  697. src = BOOT_SOURCE_RESERVED;
  698. }
  699. }
  700. }
  701. #endif
  702. if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
  703. src = BOOT_SOURCE_QSPI_NOR;
  704. debug("%s: src 0x%x\n", __func__, src);
  705. return src;
  706. }
  707. enum boot_src get_boot_src(void)
  708. {
  709. struct pt_regs regs;
  710. u32 porsr1 = 0;
  711. #if defined(CONFIG_FSL_LSCH3)
  712. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  713. #elif defined(CONFIG_FSL_LSCH2)
  714. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  715. #endif
  716. if (current_el() == 2) {
  717. regs.regs[0] = SIP_SVC_RCW;
  718. smc_call(&regs);
  719. if (!regs.regs[0])
  720. porsr1 = regs.regs[1];
  721. }
  722. if (current_el() == 3 || !porsr1) {
  723. #ifdef CONFIG_FSL_LSCH3
  724. porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
  725. #elif defined(CONFIG_FSL_LSCH2)
  726. porsr1 = in_be32(&gur->porsr1);
  727. #endif
  728. }
  729. debug("%s: porsr1 0x%x\n", __func__, porsr1);
  730. return __get_boot_src(porsr1);
  731. }
  732. #ifdef CONFIG_ENV_IS_IN_MMC
  733. int mmc_get_env_dev(void)
  734. {
  735. enum boot_src src = get_boot_src();
  736. int dev = CONFIG_SYS_MMC_ENV_DEV;
  737. switch (src) {
  738. case BOOT_SOURCE_SD_MMC:
  739. dev = 0;
  740. break;
  741. case BOOT_SOURCE_SD_MMC2:
  742. dev = 1;
  743. break;
  744. default:
  745. break;
  746. }
  747. return dev;
  748. }
  749. #endif
  750. enum env_location env_get_location(enum env_operation op, int prio)
  751. {
  752. enum boot_src src = get_boot_src();
  753. enum env_location env_loc = ENVL_NOWHERE;
  754. if (prio)
  755. return ENVL_UNKNOWN;
  756. #ifdef CONFIG_ENV_IS_NOWHERE
  757. return env_loc;
  758. #endif
  759. switch (src) {
  760. case BOOT_SOURCE_IFC_NOR:
  761. env_loc = ENVL_FLASH;
  762. break;
  763. case BOOT_SOURCE_QSPI_NOR:
  764. /* FALLTHROUGH */
  765. case BOOT_SOURCE_XSPI_NOR:
  766. env_loc = ENVL_SPI_FLASH;
  767. break;
  768. case BOOT_SOURCE_IFC_NAND:
  769. /* FALLTHROUGH */
  770. case BOOT_SOURCE_QSPI_NAND:
  771. /* FALLTHROUGH */
  772. case BOOT_SOURCE_XSPI_NAND:
  773. env_loc = ENVL_NAND;
  774. break;
  775. case BOOT_SOURCE_SD_MMC:
  776. /* FALLTHROUGH */
  777. case BOOT_SOURCE_SD_MMC2:
  778. env_loc = ENVL_MMC;
  779. break;
  780. case BOOT_SOURCE_I2C1_EXTENDED:
  781. /* FALLTHROUGH */
  782. default:
  783. break;
  784. }
  785. return env_loc;
  786. }
  787. #endif /* CONFIG_TFABOOT */
  788. u32 initiator_type(u32 cluster, int init_id)
  789. {
  790. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  791. u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
  792. u32 type = 0;
  793. type = gur_in32(&gur->tp_ityp[idx]);
  794. if (type & TP_ITYP_AV)
  795. return type;
  796. return 0;
  797. }
  798. u32 cpu_pos_mask(void)
  799. {
  800. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  801. int i = 0;
  802. u32 cluster, type, mask = 0;
  803. do {
  804. int j;
  805. cluster = gur_in32(&gur->tp_cluster[i].lower);
  806. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  807. type = initiator_type(cluster, j);
  808. if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
  809. mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
  810. }
  811. i++;
  812. } while ((cluster & TP_CLUSTER_EOC) == 0x0);
  813. return mask;
  814. }
  815. u32 cpu_mask(void)
  816. {
  817. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  818. int i = 0, count = 0;
  819. u32 cluster, type, mask = 0;
  820. do {
  821. int j;
  822. cluster = gur_in32(&gur->tp_cluster[i].lower);
  823. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  824. type = initiator_type(cluster, j);
  825. if (type) {
  826. if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  827. mask |= 1 << count;
  828. count++;
  829. }
  830. }
  831. i++;
  832. } while ((cluster & TP_CLUSTER_EOC) == 0x0);
  833. return mask;
  834. }
  835. /*
  836. * Return the number of cores on this SOC.
  837. */
  838. int cpu_numcores(void)
  839. {
  840. return hweight32(cpu_mask());
  841. }
  842. int fsl_qoriq_core_to_cluster(unsigned int core)
  843. {
  844. struct ccsr_gur __iomem *gur =
  845. (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
  846. int i = 0, count = 0;
  847. u32 cluster;
  848. do {
  849. int j;
  850. cluster = gur_in32(&gur->tp_cluster[i].lower);
  851. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  852. if (initiator_type(cluster, j)) {
  853. if (count == core)
  854. return i;
  855. count++;
  856. }
  857. }
  858. i++;
  859. } while ((cluster & TP_CLUSTER_EOC) == 0x0);
  860. return -1; /* cannot identify the cluster */
  861. }
  862. u32 fsl_qoriq_core_to_type(unsigned int core)
  863. {
  864. struct ccsr_gur __iomem *gur =
  865. (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
  866. int i = 0, count = 0;
  867. u32 cluster, type;
  868. do {
  869. int j;
  870. cluster = gur_in32(&gur->tp_cluster[i].lower);
  871. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  872. type = initiator_type(cluster, j);
  873. if (type) {
  874. if (count == core)
  875. return type;
  876. count++;
  877. }
  878. }
  879. i++;
  880. } while ((cluster & TP_CLUSTER_EOC) == 0x0);
  881. return -1; /* cannot identify the cluster */
  882. }
  883. #ifndef CONFIG_FSL_LSCH3
  884. uint get_svr(void)
  885. {
  886. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  887. return gur_in32(&gur->svr);
  888. }
  889. #endif
  890. #ifdef CONFIG_DISPLAY_CPUINFO
  891. int print_cpuinfo(void)
  892. {
  893. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  894. struct sys_info sysinfo;
  895. char buf[32];
  896. unsigned int i, core;
  897. u32 type, rcw, svr = gur_in32(&gur->svr);
  898. puts("SoC: ");
  899. cpu_name(buf);
  900. printf(" %s (0x%x)\n", buf, svr);
  901. memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  902. get_sys_info(&sysinfo);
  903. puts("Clock Configuration:");
  904. for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
  905. if (!(i % 3))
  906. puts("\n ");
  907. type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
  908. printf("CPU%d(%s):%-4s MHz ", core,
  909. type == TY_ITYP_VER_A7 ? "A7 " :
  910. (type == TY_ITYP_VER_A53 ? "A53" :
  911. (type == TY_ITYP_VER_A57 ? "A57" :
  912. (type == TY_ITYP_VER_A72 ? "A72" : " "))),
  913. strmhz(buf, sysinfo.freq_processor[core]));
  914. }
  915. /* Display platform clock as Bus frequency. */
  916. printf("\n Bus: %-4s MHz ",
  917. strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
  918. printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
  919. #ifdef CONFIG_SYS_DPAA_FMAN
  920. printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
  921. #endif
  922. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  923. if (soc_has_dp_ddr()) {
  924. printf(" DP-DDR: %-4s MT/s",
  925. strmhz(buf, sysinfo.freq_ddrbus2));
  926. }
  927. #endif
  928. puts("\n");
  929. /*
  930. * Display the RCW, so that no one gets confused as to what RCW
  931. * we're actually using for this boot.
  932. */
  933. puts("Reset Configuration Word (RCW):");
  934. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  935. rcw = gur_in32(&gur->rcwsr[i]);
  936. if ((i % 4) == 0)
  937. printf("\n %08x:", i * 4);
  938. printf(" %08x", rcw);
  939. }
  940. puts("\n");
  941. return 0;
  942. }
  943. #endif
  944. #ifdef CONFIG_FSL_ESDHC
  945. int cpu_mmc_init(bd_t *bis)
  946. {
  947. return fsl_esdhc_mmc_init(bis);
  948. }
  949. #endif
  950. int cpu_eth_init(bd_t *bis)
  951. {
  952. int error = 0;
  953. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  954. error = fsl_mc_ldpaa_init(bis);
  955. #endif
  956. #ifdef CONFIG_FMAN_ENET
  957. fm_standard_init(bis);
  958. #endif
  959. return error;
  960. }
  961. static inline int check_psci(void)
  962. {
  963. unsigned int psci_ver;
  964. psci_ver = sec_firmware_support_psci_version();
  965. if (psci_ver == PSCI_INVALID_VER)
  966. return 1;
  967. return 0;
  968. }
  969. static void config_core_prefetch(void)
  970. {
  971. char *buf = NULL;
  972. char buffer[HWCONFIG_BUFFER_SIZE];
  973. const char *prefetch_arg = NULL;
  974. size_t arglen;
  975. unsigned int mask;
  976. struct pt_regs regs;
  977. if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
  978. buf = buffer;
  979. prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
  980. &arglen, buf);
  981. if (prefetch_arg) {
  982. mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
  983. if (mask & 0x1) {
  984. printf("Core0 prefetch can't be disabled\n");
  985. return;
  986. }
  987. #define SIP_PREFETCH_DISABLE_64 0xC200FF13
  988. regs.regs[0] = SIP_PREFETCH_DISABLE_64;
  989. regs.regs[1] = mask;
  990. smc_call(&regs);
  991. if (regs.regs[0])
  992. printf("Prefetch disable config failed for mask ");
  993. else
  994. printf("Prefetch disable config passed for mask ");
  995. printf("0x%x\n", mask);
  996. }
  997. }
  998. int arch_early_init_r(void)
  999. {
  1000. #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  1001. u32 svr_dev_id;
  1002. /*
  1003. * erratum A009635 is valid only for LS2080A SoC and
  1004. * its personalitiesi
  1005. */
  1006. svr_dev_id = get_svr();
  1007. if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
  1008. erratum_a009635();
  1009. #endif
  1010. #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
  1011. erratum_a009942_check_cpo();
  1012. #endif
  1013. if (check_psci()) {
  1014. debug("PSCI: PSCI does not exist.\n");
  1015. /* if PSCI does not exist, boot secondary cores here */
  1016. if (fsl_layerscape_wake_seconday_cores())
  1017. printf("Did not wake secondary cores\n");
  1018. }
  1019. config_core_prefetch();
  1020. #ifdef CONFIG_SYS_HAS_SERDES
  1021. fsl_serdes_init();
  1022. #endif
  1023. #ifdef CONFIG_SYS_FSL_HAS_RGMII
  1024. /* some dpmacs in armv8a based freescale layerscape SOCs can be
  1025. * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
  1026. * EC*_PMUX(rgmii) bits in RCW.
  1027. * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
  1028. * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
  1029. * Now if a dpmac is enabled by serdes bits then it takes precedence
  1030. * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
  1031. * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
  1032. * then the dpmac is SGMII and not RGMII.
  1033. *
  1034. * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
  1035. * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
  1036. * or not? if it is (fsl_serdes_init has already enabled the dpmac),
  1037. * then don't enable it.
  1038. */
  1039. fsl_rgmii_init();
  1040. #endif
  1041. #ifdef CONFIG_FMAN_ENET
  1042. fman_enet_init();
  1043. #endif
  1044. #ifdef CONFIG_SYS_DPAA_QBMAN
  1045. setup_qbman_portals();
  1046. #endif
  1047. return 0;
  1048. }
  1049. int timer_init(void)
  1050. {
  1051. u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
  1052. #ifdef CONFIG_FSL_LSCH3
  1053. u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
  1054. #endif
  1055. #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
  1056. u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
  1057. u32 svr_dev_id;
  1058. #endif
  1059. #ifdef COUNTER_FREQUENCY_REAL
  1060. unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
  1061. /* Update with accurate clock frequency */
  1062. if (current_el() == 3)
  1063. asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
  1064. #endif
  1065. #ifdef CONFIG_FSL_LSCH3
  1066. /* Enable timebase for all clusters.
  1067. * It is safe to do so even some clusters are not enabled.
  1068. */
  1069. out_le32(cltbenr, 0xf);
  1070. #endif
  1071. #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
  1072. /*
  1073. * In certain Layerscape SoCs, the clock for each core's
  1074. * has an enable bit in the PMU Physical Core Time Base Enable
  1075. * Register (PCTBENR), which allows the watchdog to operate.
  1076. */
  1077. setbits_le32(pctbenr, 0xff);
  1078. /*
  1079. * For LS2080A SoC and its personalities, timer controller
  1080. * offset is different
  1081. */
  1082. svr_dev_id = get_svr();
  1083. if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
  1084. cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
  1085. #endif
  1086. /* Enable clock for timer
  1087. * This is a global setting.
  1088. */
  1089. out_le32(cntcr, 0x1);
  1090. return 0;
  1091. }
  1092. __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
  1093. void __efi_runtime reset_cpu(ulong addr)
  1094. {
  1095. u32 val;
  1096. #ifdef CONFIG_ARCH_LX2160A
  1097. val = in_le32(rstcr);
  1098. val |= 0x01;
  1099. out_le32(rstcr, val);
  1100. #else
  1101. /* Raise RESET_REQ_B */
  1102. val = scfg_in32(rstcr);
  1103. val |= 0x02;
  1104. scfg_out32(rstcr, val);
  1105. #endif
  1106. }
  1107. #ifdef CONFIG_EFI_LOADER
  1108. void __efi_runtime EFIAPI efi_reset_system(
  1109. enum efi_reset_type reset_type,
  1110. efi_status_t reset_status,
  1111. unsigned long data_size, void *reset_data)
  1112. {
  1113. switch (reset_type) {
  1114. case EFI_RESET_COLD:
  1115. case EFI_RESET_WARM:
  1116. case EFI_RESET_PLATFORM_SPECIFIC:
  1117. reset_cpu(0);
  1118. break;
  1119. case EFI_RESET_SHUTDOWN:
  1120. /* Nothing we can do */
  1121. break;
  1122. }
  1123. while (1) { }
  1124. }
  1125. efi_status_t efi_reset_system_init(void)
  1126. {
  1127. return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
  1128. }
  1129. #endif
  1130. /*
  1131. * Calculate reserved memory with given memory bank
  1132. * Return aligned memory size on success
  1133. * Return (ram_size + needed size) for failure
  1134. */
  1135. phys_size_t board_reserve_ram_top(phys_size_t ram_size)
  1136. {
  1137. phys_size_t ram_top = ram_size;
  1138. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  1139. ram_top = mc_get_dram_block_size();
  1140. if (ram_top > ram_size)
  1141. return ram_size + ram_top;
  1142. ram_top = ram_size - ram_top;
  1143. /* The start address of MC reserved memory needs to be aligned. */
  1144. ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
  1145. #endif
  1146. return ram_size - ram_top;
  1147. }
  1148. phys_size_t get_effective_memsize(void)
  1149. {
  1150. phys_size_t ea_size, rem = 0;
  1151. /*
  1152. * For ARMv8 SoCs, DDR memory is split into two or three regions. The
  1153. * first region is 2GB space at 0x8000_0000. Secure memory needs to
  1154. * allocated from first region. If the memory extends to the second
  1155. * region (or the third region if applicable), Management Complex (MC)
  1156. * memory should be put into the highest region, i.e. the end of DDR
  1157. * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
  1158. * U-Boot doesn't relocate itself into higher address. Should DDR be
  1159. * configured to skip the first region, this function needs to be
  1160. * adjusted.
  1161. */
  1162. if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
  1163. ea_size = CONFIG_MAX_MEM_MAPPED;
  1164. rem = gd->ram_size - ea_size;
  1165. } else {
  1166. ea_size = gd->ram_size;
  1167. }
  1168. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  1169. /* Check if we have enough space for secure memory */
  1170. if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
  1171. ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
  1172. else
  1173. printf("Error: No enough space for secure memory.\n");
  1174. #endif
  1175. /* Check if we have enough memory for MC */
  1176. if (rem < board_reserve_ram_top(rem)) {
  1177. /* Not enough memory in high region to reserve */
  1178. if (ea_size > board_reserve_ram_top(ea_size))
  1179. ea_size -= board_reserve_ram_top(ea_size);
  1180. else
  1181. printf("Error: No enough space for reserved memory.\n");
  1182. }
  1183. return ea_size;
  1184. }
  1185. #ifdef CONFIG_TFABOOT
  1186. phys_size_t tfa_get_dram_size(void)
  1187. {
  1188. struct pt_regs regs;
  1189. phys_size_t dram_size = 0;
  1190. regs.regs[0] = SMC_DRAM_BANK_INFO;
  1191. regs.regs[1] = -1;
  1192. smc_call(&regs);
  1193. if (regs.regs[0])
  1194. return 0;
  1195. dram_size = regs.regs[1];
  1196. return dram_size;
  1197. }
  1198. static int tfa_dram_init_banksize(void)
  1199. {
  1200. int i = 0, ret = 0;
  1201. struct pt_regs regs;
  1202. phys_size_t dram_size = tfa_get_dram_size();
  1203. debug("dram_size %llx\n", dram_size);
  1204. if (!dram_size)
  1205. return -EINVAL;
  1206. do {
  1207. regs.regs[0] = SMC_DRAM_BANK_INFO;
  1208. regs.regs[1] = i;
  1209. smc_call(&regs);
  1210. if (regs.regs[0]) {
  1211. ret = -EINVAL;
  1212. break;
  1213. }
  1214. debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
  1215. regs.regs[2]);
  1216. gd->bd->bi_dram[i].start = regs.regs[1];
  1217. gd->bd->bi_dram[i].size = regs.regs[2];
  1218. dram_size -= gd->bd->bi_dram[i].size;
  1219. i++;
  1220. } while (dram_size);
  1221. if (i > 0)
  1222. ret = 0;
  1223. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  1224. /* Assign memory for MC */
  1225. #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  1226. if (gd->bd->bi_dram[2].size >=
  1227. board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
  1228. gd->arch.resv_ram = gd->bd->bi_dram[2].start +
  1229. gd->bd->bi_dram[2].size -
  1230. board_reserve_ram_top(gd->bd->bi_dram[2].size);
  1231. } else
  1232. #endif
  1233. {
  1234. if (gd->bd->bi_dram[1].size >=
  1235. board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
  1236. gd->arch.resv_ram = gd->bd->bi_dram[1].start +
  1237. gd->bd->bi_dram[1].size -
  1238. board_reserve_ram_top(gd->bd->bi_dram[1].size);
  1239. } else if (gd->bd->bi_dram[0].size >
  1240. board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
  1241. gd->arch.resv_ram = gd->bd->bi_dram[0].start +
  1242. gd->bd->bi_dram[0].size -
  1243. board_reserve_ram_top(gd->bd->bi_dram[0].size);
  1244. }
  1245. }
  1246. #endif /* CONFIG_FSL_MC_ENET */
  1247. return ret;
  1248. }
  1249. #endif
  1250. int dram_init_banksize(void)
  1251. {
  1252. #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  1253. phys_size_t dp_ddr_size;
  1254. #endif
  1255. #ifdef CONFIG_TFABOOT
  1256. if (!tfa_dram_init_banksize())
  1257. return 0;
  1258. #endif
  1259. /*
  1260. * gd->ram_size has the total size of DDR memory, less reserved secure
  1261. * memory. The DDR extends from low region to high region(s) presuming
  1262. * no hole is created with DDR configuration. gd->arch.secure_ram tracks
  1263. * the location of secure memory. gd->arch.resv_ram tracks the location
  1264. * of reserved memory for Management Complex (MC). Because gd->ram_size
  1265. * is reduced by this function if secure memory is reserved, checking
  1266. * gd->arch.secure_ram should be done to avoid running it repeatedly.
  1267. */
  1268. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  1269. if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
  1270. debug("No need to run again, skip %s\n", __func__);
  1271. return 0;
  1272. }
  1273. #endif
  1274. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  1275. if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
  1276. gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
  1277. gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
  1278. gd->bd->bi_dram[1].size = gd->ram_size -
  1279. CONFIG_SYS_DDR_BLOCK1_SIZE;
  1280. #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  1281. if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
  1282. gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
  1283. gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
  1284. CONFIG_SYS_DDR_BLOCK2_SIZE;
  1285. gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
  1286. }
  1287. #endif
  1288. } else {
  1289. gd->bd->bi_dram[0].size = gd->ram_size;
  1290. }
  1291. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  1292. if (gd->bd->bi_dram[0].size >
  1293. CONFIG_SYS_MEM_RESERVE_SECURE) {
  1294. gd->bd->bi_dram[0].size -=
  1295. CONFIG_SYS_MEM_RESERVE_SECURE;
  1296. gd->arch.secure_ram = gd->bd->bi_dram[0].start +
  1297. gd->bd->bi_dram[0].size;
  1298. gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
  1299. gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
  1300. }
  1301. #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
  1302. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  1303. /* Assign memory for MC */
  1304. #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  1305. if (gd->bd->bi_dram[2].size >=
  1306. board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
  1307. gd->arch.resv_ram = gd->bd->bi_dram[2].start +
  1308. gd->bd->bi_dram[2].size -
  1309. board_reserve_ram_top(gd->bd->bi_dram[2].size);
  1310. } else
  1311. #endif
  1312. {
  1313. if (gd->bd->bi_dram[1].size >=
  1314. board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
  1315. gd->arch.resv_ram = gd->bd->bi_dram[1].start +
  1316. gd->bd->bi_dram[1].size -
  1317. board_reserve_ram_top(gd->bd->bi_dram[1].size);
  1318. } else if (gd->bd->bi_dram[0].size >
  1319. board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
  1320. gd->arch.resv_ram = gd->bd->bi_dram[0].start +
  1321. gd->bd->bi_dram[0].size -
  1322. board_reserve_ram_top(gd->bd->bi_dram[0].size);
  1323. }
  1324. }
  1325. #endif /* CONFIG_FSL_MC_ENET */
  1326. #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  1327. #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  1328. #error "This SoC shouldn't have DP DDR"
  1329. #endif
  1330. if (soc_has_dp_ddr()) {
  1331. /* initialize DP-DDR here */
  1332. puts("DP-DDR: ");
  1333. /*
  1334. * DDR controller use 0 as the base address for binding.
  1335. * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  1336. */
  1337. dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
  1338. CONFIG_DP_DDR_CTRL,
  1339. CONFIG_DP_DDR_NUM_CTRLS,
  1340. CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
  1341. NULL, NULL, NULL);
  1342. if (dp_ddr_size) {
  1343. gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
  1344. gd->bd->bi_dram[2].size = dp_ddr_size;
  1345. } else {
  1346. puts("Not detected");
  1347. }
  1348. }
  1349. #endif
  1350. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  1351. debug("%s is called. gd->ram_size is reduced to %lu\n",
  1352. __func__, (ulong)gd->ram_size);
  1353. #endif
  1354. return 0;
  1355. }
  1356. #if CONFIG_IS_ENABLED(EFI_LOADER)
  1357. void efi_add_known_memory(void)
  1358. {
  1359. int i;
  1360. phys_addr_t ram_start, start;
  1361. phys_size_t ram_size;
  1362. u64 pages;
  1363. /* Add RAM */
  1364. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  1365. #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  1366. #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  1367. #error "This SoC shouldn't have DP DDR"
  1368. #endif
  1369. if (i == 2)
  1370. continue; /* skip DP-DDR */
  1371. #endif
  1372. ram_start = gd->bd->bi_dram[i].start;
  1373. ram_size = gd->bd->bi_dram[i].size;
  1374. #ifdef CONFIG_RESV_RAM
  1375. if (gd->arch.resv_ram >= ram_start &&
  1376. gd->arch.resv_ram < ram_start + ram_size)
  1377. ram_size = gd->arch.resv_ram - ram_start;
  1378. #endif
  1379. start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
  1380. pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
  1381. efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
  1382. false);
  1383. }
  1384. }
  1385. #endif
  1386. /*
  1387. * Before DDR size is known, early MMU table have DDR mapped as device memory
  1388. * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
  1389. * needs to be set for these mappings.
  1390. * If a special case configures DDR with holes in the mapping, the holes need
  1391. * to be marked as invalid. This is not implemented in this function.
  1392. */
  1393. void update_early_mmu_table(void)
  1394. {
  1395. if (!gd->arch.tlb_addr)
  1396. return;
  1397. if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
  1398. mmu_change_region_attr(
  1399. CONFIG_SYS_SDRAM_BASE,
  1400. gd->ram_size,
  1401. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  1402. PTE_BLOCK_OUTER_SHARE |
  1403. PTE_BLOCK_NS |
  1404. PTE_TYPE_VALID);
  1405. } else {
  1406. mmu_change_region_attr(
  1407. CONFIG_SYS_SDRAM_BASE,
  1408. CONFIG_SYS_DDR_BLOCK1_SIZE,
  1409. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  1410. PTE_BLOCK_OUTER_SHARE |
  1411. PTE_BLOCK_NS |
  1412. PTE_TYPE_VALID);
  1413. #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
  1414. #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
  1415. #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
  1416. #endif
  1417. if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
  1418. CONFIG_SYS_DDR_BLOCK2_SIZE) {
  1419. mmu_change_region_attr(
  1420. CONFIG_SYS_DDR_BLOCK2_BASE,
  1421. CONFIG_SYS_DDR_BLOCK2_SIZE,
  1422. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  1423. PTE_BLOCK_OUTER_SHARE |
  1424. PTE_BLOCK_NS |
  1425. PTE_TYPE_VALID);
  1426. mmu_change_region_attr(
  1427. CONFIG_SYS_DDR_BLOCK3_BASE,
  1428. gd->ram_size -
  1429. CONFIG_SYS_DDR_BLOCK1_SIZE -
  1430. CONFIG_SYS_DDR_BLOCK2_SIZE,
  1431. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  1432. PTE_BLOCK_OUTER_SHARE |
  1433. PTE_BLOCK_NS |
  1434. PTE_TYPE_VALID);
  1435. } else
  1436. #endif
  1437. {
  1438. mmu_change_region_attr(
  1439. CONFIG_SYS_DDR_BLOCK2_BASE,
  1440. gd->ram_size -
  1441. CONFIG_SYS_DDR_BLOCK1_SIZE,
  1442. PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  1443. PTE_BLOCK_OUTER_SHARE |
  1444. PTE_BLOCK_NS |
  1445. PTE_TYPE_VALID);
  1446. }
  1447. }
  1448. }
  1449. __weak int dram_init(void)
  1450. {
  1451. fsl_initdram();
  1452. #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
  1453. defined(CONFIG_SPL_BUILD)
  1454. /* This will break-before-make MMU for DDR */
  1455. update_early_mmu_table();
  1456. #endif
  1457. return 0;
  1458. }