board.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM335X based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <net.h>
  14. #include <serial.h>
  15. #include <asm/global_data.h>
  16. #include <linux/libfdt.h>
  17. #include <spl.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/hardware.h>
  20. #include <asm/arch/omap.h>
  21. #include <asm/arch/ddr_defs.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/gpio.h>
  24. #include <asm/arch/mmc_host_def.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <asm/arch/mem.h>
  27. #include <asm/arch/mux.h>
  28. #include <asm/io.h>
  29. #include <asm/emif.h>
  30. #include <asm/gpio.h>
  31. #include <i2c.h>
  32. #include <miiphy.h>
  33. #include <cpsw.h>
  34. #include <power/tps65910.h>
  35. #include <watchdog.h>
  36. #include "board.h"
  37. DECLARE_GLOBAL_DATA_PTR;
  38. /* GPIO that controls DIP switch and mPCIe slot */
  39. #define DIP_S1 44
  40. #define MPCIE_SW 100
  41. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  42. static int baltos_set_console(void)
  43. {
  44. int val, i, dips = 0;
  45. char buf[7];
  46. for (i = 0; i < 4; i++) {
  47. sprintf(buf, "dip_s%d", i + 1);
  48. if (gpio_request(DIP_S1 + i, buf)) {
  49. printf("failed to export GPIO %d\n", DIP_S1 + i);
  50. return 0;
  51. }
  52. if (gpio_direction_input(DIP_S1 + i)) {
  53. printf("failed to set GPIO %d direction\n", DIP_S1 + i);
  54. return 0;
  55. }
  56. val = gpio_get_value(DIP_S1 + i);
  57. dips |= val << i;
  58. }
  59. printf("DIPs: 0x%1x\n", (~dips) & 0xf);
  60. if ((dips & 0xf) == 0xe)
  61. env_set("console", "ttyUSB0,115200n8");
  62. return 0;
  63. }
  64. static int read_eeprom(BSP_VS_HWPARAM *header)
  65. {
  66. i2c_set_bus_num(1);
  67. /* Check if baseboard eeprom is available */
  68. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  69. puts("Could not probe the EEPROM; something fundamentally "
  70. "wrong on the I2C bus.\n");
  71. return -ENODEV;
  72. }
  73. /* read the eeprom using i2c */
  74. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  75. sizeof(BSP_VS_HWPARAM))) {
  76. puts("Could not read the EEPROM; something fundamentally"
  77. " wrong on the I2C bus.\n");
  78. return -EIO;
  79. }
  80. if (header->Magic != 0xDEADBEEF) {
  81. printf("Incorrect magic number (0x%x) in EEPROM\n",
  82. header->Magic);
  83. /* fill default values */
  84. header->SystemId = 211;
  85. header->MAC1[0] = 0x00;
  86. header->MAC1[1] = 0x00;
  87. header->MAC1[2] = 0x00;
  88. header->MAC1[3] = 0x00;
  89. header->MAC1[4] = 0x00;
  90. header->MAC1[5] = 0x01;
  91. header->MAC2[0] = 0x00;
  92. header->MAC2[1] = 0x00;
  93. header->MAC2[2] = 0x00;
  94. header->MAC2[3] = 0x00;
  95. header->MAC2[4] = 0x00;
  96. header->MAC2[5] = 0x02;
  97. header->MAC3[0] = 0x00;
  98. header->MAC3[1] = 0x00;
  99. header->MAC3[2] = 0x00;
  100. header->MAC3[3] = 0x00;
  101. header->MAC3[4] = 0x00;
  102. header->MAC3[5] = 0x03;
  103. }
  104. return 0;
  105. }
  106. #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
  107. static const struct ddr_data ddr3_baltos_data = {
  108. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  109. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  110. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  111. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  112. };
  113. static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
  114. .cmd0csratio = MT41K256M16HA125E_RATIO,
  115. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  116. .cmd1csratio = MT41K256M16HA125E_RATIO,
  117. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  118. .cmd2csratio = MT41K256M16HA125E_RATIO,
  119. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  120. };
  121. static struct emif_regs ddr3_baltos_emif_reg_data = {
  122. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  123. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  124. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  125. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  126. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  127. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  128. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  129. };
  130. #ifdef CONFIG_SPL_OS_BOOT
  131. int spl_start_uboot(void)
  132. {
  133. /* break into full u-boot on 'c' */
  134. return (serial_tstc() && serial_getc() == 'c');
  135. }
  136. #endif
  137. #define OSC (V_OSCK/1000000)
  138. const struct dpll_params dpll_ddr = {
  139. 266, OSC-1, 1, -1, -1, -1, -1};
  140. const struct dpll_params dpll_ddr_evm_sk = {
  141. 303, OSC-1, 1, -1, -1, -1, -1};
  142. const struct dpll_params dpll_ddr_baltos = {
  143. 400, OSC-1, 1, -1, -1, -1, -1};
  144. void am33xx_spl_board_init(void)
  145. {
  146. int mpu_vdd;
  147. int sil_rev;
  148. /* Get the frequency */
  149. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  150. /*
  151. * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
  152. * MPU frequencies we support we use a CORE voltage of
  153. * 1.1375V. For MPU voltage we need to switch based on
  154. * the frequency we are running at.
  155. */
  156. i2c_set_bus_num(1);
  157. printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
  158. if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
  159. puts("i2c: cannot access TPS65910\n");
  160. return;
  161. }
  162. /*
  163. * Depending on MPU clock and PG we will need a different
  164. * VDD to drive at that speed.
  165. */
  166. sil_rev = readl(&cdev->deviceid) >> 28;
  167. mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
  168. dpll_mpu_opp100.m);
  169. /* Tell the TPS65910 to use i2c */
  170. tps65910_set_i2c_control();
  171. /* First update MPU voltage. */
  172. if (tps65910_voltage_update(MPU, mpu_vdd))
  173. return;
  174. /* Second, update the CORE voltage. */
  175. if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
  176. return;
  177. /* Set CORE Frequencies to OPP100 */
  178. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  179. /* Set MPU Frequency to what we detected now that voltages are set */
  180. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  181. writel(0x000010ff, PRM_DEVICE_INST + 4);
  182. }
  183. const struct dpll_params *get_dpll_ddr_params(void)
  184. {
  185. enable_i2c1_pin_mux();
  186. i2c_set_bus_num(1);
  187. return &dpll_ddr_baltos;
  188. }
  189. void set_uart_mux_conf(void)
  190. {
  191. enable_uart0_pin_mux();
  192. }
  193. void set_mux_conf_regs(void)
  194. {
  195. enable_board_pin_mux();
  196. }
  197. const struct ctrl_ioregs ioregs_baltos = {
  198. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  199. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  200. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  201. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  202. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  203. };
  204. void sdram_init(void)
  205. {
  206. config_ddr(400, &ioregs_baltos,
  207. &ddr3_baltos_data,
  208. &ddr3_baltos_cmd_ctrl_data,
  209. &ddr3_baltos_emif_reg_data, 0);
  210. }
  211. #endif
  212. /*
  213. * Basic board specific setup. Pinmux has been handled already.
  214. */
  215. int board_init(void)
  216. {
  217. #if defined(CONFIG_HW_WATCHDOG)
  218. hw_watchdog_init();
  219. #endif
  220. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  221. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  222. gpmc_init();
  223. #endif
  224. return 0;
  225. }
  226. int ft_board_setup(void *blob, struct bd_info *bd)
  227. {
  228. int node, ret;
  229. unsigned char mac_addr[6];
  230. BSP_VS_HWPARAM header;
  231. /* get production data */
  232. if (read_eeprom(&header))
  233. return 0;
  234. /* setup MAC1 */
  235. mac_addr[0] = header.MAC1[0];
  236. mac_addr[1] = header.MAC1[1];
  237. mac_addr[2] = header.MAC1[2];
  238. mac_addr[3] = header.MAC1[3];
  239. mac_addr[4] = header.MAC1[4];
  240. mac_addr[5] = header.MAC1[5];
  241. node = fdt_path_offset(blob, "ethernet0");
  242. if (node < 0) {
  243. printf("no ethernet0 path offset\n");
  244. return -ENODEV;
  245. }
  246. ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
  247. if (ret) {
  248. printf("error setting mac-address property\n");
  249. return -ENODEV;
  250. }
  251. /* setup MAC2 */
  252. mac_addr[0] = header.MAC2[0];
  253. mac_addr[1] = header.MAC2[1];
  254. mac_addr[2] = header.MAC2[2];
  255. mac_addr[3] = header.MAC2[3];
  256. mac_addr[4] = header.MAC2[4];
  257. mac_addr[5] = header.MAC2[5];
  258. node = fdt_path_offset(blob, "ethernet1");
  259. if (node < 0) {
  260. printf("no ethernet1 path offset\n");
  261. return -ENODEV;
  262. }
  263. ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
  264. if (ret) {
  265. printf("error setting mac-address property\n");
  266. return -ENODEV;
  267. }
  268. printf("\nFDT was successfully setup\n");
  269. return 0;
  270. }
  271. static struct module_pin_mux pcie_sw_pin_mux[] = {
  272. {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
  273. {-1},
  274. };
  275. static struct module_pin_mux dip_pin_mux[] = {
  276. {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
  277. {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
  278. {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
  279. {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
  280. {-1},
  281. };
  282. #ifdef CONFIG_BOARD_LATE_INIT
  283. int board_late_init(void)
  284. {
  285. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  286. BSP_VS_HWPARAM header;
  287. char model[4];
  288. /* get production data */
  289. if (read_eeprom(&header)) {
  290. strcpy(model, "211");
  291. } else {
  292. sprintf(model, "%d", header.SystemId);
  293. if (header.SystemId == 215) {
  294. configure_module_pin_mux(dip_pin_mux);
  295. baltos_set_console();
  296. }
  297. }
  298. /* turn power for the mPCIe slot */
  299. configure_module_pin_mux(pcie_sw_pin_mux);
  300. if (gpio_request(MPCIE_SW, "mpcie_sw")) {
  301. printf("failed to export GPIO %d\n", MPCIE_SW);
  302. return -ENODEV;
  303. }
  304. if (gpio_direction_output(MPCIE_SW, 1)) {
  305. printf("failed to set GPIO %d direction\n", MPCIE_SW);
  306. return -ENODEV;
  307. }
  308. env_set("board_name", model);
  309. #endif
  310. return 0;
  311. }
  312. #endif
  313. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  314. (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
  315. static void cpsw_control(int enabled)
  316. {
  317. /* VTP can be added here */
  318. return;
  319. }
  320. static struct cpsw_slave_data cpsw_slaves[] = {
  321. {
  322. .slave_reg_ofs = 0x208,
  323. .sliver_reg_ofs = 0xd80,
  324. .phy_addr = 0,
  325. },
  326. {
  327. .slave_reg_ofs = 0x308,
  328. .sliver_reg_ofs = 0xdc0,
  329. .phy_addr = 7,
  330. },
  331. };
  332. static struct cpsw_platform_data cpsw_data = {
  333. .mdio_base = CPSW_MDIO_BASE,
  334. .cpsw_base = CPSW_BASE,
  335. .mdio_div = 0xff,
  336. .channels = 8,
  337. .cpdma_reg_ofs = 0x800,
  338. .slaves = 2,
  339. .slave_data = cpsw_slaves,
  340. .active_slave = 1,
  341. .ale_reg_ofs = 0xd00,
  342. .ale_entries = 1024,
  343. .host_port_reg_ofs = 0x108,
  344. .hw_stats_reg_ofs = 0x900,
  345. .bd_ram_ofs = 0x2000,
  346. .mac_control = (1 << 5),
  347. .control = cpsw_control,
  348. .host_port_num = 0,
  349. .version = CPSW_CTRL_VERSION_2,
  350. };
  351. #endif
  352. #if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \
  353. && defined(CONFIG_SPL_BUILD)) || \
  354. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  355. defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
  356. !defined(CONFIG_SPL_BUILD))
  357. int board_eth_init(struct bd_info *bis)
  358. {
  359. int rv, n = 0;
  360. uint8_t mac_addr[6];
  361. uint32_t mac_hi, mac_lo;
  362. /*
  363. * Note here that we're using CPSW1 since that has a 1Gbit PHY while
  364. * CSPW0 has a 100Mbit PHY.
  365. *
  366. * On product, CPSW1 maps to port labeled WAN.
  367. */
  368. /* try reading mac address from efuse */
  369. mac_lo = readl(&cdev->macid1l);
  370. mac_hi = readl(&cdev->macid1h);
  371. mac_addr[0] = mac_hi & 0xFF;
  372. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  373. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  374. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  375. mac_addr[4] = mac_lo & 0xFF;
  376. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  377. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  378. (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
  379. if (!env_get("ethaddr")) {
  380. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  381. if (is_valid_ethaddr(mac_addr))
  382. eth_env_set_enetaddr("ethaddr", mac_addr);
  383. }
  384. #ifdef CONFIG_DRIVER_TI_CPSW
  385. writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
  386. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
  387. rv = cpsw_register(&cpsw_data);
  388. if (rv < 0)
  389. printf("Error %d registering CPSW switch\n", rv);
  390. else
  391. n += rv;
  392. #endif
  393. /*
  394. *
  395. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  396. * operating points. So we must set the TX clock delay feature
  397. * in the AR8051 PHY. Since we only support a single ethernet
  398. * device in U-Boot, we only do this for the first instance.
  399. */
  400. #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
  401. #define AR8051_PHY_DEBUG_DATA_REG 0x1e
  402. #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
  403. #define AR8051_RGMII_TX_CLK_DLY 0x100
  404. const char *devname;
  405. devname = miiphy_get_current_dev();
  406. miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
  407. AR8051_DEBUG_RGMII_CLK_DLY_REG);
  408. miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
  409. AR8051_RGMII_TX_CLK_DLY);
  410. #endif
  411. return n;
  412. }
  413. #endif