board.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TCL SL50 board
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <net.h>
  14. #include <serial.h>
  15. #include <spl.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/omap.h>
  19. #include <asm/arch/ddr_defs.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/arch/mmc_host_def.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/arch/mem.h>
  25. #include <asm/global_data.h>
  26. #include <asm/io.h>
  27. #include <asm/emif.h>
  28. #include <asm/gpio.h>
  29. #include <i2c.h>
  30. #include <miiphy.h>
  31. #include <cpsw.h>
  32. #include <power/tps65217.h>
  33. #include <power/tps65910.h>
  34. #include <env_internal.h>
  35. #include <watchdog.h>
  36. #include "board.h"
  37. DECLARE_GLOBAL_DATA_PTR;
  38. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  39. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  40. static const struct ddr_data ddr3_sl50_data = {
  41. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  42. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  43. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  44. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  45. };
  46. static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
  47. .cmd0csratio = MT41K256M16HA125E_RATIO,
  48. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  49. .cmd1csratio = MT41K256M16HA125E_RATIO,
  50. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  51. .cmd2csratio = MT41K256M16HA125E_RATIO,
  52. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  53. };
  54. static struct emif_regs ddr3_sl50_emif_reg_data = {
  55. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  56. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  57. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  58. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  59. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  60. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  61. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  62. };
  63. #ifdef CONFIG_SPL_OS_BOOT
  64. int spl_start_uboot(void)
  65. {
  66. /* break into full u-boot on 'c' */
  67. if (serial_tstc() && serial_getc() == 'c')
  68. return 1;
  69. #ifdef CONFIG_SPL_ENV_SUPPORT
  70. env_init();
  71. env_load();
  72. if (env_get_yesno("boot_os") != 1)
  73. return 1;
  74. #endif
  75. return 0;
  76. }
  77. #endif
  78. #define OSC (V_OSCK/1000000)
  79. const struct dpll_params dpll_ddr_sl50 = {
  80. 400, OSC-1, 1, -1, -1, -1, -1};
  81. void am33xx_spl_board_init(void)
  82. {
  83. int mpu_vdd;
  84. /* Get the frequency */
  85. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  86. /* BeagleBone PMIC Code */
  87. int usb_cur_lim;
  88. if (i2c_probe(TPS65217_CHIP_PM))
  89. return;
  90. /*
  91. * Increase USB current limit to 1300mA or 1800mA and set
  92. * the MPU voltage controller as needed.
  93. */
  94. if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  95. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  96. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  97. } else {
  98. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  99. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  100. }
  101. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  102. TPS65217_POWER_PATH,
  103. usb_cur_lim,
  104. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  105. puts("tps65217_reg_write failure\n");
  106. /* Set DCDC3 (CORE) voltage to 1.125V */
  107. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  108. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  109. puts("tps65217_voltage_update failure\n");
  110. return;
  111. }
  112. /* Set CORE Frequencies to OPP100 */
  113. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  114. /* Set DCDC2 (MPU) voltage */
  115. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  116. puts("tps65217_voltage_update failure\n");
  117. return;
  118. }
  119. /*
  120. * Set LDO3 to 1.8V and LDO4 to 3.3V
  121. */
  122. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  123. TPS65217_DEFLS1,
  124. TPS65217_LDO_VOLTAGE_OUT_1_8,
  125. TPS65217_LDO_MASK))
  126. puts("tps65217_reg_write failure\n");
  127. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  128. TPS65217_DEFLS2,
  129. TPS65217_LDO_VOLTAGE_OUT_3_3,
  130. TPS65217_LDO_MASK))
  131. puts("tps65217_reg_write failure\n");
  132. /* Set MPU Frequency to what we detected now that voltages are set */
  133. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  134. }
  135. const struct dpll_params *get_dpll_ddr_params(void)
  136. {
  137. enable_i2c0_pin_mux();
  138. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  139. return &dpll_ddr_sl50;
  140. }
  141. void set_uart_mux_conf(void)
  142. {
  143. #if CONFIG_CONS_INDEX == 1
  144. enable_uart0_pin_mux();
  145. #elif CONFIG_CONS_INDEX == 2
  146. enable_uart1_pin_mux();
  147. #elif CONFIG_CONS_INDEX == 3
  148. enable_uart2_pin_mux();
  149. #elif CONFIG_CONS_INDEX == 4
  150. enable_uart3_pin_mux();
  151. #elif CONFIG_CONS_INDEX == 5
  152. enable_uart4_pin_mux();
  153. #elif CONFIG_CONS_INDEX == 6
  154. enable_uart5_pin_mux();
  155. #endif
  156. }
  157. void set_mux_conf_regs(void)
  158. {
  159. enable_board_pin_mux();
  160. }
  161. const struct ctrl_ioregs ioregs_evmsk = {
  162. .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  163. .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  164. .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
  165. .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  166. .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  167. };
  168. const struct ctrl_ioregs ioregs_bonelt = {
  169. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  170. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  171. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  172. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  173. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  174. };
  175. const struct ctrl_ioregs ioregs_evm15 = {
  176. .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  177. .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  178. .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  179. .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  180. .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  181. };
  182. const struct ctrl_ioregs ioregs = {
  183. .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  184. .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  185. .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  186. .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  187. .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  188. };
  189. void sdram_init(void)
  190. {
  191. config_ddr(400, &ioregs_bonelt,
  192. &ddr3_sl50_data,
  193. &ddr3_sl50_cmd_ctrl_data,
  194. &ddr3_sl50_emif_reg_data, 0);
  195. }
  196. #endif
  197. /*
  198. * Basic board specific setup. Pinmux has been handled already.
  199. */
  200. int board_init(void)
  201. {
  202. #if defined(CONFIG_HW_WATCHDOG)
  203. hw_watchdog_init();
  204. #endif
  205. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  206. return 0;
  207. }
  208. #ifdef CONFIG_BOARD_LATE_INIT
  209. int board_late_init(void)
  210. {
  211. return 0;
  212. }
  213. #endif
  214. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  215. (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
  216. static void cpsw_control(int enabled)
  217. {
  218. /* VTP can be added here */
  219. return;
  220. }
  221. static struct cpsw_slave_data cpsw_slaves[] = {
  222. {
  223. .slave_reg_ofs = 0x208,
  224. .sliver_reg_ofs = 0xd80,
  225. .phy_addr = 0,
  226. },
  227. {
  228. .slave_reg_ofs = 0x308,
  229. .sliver_reg_ofs = 0xdc0,
  230. .phy_addr = 1,
  231. },
  232. };
  233. static struct cpsw_platform_data cpsw_data = {
  234. .mdio_base = CPSW_MDIO_BASE,
  235. .cpsw_base = CPSW_BASE,
  236. .mdio_div = 0xff,
  237. .channels = 8,
  238. .cpdma_reg_ofs = 0x800,
  239. .slaves = 1,
  240. .slave_data = cpsw_slaves,
  241. .ale_reg_ofs = 0xd00,
  242. .ale_entries = 1024,
  243. .host_port_reg_ofs = 0x108,
  244. .hw_stats_reg_ofs = 0x900,
  245. .bd_ram_ofs = 0x2000,
  246. .mac_control = (1 << 5),
  247. .control = cpsw_control,
  248. .host_port_num = 0,
  249. .version = CPSW_CTRL_VERSION_2,
  250. };
  251. #endif
  252. /*
  253. * This function will:
  254. * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
  255. * in the environment
  256. * Perform fixups to the PHY present on certain boards. We only need this
  257. * function in:
  258. * - SPL with either CPSW or USB ethernet support
  259. * - Full U-Boot, with either CPSW or USB ethernet
  260. * Build in only these cases to avoid warnings about unused variables
  261. * when we build an SPL that has neither option but full U-Boot will.
  262. */
  263. #if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \
  264. && defined(CONFIG_SPL_BUILD)) || \
  265. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  266. defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
  267. !defined(CONFIG_SPL_BUILD))
  268. int board_eth_init(struct bd_info *bis)
  269. {
  270. int rv, n = 0;
  271. uint8_t mac_addr[6];
  272. uint32_t mac_hi, mac_lo;
  273. /* try reading mac address from efuse */
  274. mac_lo = readl(&cdev->macid0l);
  275. mac_hi = readl(&cdev->macid0h);
  276. mac_addr[0] = mac_hi & 0xFF;
  277. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  278. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  279. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  280. mac_addr[4] = mac_lo & 0xFF;
  281. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  282. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  283. (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
  284. if (!env_get("ethaddr")) {
  285. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  286. if (is_valid_ethaddr(mac_addr))
  287. eth_env_set_enetaddr("ethaddr", mac_addr);
  288. }
  289. #ifdef CONFIG_DRIVER_TI_CPSW
  290. mac_lo = readl(&cdev->macid1l);
  291. mac_hi = readl(&cdev->macid1h);
  292. mac_addr[0] = mac_hi & 0xFF;
  293. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  294. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  295. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  296. mac_addr[4] = mac_lo & 0xFF;
  297. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  298. if (!env_get("eth1addr")) {
  299. if (is_valid_ethaddr(mac_addr))
  300. eth_env_set_enetaddr("eth1addr", mac_addr);
  301. }
  302. writel(MII_MODE_ENABLE, &cdev->miisel);
  303. cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
  304. PHY_INTERFACE_MODE_MII;
  305. rv = cpsw_register(&cpsw_data);
  306. if (rv < 0)
  307. printf("Error %d registering CPSW switch\n", rv);
  308. else
  309. n += rv;
  310. #endif
  311. /*
  312. *
  313. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  314. * operating points. So we must set the TX clock delay feature
  315. * in the AR8051 PHY. Since we only support a single ethernet
  316. * device in U-Boot, we only do this for the first instance.
  317. */
  318. #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
  319. #define AR8051_PHY_DEBUG_DATA_REG 0x1e
  320. #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
  321. #define AR8051_RGMII_TX_CLK_DLY 0x100
  322. #endif
  323. #if defined(CONFIG_USB_ETHER) && \
  324. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
  325. if (is_valid_ether_addr(mac_addr))
  326. eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
  327. rv = usb_eth_initialize(bis);
  328. if (rv < 0)
  329. printf("Error %d registering USB_ETHER\n", rv);
  330. else
  331. n += rv;
  332. #endif
  333. return n;
  334. }
  335. #endif