board.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for TI AM335X based draco board
  4. * (C) Copyright 2013 Siemens Schweiz AG
  5. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * Based on:
  8. *
  9. * Board functions for TI AM335X based boards
  10. * u-boot:/board/ti/am335x/board.c
  11. *
  12. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  13. */
  14. #include <common.h>
  15. #include <command.h>
  16. #include <env.h>
  17. #include <errno.h>
  18. #include <init.h>
  19. #include <net.h>
  20. #include <spl.h>
  21. #include <asm/arch/cpu.h>
  22. #include <asm/arch/hardware.h>
  23. #include <asm/arch/omap.h>
  24. #include <asm/arch/ddr_defs.h>
  25. #include <asm/arch/clock.h>
  26. #include <asm/arch/gpio.h>
  27. #include <asm/arch/mmc_host_def.h>
  28. #include <asm/arch/sys_proto.h>
  29. #include <asm/arch/mem.h>
  30. #include <asm/io.h>
  31. #include <asm/emif.h>
  32. #include <asm/gpio.h>
  33. #include <i2c.h>
  34. #include <miiphy.h>
  35. #include <cpsw.h>
  36. #include <watchdog.h>
  37. #include <linux/delay.h>
  38. #include "board.h"
  39. #include "../common/factoryset.h"
  40. #include <nand.h>
  41. #ifdef CONFIG_SPL_BUILD
  42. static struct draco_baseboard_id __section(".data") settings;
  43. #if DDR_PLL_FREQ == 303
  44. #if !defined(CONFIG_TARGET_ETAMIN)
  45. /* Default@303MHz-i0 */
  46. const struct ddr3_data ddr3_default = {
  47. 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
  48. 0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
  49. 0x0000093B, 0x0000014A,
  50. "default name @303MHz \0",
  51. "default marking \0",
  52. };
  53. #else
  54. /* etamin board */
  55. const struct ddr3_data ddr3_default = {
  56. 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
  57. 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
  58. 0x0000093B, 0x0000018A,
  59. "test-etamin \0",
  60. "generic-8Gbit \0",
  61. };
  62. #endif
  63. #elif DDR_PLL_FREQ == 400
  64. /* Default@400MHz-i0 */
  65. const struct ddr3_data ddr3_default = {
  66. 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
  67. 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
  68. 0x00000618, 0x0000014A,
  69. "default name @400MHz \0",
  70. "default marking \0",
  71. };
  72. #endif
  73. static void set_default_ddr3_timings(void)
  74. {
  75. printf("Set default DDR3 settings\n");
  76. settings.ddr3 = ddr3_default;
  77. }
  78. static void print_ddr3_timings(void)
  79. {
  80. printf("\nDDR3\n");
  81. printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
  82. printf("device:\t\t%s\n", settings.ddr3.manu_name);
  83. printf("marking:\t%s\n", settings.ddr3.manu_marking);
  84. printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
  85. "default", "diff");
  86. PRINTARGS(magic);
  87. PRINTARGS(version);
  88. PRINTARGS(ddr3_sratio);
  89. PRINTARGS(iclkout);
  90. PRINTARGS(dt0rdsratio0);
  91. PRINTARGS(dt0wdsratio0);
  92. PRINTARGS(dt0fwsratio0);
  93. PRINTARGS(dt0wrsratio0);
  94. PRINTARGS(sdram_tim1);
  95. PRINTARGS(sdram_tim2);
  96. PRINTARGS(sdram_tim3);
  97. PRINTARGS(emif_ddr_phy_ctlr_1);
  98. PRINTARGS(sdram_config);
  99. PRINTARGS(ref_ctrl);
  100. PRINTARGS(ioctr_val);
  101. }
  102. static void print_chip_data(void)
  103. {
  104. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  105. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  106. printf("\nCPU BOARD\n");
  107. printf("device: \t'%s'\n", settings.chip.sdevname);
  108. printf("hw version: \t'%s'\n", settings.chip.shwver);
  109. printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
  110. }
  111. #endif /* CONFIG_SPL_BUILD */
  112. #define AM335X_NAND_ECC_MASK 0x0f
  113. #define AM335X_NAND_ECC_TYPE_16 0x02
  114. static int ecc_type;
  115. struct am335x_nand_geometry {
  116. u32 magic;
  117. u8 nand_geo_addr;
  118. u8 nand_geo_page;
  119. u8 nand_bus;
  120. };
  121. static int draco_read_nand_geometry(void)
  122. {
  123. struct am335x_nand_geometry geo;
  124. /* Read NAND geometry */
  125. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
  126. (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
  127. printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
  128. return -EIO;
  129. }
  130. if (geo.magic != 0xa657b310) {
  131. printf("%s: bad magic: %x\n", __func__, geo.magic);
  132. return -EFAULT;
  133. }
  134. if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
  135. ecc_type = 16;
  136. else
  137. ecc_type = 8;
  138. return 0;
  139. }
  140. /*
  141. * Read header information from EEPROM into global structure.
  142. */
  143. static int read_eeprom(void)
  144. {
  145. /* Check if baseboard eeprom is available */
  146. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  147. printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
  148. return 1;
  149. }
  150. #ifdef CONFIG_SPL_BUILD
  151. /* Read Siemens eeprom data (DDR3) */
  152. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
  153. (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
  154. printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
  155. set_default_ddr3_timings();
  156. }
  157. /* Read Siemens eeprom data (CHIP) */
  158. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
  159. (uchar *)&settings.chip, sizeof(settings.chip)))
  160. printf("Could not read chip settings\n");
  161. if (ddr3_default.magic == settings.ddr3.magic &&
  162. ddr3_default.version == settings.ddr3.version) {
  163. printf("Using DDR3 settings from EEPROM\n");
  164. } else {
  165. if (ddr3_default.magic != settings.ddr3.magic)
  166. printf("Warning: No valid DDR3 data in eeprom.\n");
  167. if (ddr3_default.version != settings.ddr3.version)
  168. printf("Warning: DDR3 data version does not match.\n");
  169. printf("Using default settings\n");
  170. set_default_ddr3_timings();
  171. }
  172. if (MAGIC_CHIP == settings.chip.magic)
  173. print_chip_data();
  174. else
  175. printf("Warning: No chip data in eeprom\n");
  176. print_ddr3_timings();
  177. return draco_read_nand_geometry();
  178. #endif
  179. return 0;
  180. }
  181. #ifdef CONFIG_SPL_BUILD
  182. static void board_init_ddr(void)
  183. {
  184. struct emif_regs draco_ddr3_emif_reg_data = {
  185. .zq_config = 0x50074BE4,
  186. };
  187. struct ddr_data draco_ddr3_data = {
  188. };
  189. struct cmd_control draco_ddr3_cmd_ctrl_data = {
  190. };
  191. struct ctrl_ioregs draco_ddr3_ioregs = {
  192. };
  193. /* pass values from eeprom */
  194. draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
  195. draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
  196. draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
  197. draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
  198. settings.ddr3.emif_ddr_phy_ctlr_1;
  199. draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
  200. draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
  201. draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
  202. draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
  203. draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
  204. draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
  205. draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
  206. draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
  207. draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
  208. draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
  209. draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
  210. draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
  211. draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
  212. draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
  213. draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
  214. draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
  215. draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
  216. draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
  217. config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
  218. &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
  219. }
  220. static void spl_siemens_board_init(void)
  221. {
  222. return;
  223. }
  224. #endif /* if def CONFIG_SPL_BUILD */
  225. #ifdef CONFIG_BOARD_LATE_INIT
  226. int board_late_init(void)
  227. {
  228. int ret;
  229. ret = draco_read_nand_geometry();
  230. if (ret != 0)
  231. return ret;
  232. nand_curr_device = 0;
  233. omap_nand_switch_ecc(1, ecc_type);
  234. #ifdef CONFIG_TARGET_ETAMIN
  235. nand_curr_device = 1;
  236. omap_nand_switch_ecc(1, ecc_type);
  237. #endif
  238. #ifdef CONFIG_FACTORYSET
  239. /* Set ASN in environment*/
  240. if (factory_dat.asn[0] != 0) {
  241. env_set("dtb_name", (char *)factory_dat.asn);
  242. } else {
  243. /* dtb suffix gets added in load script */
  244. env_set("dtb_name", "am335x-draco");
  245. }
  246. #else
  247. env_set("dtb_name", "am335x-draco");
  248. #endif
  249. return 0;
  250. }
  251. #endif
  252. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  253. (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
  254. static void cpsw_control(int enabled)
  255. {
  256. /* VTP can be added here */
  257. return;
  258. }
  259. static struct cpsw_slave_data cpsw_slaves[] = {
  260. {
  261. .slave_reg_ofs = 0x208,
  262. .sliver_reg_ofs = 0xd80,
  263. .phy_addr = 0,
  264. .phy_if = PHY_INTERFACE_MODE_MII,
  265. },
  266. };
  267. static struct cpsw_platform_data cpsw_data = {
  268. .mdio_base = CPSW_MDIO_BASE,
  269. .cpsw_base = CPSW_BASE,
  270. .mdio_div = 0xff,
  271. .channels = 4,
  272. .cpdma_reg_ofs = 0x800,
  273. .slaves = 1,
  274. .slave_data = cpsw_slaves,
  275. .ale_reg_ofs = 0xd00,
  276. .ale_entries = 1024,
  277. .host_port_reg_ofs = 0x108,
  278. .hw_stats_reg_ofs = 0x900,
  279. .bd_ram_ofs = 0x2000,
  280. .mac_control = (1 << 5),
  281. .control = cpsw_control,
  282. .host_port_num = 0,
  283. .version = CPSW_CTRL_VERSION_2,
  284. };
  285. #if defined(CONFIG_DRIVER_TI_CPSW) || \
  286. (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
  287. int board_eth_init(struct bd_info *bis)
  288. {
  289. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  290. int n = 0;
  291. int rv;
  292. factoryset_env_set();
  293. /* Set rgmii mode and enable rmii clock to be sourced from chip */
  294. writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
  295. rv = cpsw_register(&cpsw_data);
  296. if (rv < 0)
  297. printf("Error %d registering CPSW switch\n", rv);
  298. else
  299. n += rv;
  300. return n;
  301. }
  302. static int do_switch_reset(struct cmd_tbl *cmdtp, int flag, int argc,
  303. char *const argv[])
  304. {
  305. /* Reset SMSC LAN9303 switch for default configuration */
  306. gpio_request(GPIO_LAN9303_NRST, "nRST");
  307. gpio_direction_output(GPIO_LAN9303_NRST, 0);
  308. /* assert active low reset for 200us */
  309. udelay(200);
  310. gpio_set_value(GPIO_LAN9303_NRST, 1);
  311. return 0;
  312. };
  313. U_BOOT_CMD(
  314. switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
  315. "Reset LAN9303 switch via its reset pin",
  316. ""
  317. );
  318. #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
  319. #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
  320. #ifdef CONFIG_NAND_CS_INIT
  321. /* GPMC definitions for second nand cs1 */
  322. static const u32 gpmc_nand_config[] = {
  323. ETAMIN_NAND_GPMC_CONFIG1,
  324. ETAMIN_NAND_GPMC_CONFIG2,
  325. ETAMIN_NAND_GPMC_CONFIG3,
  326. ETAMIN_NAND_GPMC_CONFIG4,
  327. ETAMIN_NAND_GPMC_CONFIG5,
  328. ETAMIN_NAND_GPMC_CONFIG6,
  329. /*CONFIG7- computed as params */
  330. };
  331. static void board_nand_cs_init(void)
  332. {
  333. enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
  334. 0x18000000, GPMC_SIZE_16M);
  335. }
  336. #endif
  337. #include "../common/board.c"