sh_spi.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SH SPI driver
  4. *
  5. * Copyright (C) 2011-2012 Renesas Solutions Corp.
  6. */
  7. #include <common.h>
  8. #include <console.h>
  9. #include <malloc.h>
  10. #include <spi.h>
  11. #include <asm/io.h>
  12. #include <linux/delay.h>
  13. #include "sh_spi.h"
  14. static void sh_spi_write(unsigned long data, unsigned long *reg)
  15. {
  16. writel(data, reg);
  17. }
  18. static unsigned long sh_spi_read(unsigned long *reg)
  19. {
  20. return readl(reg);
  21. }
  22. static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
  23. {
  24. unsigned long tmp;
  25. tmp = sh_spi_read(reg);
  26. tmp |= val;
  27. sh_spi_write(tmp, reg);
  28. }
  29. static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
  30. {
  31. unsigned long tmp;
  32. tmp = sh_spi_read(reg);
  33. tmp &= ~val;
  34. sh_spi_write(tmp, reg);
  35. }
  36. static void clear_fifo(struct sh_spi *ss)
  37. {
  38. sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
  39. sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
  40. }
  41. static int recvbuf_wait(struct sh_spi *ss)
  42. {
  43. while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
  44. if (ctrlc())
  45. return 1;
  46. udelay(10);
  47. }
  48. return 0;
  49. }
  50. static int write_fifo_empty_wait(struct sh_spi *ss)
  51. {
  52. while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
  53. if (ctrlc())
  54. return 1;
  55. udelay(10);
  56. }
  57. return 0;
  58. }
  59. static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
  60. {
  61. unsigned long val = 0;
  62. if (cs & 0x01)
  63. val |= SH_SPI_SSS0;
  64. if (cs & 0x02)
  65. val |= SH_SPI_SSS1;
  66. sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
  67. sh_spi_set_bit(val, &ss->regs->cr4);
  68. }
  69. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  70. unsigned int max_hz, unsigned int mode)
  71. {
  72. struct sh_spi *ss;
  73. if (!spi_cs_is_valid(bus, cs))
  74. return NULL;
  75. ss = spi_alloc_slave(struct sh_spi, bus, cs);
  76. if (!ss)
  77. return NULL;
  78. ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
  79. /* SPI sycle stop */
  80. sh_spi_write(0xfe, &ss->regs->cr1);
  81. /* CR1 init */
  82. sh_spi_write(0x00, &ss->regs->cr1);
  83. /* CR3 init */
  84. sh_spi_write(0x00, &ss->regs->cr3);
  85. sh_spi_set_cs(ss, cs);
  86. clear_fifo(ss);
  87. /* 1/8 clock */
  88. sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
  89. udelay(10);
  90. return &ss->slave;
  91. }
  92. void spi_free_slave(struct spi_slave *slave)
  93. {
  94. struct sh_spi *spi = to_sh_spi(slave);
  95. free(spi);
  96. }
  97. int spi_claim_bus(struct spi_slave *slave)
  98. {
  99. return 0;
  100. }
  101. void spi_release_bus(struct spi_slave *slave)
  102. {
  103. struct sh_spi *ss = to_sh_spi(slave);
  104. sh_spi_write(sh_spi_read(&ss->regs->cr1) &
  105. ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
  106. }
  107. static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
  108. unsigned int len, unsigned long flags)
  109. {
  110. int i, cur_len, ret = 0;
  111. int remain = (int)len;
  112. if (len >= SH_SPI_FIFO_SIZE)
  113. sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
  114. while (remain > 0) {
  115. cur_len = (remain < SH_SPI_FIFO_SIZE) ?
  116. remain : SH_SPI_FIFO_SIZE;
  117. for (i = 0; i < cur_len &&
  118. !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
  119. !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
  120. i++)
  121. sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
  122. cur_len = i;
  123. if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
  124. /* Abort the transaction */
  125. flags |= SPI_XFER_END;
  126. sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
  127. ret = 1;
  128. break;
  129. }
  130. remain -= cur_len;
  131. tx_data += cur_len;
  132. if (remain > 0)
  133. write_fifo_empty_wait(ss);
  134. }
  135. if (flags & SPI_XFER_END) {
  136. sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
  137. sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
  138. udelay(100);
  139. write_fifo_empty_wait(ss);
  140. }
  141. return ret;
  142. }
  143. static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
  144. unsigned int len, unsigned long flags)
  145. {
  146. int i;
  147. if (len > SH_SPI_MAX_BYTE)
  148. sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
  149. else
  150. sh_spi_write(len, &ss->regs->cr3);
  151. sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
  152. sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
  153. for (i = 0; i < len; i++) {
  154. if (recvbuf_wait(ss))
  155. return 0;
  156. rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
  157. }
  158. sh_spi_write(0, &ss->regs->cr3);
  159. return 0;
  160. }
  161. int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
  162. void *din, unsigned long flags)
  163. {
  164. struct sh_spi *ss = to_sh_spi(slave);
  165. const unsigned char *tx_data = dout;
  166. unsigned char *rx_data = din;
  167. unsigned int len = bitlen / 8;
  168. int ret = 0;
  169. if (flags & SPI_XFER_BEGIN)
  170. sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
  171. &ss->regs->cr1);
  172. if (tx_data)
  173. ret = sh_spi_send(ss, tx_data, len, flags);
  174. if (ret == 0 && rx_data)
  175. ret = sh_spi_receive(ss, rx_data, len, flags);
  176. if (flags & SPI_XFER_END) {
  177. sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
  178. udelay(100);
  179. sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
  180. &ss->regs->cr1);
  181. clear_fifo(ss);
  182. }
  183. return ret;
  184. }
  185. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  186. {
  187. if (!bus && cs < SH_SPI_NUM_CS)
  188. return 1;
  189. else
  190. return 0;
  191. }
  192. void spi_cs_activate(struct spi_slave *slave)
  193. {
  194. }
  195. void spi_cs_deactivate(struct spi_slave *slave)
  196. {
  197. }