rk_mipi.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
  4. * Author: Eric Gao <eric.gao@rock-chips.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <panel.h>
  12. #include <regmap.h>
  13. #include "rk_mipi.h"
  14. #include <syscon.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <dm/uclass-internal.h>
  18. #include <linux/kernel.h>
  19. #include <asm/arch-rockchip/clock.h>
  20. #include <asm/arch-rockchip/cru.h>
  21. #include <asm/arch-rockchip/grf_rk3399.h>
  22. #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int rk_mipi_read_timing(struct udevice *dev,
  25. struct display_timing *timing)
  26. {
  27. int ret;
  28. ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing);
  29. if (ret) {
  30. debug("%s: Failed to decode display timing (ret=%d)\n",
  31. __func__, ret);
  32. return -EINVAL;
  33. }
  34. return 0;
  35. }
  36. /*
  37. * Register write function used only for mipi dsi controller.
  38. * Parameter:
  39. * @regs: mipi controller address
  40. * @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can
  41. * use define in rk_mipi.h directly for this parameter
  42. * @val: value that will be write to specified bits of register
  43. */
  44. static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val)
  45. {
  46. u32 dat;
  47. u32 mask;
  48. u32 offset = (reg >> OFFSET_SHIFT) & 0xff;
  49. u32 bits = (reg >> BITS_SHIFT) & 0xff;
  50. uintptr_t addr = (reg >> ADDR_SHIFT) + regs;
  51. /* Mask for specifiled bits,the corresponding bits will be clear */
  52. mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits)));
  53. /* Make sure val in the available range */
  54. val &= ~(0xffffffff << bits);
  55. /* Get register's original val */
  56. dat = readl(addr);
  57. /* Clear specified bits */
  58. dat &= mask;
  59. /* Fill specified bits */
  60. dat |= val << offset;
  61. writel(dat, addr);
  62. }
  63. int rk_mipi_dsi_enable(struct udevice *dev,
  64. const struct display_timing *timing)
  65. {
  66. ofnode node, timing_node;
  67. int val;
  68. struct rk_mipi_priv *priv = dev_get_priv(dev);
  69. uintptr_t regs = priv->regs;
  70. u32 txbyte_clk = priv->txbyte_clk;
  71. u32 txesc_clk = priv->txesc_clk;
  72. txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
  73. /* Set Display timing parameter */
  74. rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
  75. rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
  76. rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ
  77. + timing->hback_porch.typ + timing->hactive.typ
  78. + timing->hfront_porch.typ));
  79. rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);
  80. rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);
  81. rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);
  82. rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);
  83. /* Set Signal Polarity */
  84. val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
  85. rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val);
  86. val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
  87. rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val);
  88. val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
  89. rk_mipi_dsi_write(regs, DATAEN_ACTIVE_LOW, val);
  90. val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
  91. rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val);
  92. /* Set video mode */
  93. rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE);
  94. /* Set video mode transmission type as burst mode */
  95. rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE);
  96. /* Set pix num in a video package */
  97. rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
  98. /* Set dpi color coding depth 24 bit */
  99. timing_node = ofnode_find_subnode(dev_ofnode(dev), "display-timings");
  100. node = ofnode_first_subnode(timing_node);
  101. val = ofnode_read_u32_default(node, "bits-per-pixel", -1);
  102. switch (val) {
  103. case 16:
  104. rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);
  105. break;
  106. case 24:
  107. rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
  108. break;
  109. case 30:
  110. rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT);
  111. break;
  112. default:
  113. rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
  114. }
  115. /* Enable low power mode */
  116. rk_mipi_dsi_write(regs, LP_CMD_EN, 1);
  117. rk_mipi_dsi_write(regs, LP_HFP_EN, 1);
  118. rk_mipi_dsi_write(regs, LP_VACT_EN, 1);
  119. rk_mipi_dsi_write(regs, LP_VFP_EN, 1);
  120. rk_mipi_dsi_write(regs, LP_VBP_EN, 1);
  121. rk_mipi_dsi_write(regs, LP_VSA_EN, 1);
  122. /* Division for timeout counter clk */
  123. rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a);
  124. /* Tx esc clk division from txbyte clk */
  125. rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);
  126. /* Timeout count for hs<->lp transation between Line period */
  127. rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8);
  128. /* Phy State transfer timing */
  129. rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32);
  130. rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1);
  131. rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14);
  132. rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10);
  133. rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710);
  134. /* Power on */
  135. rk_mipi_dsi_write(regs, SHUTDOWNZ, 1);
  136. return 0;
  137. }
  138. /* rk mipi dphy write function. It is used to write test data to dphy */
  139. static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code,
  140. unsigned char *test_data, unsigned char size)
  141. {
  142. int i = 0;
  143. /* Write Test code */
  144. rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
  145. rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code);
  146. rk_mipi_dsi_write(regs, PHY_TESTEN, 1);
  147. rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
  148. rk_mipi_dsi_write(regs, PHY_TESTEN, 0);
  149. /* Write Test data */
  150. for (i = 0; i < size; i++) {
  151. rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
  152. rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]);
  153. rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
  154. }
  155. }
  156. /*
  157. * Mipi dphy config function. Calculate the suitable prediv, feedback div,
  158. * fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate,
  159. * and then enable phy.
  160. */
  161. int rk_mipi_phy_enable(struct udevice *dev)
  162. {
  163. int i;
  164. struct rk_mipi_priv *priv = dev_get_priv(dev);
  165. uintptr_t regs = priv->regs;
  166. u64 fbdiv;
  167. u64 prediv = 1;
  168. u32 max_fbdiv = 512;
  169. u32 max_prediv, min_prediv;
  170. u64 ddr_clk = priv->phy_clk;
  171. u32 refclk = priv->ref_clk;
  172. u32 remain = refclk;
  173. unsigned char test_data[2] = {0};
  174. int freq_rang[][2] = {
  175. {90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01},
  176. {140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12},
  177. {200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23},
  178. {270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15},
  179. {400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07},
  180. {600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09},
  181. {800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a},
  182. {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
  183. {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
  184. {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
  185. };
  186. /* Shutdown mode */
  187. rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0);
  188. rk_mipi_dsi_write(regs, PHY_RSTZ, 0);
  189. rk_mipi_dsi_write(regs, PHY_TESTCLR, 1);
  190. /* Pll locking */
  191. rk_mipi_dsi_write(regs, PHY_TESTCLR, 0);
  192. /* config cp and lfp */
  193. test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
  194. rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1);
  195. test_data[0] = 0x8;
  196. rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1);
  197. test_data[0] = 0x80 | 0x40;
  198. rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1);
  199. /* select the suitable value for fsfreqrang reg */
  200. for (i = 0; i < ARRAY_SIZE(freq_rang); i++) {
  201. if (ddr_clk / (MHz) <= freq_rang[i][0])
  202. break;
  203. }
  204. if (i == ARRAY_SIZE(freq_rang)) {
  205. debug("%s: Dphy freq out of range!\n", __func__);
  206. return -EINVAL;
  207. }
  208. test_data[0] = freq_rang[i][1] << 1;
  209. rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1);
  210. /*
  211. * Calculate the best ddrclk and it's corresponding div value. If the
  212. * given pixelclock is great than 250M, ddrclk will be fix 1500M.
  213. * Otherwise,
  214. * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
  215. * according to spec.
  216. */
  217. max_prediv = (refclk / (5 * MHz));
  218. min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
  219. debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv,
  220. min_prediv);
  221. if (max_prediv < min_prediv) {
  222. debug("%s: Invalid refclk value\n", __func__);
  223. return -EINVAL;
  224. }
  225. /* Calculate the best refclk and feedback division value for dphy pll */
  226. for (i = min_prediv; i < max_prediv; i++) {
  227. if ((ddr_clk * i % refclk < remain) &&
  228. (ddr_clk * i / refclk) < max_fbdiv) {
  229. prediv = i;
  230. remain = ddr_clk * i % refclk;
  231. }
  232. }
  233. fbdiv = ddr_clk * prediv / refclk;
  234. ddr_clk = refclk * fbdiv / prediv;
  235. priv->phy_clk = ddr_clk;
  236. debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",
  237. __func__, refclk, prediv, fbdiv, ddr_clk);
  238. /* config prediv and feedback reg */
  239. test_data[0] = prediv - 1;
  240. rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1);
  241. test_data[0] = (fbdiv - 1) & 0x1f;
  242. rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
  243. test_data[0] = (fbdiv - 1) >> 5 | 0x80;
  244. rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
  245. test_data[0] = 0x30;
  246. rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1);
  247. /* rest config */
  248. test_data[0] = 0x4d;
  249. rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1);
  250. test_data[0] = 0x3d;
  251. rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
  252. test_data[0] = 0xdf;
  253. rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
  254. test_data[0] = 0x7;
  255. rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
  256. test_data[0] = 0x80 | 0x7;
  257. rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
  258. test_data[0] = 0x80 | 15;
  259. rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME,
  260. test_data, 1);
  261. test_data[0] = 0x80 | 85;
  262. rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME,
  263. test_data, 1);
  264. test_data[0] = 0x40 | 10;
  265. rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME,
  266. test_data, 1);
  267. /* enter into stop mode */
  268. rk_mipi_dsi_write(regs, N_LANES, 0x03);
  269. rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1);
  270. rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1);
  271. rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1);
  272. rk_mipi_dsi_write(regs, PHY_RSTZ, 1);
  273. return 0;
  274. }