nexell_display.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Nexell Co., Ltd.
  4. *
  5. * Author: junghyun, kim <jhkim@nexell.co.kr>
  6. *
  7. * Copyright (C) 2020 Stefan Bosch <stefan_b@posteo.net>
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <command.h>
  12. #include <dm.h>
  13. #include <mapmem.h>
  14. #include <malloc.h>
  15. #include <linux/compat.h>
  16. #include <linux/err.h>
  17. #include <video.h> /* For struct video_uc_platdata */
  18. #include <video_fb.h>
  19. #include <lcd.h>
  20. #include <asm/global_data.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/display.h>
  23. #include <asm/arch/display_dev.h>
  24. #include "videomodes.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #if !defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)
  27. static struct nx_display_dev *dp_dev;
  28. #endif
  29. static char *const dp_dev_str[] = {
  30. [DP_DEVICE_RESCONV] = "RESCONV",
  31. [DP_DEVICE_RGBLCD] = "LCD",
  32. [DP_DEVICE_HDMI] = "HDMI",
  33. [DP_DEVICE_MIPI] = "MiPi",
  34. [DP_DEVICE_LVDS] = "LVDS",
  35. [DP_DEVICE_CVBS] = "TVOUT",
  36. [DP_DEVICE_DP0] = "DP0",
  37. [DP_DEVICE_DP1] = "DP1",
  38. };
  39. #if CONFIG_IS_ENABLED(OF_CONTROL)
  40. static void nx_display_parse_dp_sync(ofnode node, struct dp_sync_info *sync)
  41. {
  42. sync->h_active_len = ofnode_read_s32_default(node, "h_active_len", 0);
  43. sync->h_sync_width = ofnode_read_s32_default(node, "h_sync_width", 0);
  44. sync->h_back_porch = ofnode_read_s32_default(node, "h_back_porch", 0);
  45. sync->h_front_porch = ofnode_read_s32_default(node, "h_front_porch", 0);
  46. sync->h_sync_invert = ofnode_read_s32_default(node, "h_sync_invert", 0);
  47. sync->v_active_len = ofnode_read_s32_default(node, "v_active_len", 0);
  48. sync->v_sync_width = ofnode_read_s32_default(node, "v_sync_width", 0);
  49. sync->v_back_porch = ofnode_read_s32_default(node, "v_back_porch", 0);
  50. sync->v_front_porch = ofnode_read_s32_default(node, "v_front_porch", 0);
  51. sync->v_sync_invert = ofnode_read_s32_default(node, "v_sync_invert", 0);
  52. sync->pixel_clock_hz = ofnode_read_s32_default(node, "pixel_clock_hz", 0);
  53. debug("DP: sync ->\n");
  54. debug("ha:%d, hs:%d, hb:%d, hf:%d, hi:%d\n",
  55. sync->h_active_len, sync->h_sync_width,
  56. sync->h_back_porch, sync->h_front_porch, sync->h_sync_invert);
  57. debug("va:%d, vs:%d, vb:%d, vf:%d, vi:%d\n",
  58. sync->v_active_len, sync->v_sync_width,
  59. sync->v_back_porch, sync->v_front_porch, sync->v_sync_invert);
  60. }
  61. static void nx_display_parse_dp_ctrl(ofnode node, struct dp_ctrl_info *ctrl)
  62. {
  63. /* clock gen */
  64. ctrl->clk_src_lv0 = ofnode_read_s32_default(node, "clk_src_lv0", 0);
  65. ctrl->clk_div_lv0 = ofnode_read_s32_default(node, "clk_div_lv0", 0);
  66. ctrl->clk_src_lv1 = ofnode_read_s32_default(node, "clk_src_lv1", 0);
  67. ctrl->clk_div_lv1 = ofnode_read_s32_default(node, "clk_div_lv1", 0);
  68. /* scan format */
  69. ctrl->interlace = ofnode_read_s32_default(node, "interlace", 0);
  70. /* syncgen format */
  71. ctrl->out_format = ofnode_read_s32_default(node, "out_format", 0);
  72. ctrl->invert_field = ofnode_read_s32_default(node, "invert_field", 0);
  73. ctrl->swap_RB = ofnode_read_s32_default(node, "swap_RB", 0);
  74. ctrl->yc_order = ofnode_read_s32_default(node, "yc_order", 0);
  75. /* extern sync delay */
  76. ctrl->delay_mask = ofnode_read_s32_default(node, "delay_mask", 0);
  77. ctrl->d_rgb_pvd = ofnode_read_s32_default(node, "d_rgb_pvd", 0);
  78. ctrl->d_hsync_cp1 = ofnode_read_s32_default(node, "d_hsync_cp1", 0);
  79. ctrl->d_vsync_fram = ofnode_read_s32_default(node, "d_vsync_fram", 0);
  80. ctrl->d_de_cp2 = ofnode_read_s32_default(node, "d_de_cp2", 0);
  81. /* extern sync delay */
  82. ctrl->vs_start_offset =
  83. ofnode_read_s32_default(node, "vs_start_offset", 0);
  84. ctrl->vs_end_offset = ofnode_read_s32_default(node, "vs_end_offset", 0);
  85. ctrl->ev_start_offset =
  86. ofnode_read_s32_default(node, "ev_start_offset", 0);
  87. ctrl->ev_end_offset = ofnode_read_s32_default(node, "ev_end_offset", 0);
  88. /* pad clock seletor */
  89. ctrl->vck_select = ofnode_read_s32_default(node, "vck_select", 0);
  90. ctrl->clk_inv_lv0 = ofnode_read_s32_default(node, "clk_inv_lv0", 0);
  91. ctrl->clk_delay_lv0 = ofnode_read_s32_default(node, "clk_delay_lv0", 0);
  92. ctrl->clk_inv_lv1 = ofnode_read_s32_default(node, "clk_inv_lv1", 0);
  93. ctrl->clk_delay_lv1 = ofnode_read_s32_default(node, "clk_delay_lv1", 0);
  94. ctrl->clk_sel_div1 = ofnode_read_s32_default(node, "clk_sel_div1", 0);
  95. debug("DP: ctrl [%s] ->\n",
  96. ctrl->interlace ? "Interlace" : " Progressive");
  97. debug("cs0:%d, cd0:%d, cs1:%d, cd1:%d\n",
  98. ctrl->clk_src_lv0, ctrl->clk_div_lv0,
  99. ctrl->clk_src_lv1, ctrl->clk_div_lv1);
  100. debug("fmt:0x%x, inv:%d, swap:%d, yb:0x%x\n",
  101. ctrl->out_format, ctrl->invert_field,
  102. ctrl->swap_RB, ctrl->yc_order);
  103. debug("dm:0x%x, drp:%d, dhs:%d, dvs:%d, dde:0x%x\n",
  104. ctrl->delay_mask, ctrl->d_rgb_pvd,
  105. ctrl->d_hsync_cp1, ctrl->d_vsync_fram, ctrl->d_de_cp2);
  106. debug("vss:%d, vse:%d, evs:%d, eve:%d\n",
  107. ctrl->vs_start_offset, ctrl->vs_end_offset,
  108. ctrl->ev_start_offset, ctrl->ev_end_offset);
  109. debug("sel:%d, i0:%d, d0:%d, i1:%d, d1:%d, s1:%d\n",
  110. ctrl->vck_select, ctrl->clk_inv_lv0, ctrl->clk_delay_lv0,
  111. ctrl->clk_inv_lv1, ctrl->clk_delay_lv1, ctrl->clk_sel_div1);
  112. }
  113. static void nx_display_parse_dp_top_layer(ofnode node, struct dp_plane_top *top)
  114. {
  115. top->screen_width = ofnode_read_s32_default(node, "screen_width", 0);
  116. top->screen_height = ofnode_read_s32_default(node, "screen_height", 0);
  117. top->video_prior = ofnode_read_s32_default(node, "video_prior", 0);
  118. top->interlace = ofnode_read_s32_default(node, "interlace", 0);
  119. top->back_color = ofnode_read_s32_default(node, "back_color", 0);
  120. top->plane_num = DP_PLANS_NUM;
  121. debug("DP: top [%s] ->\n",
  122. top->interlace ? "Interlace" : " Progressive");
  123. debug("w:%d, h:%d, prior:%d, bg:0x%x\n",
  124. top->screen_width, top->screen_height,
  125. top->video_prior, top->back_color);
  126. }
  127. static void nx_display_parse_dp_layer(ofnode node, struct dp_plane_info *plane)
  128. {
  129. plane->left = ofnode_read_s32_default(node, "left", 0);
  130. plane->width = ofnode_read_s32_default(node, "width", 0);
  131. plane->top = ofnode_read_s32_default(node, "top", 0);
  132. plane->height = ofnode_read_s32_default(node, "height", 0);
  133. plane->pixel_byte = ofnode_read_s32_default(node, "pixel_byte", 0);
  134. plane->format = ofnode_read_s32_default(node, "format", 0);
  135. plane->alpha_on = ofnode_read_s32_default(node, "alpha_on", 0);
  136. plane->alpha_depth = ofnode_read_s32_default(node, "alpha", 0);
  137. plane->tp_on = ofnode_read_s32_default(node, "tp_on", 0);
  138. plane->tp_color = ofnode_read_s32_default(node, "tp_color", 0);
  139. /* enable layer */
  140. if (plane->fb_base)
  141. plane->enable = 1;
  142. else
  143. plane->enable = 0;
  144. if (plane->fb_base == 0) {
  145. printf("fail : dp plane.%d invalid fb base [0x%x] ->\n",
  146. plane->layer, plane->fb_base);
  147. return;
  148. }
  149. debug("DP: plane.%d [0x%x] ->\n", plane->layer, plane->fb_base);
  150. debug("f:0x%x, l:%d, t:%d, %d * %d, bpp:%d, a:%d(%d), t:%d(0x%x)\n",
  151. plane->format, plane->left, plane->top, plane->width,
  152. plane->height, plane->pixel_byte, plane->alpha_on,
  153. plane->alpha_depth, plane->tp_on, plane->tp_color);
  154. }
  155. static void nx_display_parse_dp_planes(ofnode node,
  156. struct nx_display_dev *dp,
  157. struct video_uc_plat *plat)
  158. {
  159. const char *name;
  160. ofnode subnode;
  161. ofnode_for_each_subnode(subnode, node) {
  162. name = ofnode_get_name(subnode);
  163. if (strcmp(name, "layer_top") == 0)
  164. nx_display_parse_dp_top_layer(subnode, &dp->top);
  165. /*
  166. * TODO: Is it sure that only one layer is used? Otherwise
  167. * fb_base must be different?
  168. */
  169. if (strcmp(name, "layer_0") == 0) {
  170. dp->planes[0].fb_base =
  171. (uint)map_sysmem(plat->base, plat->size);
  172. debug("%s(): dp->planes[0].fb_base == 0x%x\n", __func__,
  173. (uint)dp->planes[0].fb_base);
  174. nx_display_parse_dp_layer(subnode, &dp->planes[0]);
  175. }
  176. if (strcmp(name, "layer_1") == 0) {
  177. dp->planes[1].fb_base =
  178. (uint)map_sysmem(plat->base, plat->size);
  179. debug("%s(): dp->planes[1].fb_base == 0x%x\n", __func__,
  180. (uint)dp->planes[1].fb_base);
  181. nx_display_parse_dp_layer(subnode, &dp->planes[1]);
  182. }
  183. if (strcmp(name, "layer_2") == 0) {
  184. dp->planes[2].fb_base =
  185. (uint)map_sysmem(plat->base, plat->size);
  186. debug("%s(): dp->planes[2].fb_base == 0x%x\n", __func__,
  187. (uint)dp->planes[2].fb_base);
  188. nx_display_parse_dp_layer(subnode, &dp->planes[2]);
  189. }
  190. }
  191. }
  192. static int nx_display_parse_dp_lvds(ofnode node, struct nx_display_dev *dp)
  193. {
  194. struct dp_lvds_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  195. if (!dev) {
  196. printf("failed to allocate display LVDS object.\n");
  197. return -ENOMEM;
  198. }
  199. dp->device = dev;
  200. dev->lvds_format = ofnode_read_s32_default(node, "format", 0);
  201. dev->pol_inv_hs = ofnode_read_s32_default(node, "pol_inv_hs", 0);
  202. dev->pol_inv_vs = ofnode_read_s32_default(node, "pol_inv_vs", 0);
  203. dev->pol_inv_de = ofnode_read_s32_default(node, "pol_inv_de", 0);
  204. dev->pol_inv_ck = ofnode_read_s32_default(node, "pol_inv_ck", 0);
  205. dev->voltage_level = ofnode_read_s32_default(node, "voltage_level", 0);
  206. if (!dev->voltage_level)
  207. dev->voltage_level = DEF_VOLTAGE_LEVEL;
  208. debug("DP: LVDS -> %s, voltage LV:0x%x\n",
  209. dev->lvds_format == DP_LVDS_FORMAT_VESA ? "VESA" :
  210. dev->lvds_format == DP_LVDS_FORMAT_JEIDA ? "JEIDA" : "LOC",
  211. dev->voltage_level);
  212. debug("pol inv hs:%d, vs:%d, de:%d, ck:%d\n",
  213. dev->pol_inv_hs, dev->pol_inv_vs,
  214. dev->pol_inv_de, dev->pol_inv_ck);
  215. return 0;
  216. }
  217. static int nx_display_parse_dp_rgb(ofnode node, struct nx_display_dev *dp)
  218. {
  219. struct dp_rgb_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  220. if (!dev) {
  221. printf("failed to allocate display RGB LCD object.\n");
  222. return -ENOMEM;
  223. }
  224. dp->device = dev;
  225. dev->lcd_mpu_type = ofnode_read_s32_default(node, "lcd_mpu_type", 0);
  226. debug("DP: RGB -> MPU[%s]\n", dev->lcd_mpu_type ? "O" : "X");
  227. return 0;
  228. }
  229. static int nx_display_parse_dp_mipi(ofnode node, struct nx_display_dev *dp)
  230. {
  231. struct dp_mipi_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  232. if (!dev) {
  233. printf("failed to allocate display MiPi object.\n");
  234. return -ENOMEM;
  235. }
  236. dp->device = dev;
  237. dev->lp_bitrate = ofnode_read_s32_default(node, "lp_bitrate", 0);
  238. dev->hs_bitrate = ofnode_read_s32_default(node, "hs_bitrate", 0);
  239. dev->lpm_trans = 1;
  240. dev->command_mode = 0;
  241. debug("DP: MIPI ->\n");
  242. debug("lp:%dmhz, hs:%dmhz\n", dev->lp_bitrate, dev->hs_bitrate);
  243. return 0;
  244. }
  245. static int nx_display_parse_dp_hdmi(ofnode node, struct nx_display_dev *dp)
  246. {
  247. struct dp_hdmi_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  248. if (!dev) {
  249. printf("failed to allocate display HDMI object.\n");
  250. return -ENOMEM;
  251. }
  252. dp->device = dev;
  253. dev->preset = ofnode_read_s32_default(node, "preset", 0);
  254. debug("DP: HDMI -> %d\n", dev->preset);
  255. return 0;
  256. }
  257. static int nx_display_parse_dp_lcds(ofnode node, const char *type,
  258. struct nx_display_dev *dp)
  259. {
  260. if (strcmp(type, "lvds") == 0) {
  261. dp->dev_type = DP_DEVICE_LVDS;
  262. return nx_display_parse_dp_lvds(node, dp);
  263. } else if (strcmp(type, "rgb") == 0) {
  264. dp->dev_type = DP_DEVICE_RGBLCD;
  265. return nx_display_parse_dp_rgb(node, dp);
  266. } else if (strcmp(type, "mipi") == 0) {
  267. dp->dev_type = DP_DEVICE_MIPI;
  268. return nx_display_parse_dp_mipi(node, dp);
  269. } else if (strcmp(type, "hdmi") == 0) {
  270. dp->dev_type = DP_DEVICE_HDMI;
  271. return nx_display_parse_dp_hdmi(node, dp);
  272. }
  273. printf("%s: node %s unknown display type\n", __func__,
  274. ofnode_get_name(node));
  275. return -EINVAL;
  276. return 0;
  277. }
  278. #define DT_SYNC (1 << 0)
  279. #define DT_CTRL (1 << 1)
  280. #define DT_PLANES (1 << 2)
  281. #define DT_DEVICE (1 << 3)
  282. static int nx_display_parse_dt(struct udevice *dev,
  283. struct nx_display_dev *dp,
  284. struct video_uc_plat *plat)
  285. {
  286. const char *name, *dtype;
  287. int ret = 0;
  288. unsigned int dt_status = 0;
  289. ofnode subnode;
  290. if (!dev)
  291. return -ENODEV;
  292. dp->module = dev_read_s32_default(dev, "module", -1);
  293. if (dp->module == -1)
  294. dp->module = dev_read_s32_default(dev, "index", 0);
  295. dtype = dev_read_string(dev, "lcd-type");
  296. ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
  297. name = ofnode_get_name(subnode);
  298. if (strcmp("dp-sync", name) == 0) {
  299. dt_status |= DT_SYNC;
  300. nx_display_parse_dp_sync(subnode, &dp->sync);
  301. }
  302. if (strcmp("dp-ctrl", name) == 0) {
  303. dt_status |= DT_CTRL;
  304. nx_display_parse_dp_ctrl(subnode, &dp->ctrl);
  305. }
  306. if (strcmp("dp-planes", name) == 0) {
  307. dt_status |= DT_PLANES;
  308. nx_display_parse_dp_planes(subnode, dp, plat);
  309. }
  310. if (strcmp("dp-device", name) == 0) {
  311. dt_status |= DT_DEVICE;
  312. ret = nx_display_parse_dp_lcds(subnode, dtype, dp);
  313. }
  314. }
  315. if (dt_status != (DT_SYNC | DT_CTRL | DT_PLANES | DT_DEVICE)) {
  316. printf("Not enough DT config for display [0x%x]\n", dt_status);
  317. return -ENODEV;
  318. }
  319. return ret;
  320. }
  321. #endif
  322. __weak int nx_display_fixup_dp(struct nx_display_dev *dp)
  323. {
  324. return 0;
  325. }
  326. static struct nx_display_dev *nx_display_setup(void)
  327. {
  328. struct nx_display_dev *dp;
  329. int i, ret;
  330. int node = 0;
  331. struct video_uc_plat *plat = NULL;
  332. struct udevice *dev;
  333. /* call driver probe */
  334. debug("DT: uclass device call...\n");
  335. ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
  336. if (ret) {
  337. debug("%s(): uclass_get_device(UCLASS_VIDEO, 0, &dev) != 0 --> return NULL\n",
  338. __func__);
  339. return NULL;
  340. }
  341. plat = dev_get_uclass_plat(dev);
  342. if (!dev) {
  343. debug("%s(): dev_get_uclass_plat(dev) == NULL --> return NULL\n",
  344. __func__);
  345. return NULL;
  346. }
  347. dp = dev_get_priv(dev);
  348. if (!dp) {
  349. debug("%s(): dev_get_priv(dev) == NULL --> return NULL\n",
  350. __func__);
  351. return NULL;
  352. }
  353. node = dev_ofnode(dev).of_offset;
  354. if (CONFIG_IS_ENABLED(OF_CONTROL)) {
  355. ret = nx_display_parse_dt(dev, dp, plat);
  356. if (ret)
  357. goto err_setup;
  358. }
  359. nx_display_fixup_dp(dp);
  360. for (i = 0; dp->top.plane_num > i; i++) {
  361. dp->planes[i].layer = i;
  362. if (dp->planes[i].enable && !dp->fb_plane) {
  363. dp->fb_plane = &dp->planes[i];
  364. dp->fb_addr = dp->fb_plane->fb_base;
  365. dp->depth = dp->fb_plane->pixel_byte;
  366. }
  367. }
  368. switch (dp->dev_type) {
  369. #ifdef CONFIG_VIDEO_NX_RGB
  370. case DP_DEVICE_RGBLCD:
  371. nx_rgb_display(dp->module,
  372. &dp->sync, &dp->ctrl, &dp->top,
  373. dp->planes, (struct dp_rgb_dev *)dp->device);
  374. break;
  375. #endif
  376. #ifdef CONFIG_VIDEO_NX_LVDS
  377. case DP_DEVICE_LVDS:
  378. nx_lvds_display(dp->module,
  379. &dp->sync, &dp->ctrl, &dp->top,
  380. dp->planes, (struct dp_lvds_dev *)dp->device);
  381. break;
  382. #endif
  383. #ifdef CONFIG_VIDEO_NX_MIPI
  384. case DP_DEVICE_MIPI:
  385. nx_mipi_display(dp->module,
  386. &dp->sync, &dp->ctrl, &dp->top,
  387. dp->planes, (struct dp_mipi_dev *)dp->device);
  388. break;
  389. #endif
  390. #ifdef CONFIG_VIDEO_NX_HDMI
  391. case DP_DEVICE_HDMI:
  392. nx_hdmi_display(dp->module,
  393. &dp->sync, &dp->ctrl, &dp->top,
  394. dp->planes, (struct dp_hdmi_dev *)dp->device);
  395. break;
  396. #endif
  397. default:
  398. printf("fail : not support lcd type %d !!!\n", dp->dev_type);
  399. goto err_setup;
  400. };
  401. printf("LCD: [%s] dp.%d.%d %dx%d %dbpp FB:0x%08x\n",
  402. dp_dev_str[dp->dev_type], dp->module, dp->fb_plane->layer,
  403. dp->fb_plane->width, dp->fb_plane->height, dp->depth * 8,
  404. dp->fb_addr);
  405. return dp;
  406. err_setup:
  407. kfree(dp);
  408. return NULL;
  409. }
  410. #if defined CONFIG_LCD
  411. /* default lcd */
  412. struct vidinfo panel_info = {
  413. .vl_col = 320, .vl_row = 240, .vl_bpix = 32,
  414. };
  415. void lcd_ctrl_init(void *lcdbase)
  416. {
  417. vidinfo_t *pi = &panel_info;
  418. struct nx_display_dev *dp;
  419. int bpix;
  420. dp = nx_display_setup();
  421. if (!dp)
  422. return NULL;
  423. switch (dp->depth) {
  424. case 2:
  425. bpix = LCD_COLOR16;
  426. break;
  427. case 3:
  428. case 4:
  429. bpix = LCD_COLOR32;
  430. break;
  431. default:
  432. printf("fail : not support LCD bit per pixel %d\n",
  433. dp->depth * 8);
  434. return NULL;
  435. }
  436. dp->panel_info = pi;
  437. /* set resolution with config */
  438. pi->vl_bpix = bpix;
  439. pi->vl_col = dp->fb_plane->width;
  440. pi->vl_row = dp->fb_plane->height;
  441. pi->priv = dp;
  442. gd->fb_base = dp->fb_addr;
  443. }
  444. void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  445. {
  446. }
  447. __weak void lcd_enable(void)
  448. {
  449. }
  450. #endif
  451. static int nx_display_probe(struct udevice *dev)
  452. {
  453. struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
  454. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  455. struct nx_display_plat *plat = dev_get_plat(dev);
  456. static GraphicDevice *graphic_device;
  457. char addr[64];
  458. debug("%s()\n", __func__);
  459. if (!dev)
  460. return -EINVAL;
  461. if (!uc_plat) {
  462. debug("%s(): video_uc_plat *plat == NULL --> return -EINVAL\n",
  463. __func__);
  464. return -EINVAL;
  465. }
  466. if (!uc_priv) {
  467. debug("%s(): video_priv *uc_priv == NULL --> return -EINVAL\n",
  468. __func__);
  469. return -EINVAL;
  470. }
  471. if (!plat) {
  472. debug("%s(): nx_display_plat *plat == NULL --> return -EINVAL\n",
  473. __func__);
  474. return -EINVAL;
  475. }
  476. struct nx_display_dev *dp;
  477. unsigned int pp_index = 0;
  478. dp = nx_display_setup();
  479. if (!dp) {
  480. debug("%s(): nx_display_setup() == 0 --> return -EINVAL\n",
  481. __func__);
  482. return -EINVAL;
  483. }
  484. switch (dp->depth) {
  485. case 2:
  486. pp_index = GDF_16BIT_565RGB;
  487. uc_priv->bpix = VIDEO_BPP16;
  488. break;
  489. case 3:
  490. /* There is no VIDEO_BPP24 because these values are of
  491. * type video_log2_bpp
  492. */
  493. case 4:
  494. pp_index = GDF_32BIT_X888RGB;
  495. uc_priv->bpix = VIDEO_BPP32;
  496. break;
  497. default:
  498. printf("fail : not support LCD bit per pixel %d\n",
  499. dp->depth * 8);
  500. return -EINVAL;
  501. }
  502. uc_priv->xsize = dp->fb_plane->width;
  503. uc_priv->ysize = dp->fb_plane->height;
  504. uc_priv->rot = 0;
  505. graphic_device = &dp->graphic_device;
  506. graphic_device->frameAdrs = dp->fb_addr;
  507. graphic_device->gdfIndex = pp_index;
  508. graphic_device->gdfBytesPP = dp->depth;
  509. graphic_device->winSizeX = dp->fb_plane->width;
  510. graphic_device->winSizeY = dp->fb_plane->height;
  511. graphic_device->plnSizeX =
  512. graphic_device->winSizeX * graphic_device->gdfBytesPP;
  513. /*
  514. * set environment variable "fb_addr" (frame buffer address), required
  515. * for splash image. Because drv_video_init() in common/stdio.c is only
  516. * called when CONFIG_VIDEO is set (and not if CONFIG_DM_VIDEO is set).
  517. */
  518. sprintf(addr, "0x%x", dp->fb_addr);
  519. debug("%s(): env_set(\"fb_addr\", %s) ...\n", __func__, addr);
  520. env_set("fb_addr", addr);
  521. return 0;
  522. }
  523. static int nx_display_bind(struct udevice *dev)
  524. {
  525. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  526. debug("%s()\n", __func__);
  527. /* Datasheet S5p4418:
  528. * Resolution up to 2048 x 1280, up to 12 Bit per color (HDMI)
  529. * Actual (max.) size is 0x1000000 because in U-Boot nanopi2-2016.01
  530. * "#define CONFIG_FB_ADDR 0x77000000" and next address is
  531. * "#define BMP_LOAD_ADDR 0x78000000"
  532. */
  533. plat->size = 0x1000000;
  534. return 0;
  535. }
  536. static const struct udevice_id nx_display_ids[] = {
  537. {.compatible = "nexell,nexell-display", },
  538. {}
  539. };
  540. U_BOOT_DRIVER(nexell_display) = {
  541. .name = "nexell-display",
  542. .id = UCLASS_VIDEO,
  543. .of_match = nx_display_ids,
  544. .plat_auto = sizeof(struct nx_display_plat),
  545. .bind = nx_display_bind,
  546. .probe = nx_display_probe,
  547. .priv_auto = sizeof(struct nx_display_dev),
  548. };