mtu3_core.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * mtu3_core.c - hardware access layer and gadget init/exit of
  4. * MediaTek usb3 Dual-Role Controller Driver
  5. *
  6. * Copyright (C) 2016 MediaTek Inc.
  7. *
  8. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  9. */
  10. #include <linux/log2.h>
  11. #include <linux/bitmap.h>
  12. #include "mtu3.h"
  13. #include "mtu3_dr.h"
  14. static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
  15. {
  16. struct mtu3_fifo_info *fifo = mep->fifo;
  17. struct mtu3 *mtu = mep->mtu;
  18. u32 fz_bit;
  19. mep->fifo_seg_size = mtu->is_u3_ip ? USB_SS_MAXP : USB_HS_MAXP;
  20. fz_bit = find_first_zero_bit(fifo->bitmap, fifo->limit);
  21. if (fz_bit >= fifo->limit)
  22. return -EOVERFLOW;
  23. mep->fifo_size = mep->fifo_seg_size * (mep->slot + 1);
  24. mep->fifo_addr = fifo->base + mep->fifo_size * fz_bit;
  25. generic_set_bit(fz_bit, fifo->bitmap);
  26. dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, bit: %d\n",
  27. __func__, mep->fifo_seg_size, mep->fifo_size, fz_bit);
  28. return mep->fifo_addr;
  29. }
  30. static void ep_fifo_free(struct mtu3_ep *mep)
  31. {
  32. struct mtu3_fifo_info *fifo = mep->fifo;
  33. u32 addr = mep->fifo_addr;
  34. u32 bit;
  35. if (unlikely(addr < fifo->base))
  36. return;
  37. bit = (addr - fifo->base) / mep->fifo_size;
  38. generic_clear_bit(bit, fifo->bitmap);
  39. mep->fifo_size = 0;
  40. mep->fifo_seg_size = 0;
  41. dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, bit: %d\n",
  42. __func__, mep->fifo_seg_size, mep->fifo_size, bit);
  43. }
  44. /* enable/disable U3D SS function */
  45. static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
  46. {
  47. /* If usb3_en==0, LTSSM will go to SS.Disable state */
  48. if (enable)
  49. mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
  50. else
  51. mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
  52. dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
  53. }
  54. /* set/clear U3D HS device soft connect */
  55. static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
  56. {
  57. if (enable) {
  58. mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
  59. SOFT_CONN | SUSPENDM_ENABLE);
  60. } else {
  61. mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
  62. SOFT_CONN | SUSPENDM_ENABLE);
  63. }
  64. dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
  65. }
  66. /* only port0 of U2/U3 supports device mode */
  67. static int mtu3_device_enable(struct mtu3 *mtu)
  68. {
  69. void __iomem *ibase = mtu->ippc_base;
  70. u32 check_clk = 0;
  71. mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
  72. if (mtu->is_u3_ip) {
  73. check_clk = SSUSB_U3_MAC_RST_B_STS;
  74. mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
  75. (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
  76. SSUSB_U3_PORT_HOST_SEL));
  77. }
  78. mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
  79. (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
  80. SSUSB_U2_PORT_HOST_SEL));
  81. return ssusb_check_clocks(mtu->ssusb, check_clk);
  82. }
  83. static void mtu3_device_disable(struct mtu3 *mtu)
  84. {
  85. void __iomem *ibase = mtu->ippc_base;
  86. if (mtu->is_u3_ip)
  87. mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
  88. (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
  89. mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
  90. SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
  91. mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
  92. }
  93. /* reset U3D's device module. */
  94. static void mtu3_device_reset(struct mtu3 *mtu)
  95. {
  96. void __iomem *ibase = mtu->ippc_base;
  97. mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
  98. udelay(1);
  99. mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
  100. }
  101. static void mtu3_intr_status_clear(struct mtu3 *mtu)
  102. {
  103. void __iomem *mbase = mtu->mac_base;
  104. /* Clear EP0 and Tx/Rx EPn interrupts status */
  105. mtu3_writel(mbase, U3D_EPISR, ~0x0);
  106. /* Clear U2 USB common interrupts status */
  107. mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
  108. /* Clear U3 LTSSM interrupts status */
  109. mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
  110. /* Clear speed change interrupt status */
  111. mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
  112. /* Clear QMU interrupt status */
  113. mtu3_writel(mbase, U3D_QISAR0, ~0x0);
  114. }
  115. /* disable all interrupts */
  116. static void mtu3_intr_disable(struct mtu3 *mtu)
  117. {
  118. /* Disable level 1 interrupts */
  119. mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0);
  120. /* Disable endpoint interrupts */
  121. mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0);
  122. mtu3_intr_status_clear(mtu);
  123. }
  124. /* enable system global interrupt */
  125. static void mtu3_intr_enable(struct mtu3 *mtu)
  126. {
  127. void __iomem *mbase = mtu->mac_base;
  128. u32 value;
  129. /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
  130. value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
  131. mtu3_writel(mbase, U3D_LV1IESR, value);
  132. /* Enable U2 common USB interrupts */
  133. value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
  134. mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
  135. if (mtu->is_u3_ip) {
  136. /* Enable U3 LTSSM interrupts */
  137. value = HOT_RST_INTR | WARM_RST_INTR |
  138. ENTER_U3_INTR | EXIT_U3_INTR;
  139. mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
  140. }
  141. /* Enable QMU interrupts. */
  142. value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
  143. RXQ_LENERR_INT | RXQ_ZLPERR_INT;
  144. mtu3_writel(mbase, U3D_QIESR1, value);
  145. /* Enable speed change interrupt */
  146. mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
  147. }
  148. void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed)
  149. {
  150. void __iomem *mbase = mtu->mac_base;
  151. if (speed > mtu->max_speed)
  152. speed = mtu->max_speed;
  153. switch (speed) {
  154. case USB_SPEED_FULL:
  155. /* disable U3 SS function */
  156. mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
  157. /* disable HS function */
  158. mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
  159. break;
  160. case USB_SPEED_HIGH:
  161. mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
  162. /* HS/FS detected by HW */
  163. mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
  164. break;
  165. case USB_SPEED_SUPER:
  166. mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
  167. SSUSB_U3_PORT_SSP_SPEED);
  168. break;
  169. case USB_SPEED_SUPER_PLUS:
  170. mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
  171. SSUSB_U3_PORT_SSP_SPEED);
  172. break;
  173. default:
  174. dev_err(mtu->dev, "invalid speed: %d\n", speed);
  175. return;
  176. }
  177. mtu->speed = speed;
  178. dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(mtu->speed));
  179. }
  180. /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
  181. static void mtu3_ep_reset(struct mtu3_ep *mep)
  182. {
  183. struct mtu3 *mtu = mep->mtu;
  184. u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
  185. mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
  186. mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
  187. }
  188. /* set/clear the stall and toggle bits for non-ep0 */
  189. void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
  190. {
  191. struct mtu3 *mtu = mep->mtu;
  192. void __iomem *mbase = mtu->mac_base;
  193. u8 epnum = mep->epnum;
  194. u32 csr;
  195. if (mep->is_in) { /* TX */
  196. csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
  197. if (set)
  198. csr |= TX_SENDSTALL;
  199. else
  200. csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
  201. mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
  202. } else { /* RX */
  203. csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
  204. if (set)
  205. csr |= RX_SENDSTALL;
  206. else
  207. csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
  208. mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
  209. }
  210. if (!set) {
  211. mtu3_ep_reset(mep);
  212. mep->flags &= ~MTU3_EP_STALL;
  213. } else {
  214. mep->flags |= MTU3_EP_STALL;
  215. }
  216. dev_dbg(mtu->dev, "%s: %s\n", mep->name,
  217. set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
  218. }
  219. void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
  220. {
  221. if (mtu->is_u3_ip && mtu->speed >= USB_SPEED_SUPER)
  222. mtu3_ss_func_set(mtu, is_on);
  223. else
  224. mtu3_hs_softconn_set(mtu, is_on);
  225. dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
  226. usb_speed_string(mtu->speed), is_on ? "+" : "-");
  227. }
  228. void mtu3_start(struct mtu3 *mtu)
  229. {
  230. void __iomem *mbase = mtu->mac_base;
  231. dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
  232. mtu3_readl(mbase, U3D_DEVICE_CONTROL));
  233. /* Initialize the default interrupts */
  234. mtu3_intr_enable(mtu);
  235. mtu->is_active = 1;
  236. if (mtu->softconnect)
  237. mtu3_dev_on_off(mtu, 1);
  238. }
  239. void mtu3_stop(struct mtu3 *mtu)
  240. {
  241. dev_dbg(mtu->dev, "%s\n", __func__);
  242. mtu3_intr_disable(mtu);
  243. if (mtu->softconnect)
  244. mtu3_dev_on_off(mtu, 0);
  245. mtu->is_active = 0;
  246. }
  247. /* for non-ep0 */
  248. int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
  249. int interval, int burst, int mult)
  250. {
  251. void __iomem *mbase = mtu->mac_base;
  252. bool gen2cp = mtu->gen2cp;
  253. int epnum = mep->epnum;
  254. u32 csr0, csr1, csr2;
  255. int fifo_sgsz, fifo_addr;
  256. int num_pkts;
  257. fifo_addr = ep_fifo_alloc(mep, mep->maxp);
  258. if (fifo_addr < 0) {
  259. dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
  260. return -ENOMEM;
  261. }
  262. fifo_sgsz = ilog2(mep->fifo_seg_size);
  263. dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
  264. mep->fifo_seg_size, mep->fifo_size);
  265. if (mep->is_in) {
  266. csr0 = TX_TXMAXPKTSZ(mep->maxp);
  267. csr0 |= TX_DMAREQEN;
  268. num_pkts = (burst + 1) * (mult + 1) - 1;
  269. csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
  270. csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
  271. csr2 = TX_FIFOADDR(fifo_addr >> 4);
  272. csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
  273. switch (mep->type) {
  274. case USB_ENDPOINT_XFER_BULK:
  275. csr1 |= TX_TYPE(TYPE_BULK);
  276. break;
  277. case USB_ENDPOINT_XFER_ISOC:
  278. csr1 |= TX_TYPE(TYPE_ISO);
  279. csr2 |= TX_BINTERVAL(interval);
  280. break;
  281. case USB_ENDPOINT_XFER_INT:
  282. csr1 |= TX_TYPE(TYPE_INT);
  283. csr2 |= TX_BINTERVAL(interval);
  284. break;
  285. }
  286. /* Enable QMU Done interrupt */
  287. mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
  288. mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
  289. mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
  290. mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
  291. dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
  292. epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
  293. mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
  294. mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
  295. } else {
  296. csr0 = RX_RXMAXPKTSZ(mep->maxp);
  297. csr0 |= RX_DMAREQEN;
  298. num_pkts = (burst + 1) * (mult + 1) - 1;
  299. csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
  300. csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
  301. csr2 = RX_FIFOADDR(fifo_addr >> 4);
  302. csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
  303. switch (mep->type) {
  304. case USB_ENDPOINT_XFER_BULK:
  305. csr1 |= RX_TYPE(TYPE_BULK);
  306. break;
  307. case USB_ENDPOINT_XFER_ISOC:
  308. csr1 |= RX_TYPE(TYPE_ISO);
  309. csr2 |= RX_BINTERVAL(interval);
  310. break;
  311. case USB_ENDPOINT_XFER_INT:
  312. csr1 |= RX_TYPE(TYPE_INT);
  313. csr2 |= RX_BINTERVAL(interval);
  314. break;
  315. }
  316. /*Enable QMU Done interrupt */
  317. mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
  318. mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
  319. mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
  320. mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
  321. dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
  322. epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
  323. mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
  324. mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
  325. }
  326. dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
  327. dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
  328. __func__, mep->name, mep->fifo_addr, mep->fifo_size,
  329. fifo_sgsz, mep->fifo_seg_size);
  330. return 0;
  331. }
  332. /* for non-ep0 */
  333. void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
  334. {
  335. void __iomem *mbase = mtu->mac_base;
  336. int epnum = mep->epnum;
  337. if (mep->is_in) {
  338. mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
  339. mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
  340. mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
  341. mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
  342. } else {
  343. mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
  344. mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
  345. mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
  346. mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
  347. }
  348. mtu3_ep_reset(mep);
  349. ep_fifo_free(mep);
  350. dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
  351. }
  352. /*
  353. * Two scenarios:
  354. * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
  355. * are separated;
  356. * 2. when supports only HS, the fifo is shared for all EPs, and
  357. * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
  358. * the total fifo size of non-ep0, and ep0's is fixed to 64B,
  359. * so the total fifo size is 64B + @EPNTXFFSZ;
  360. * Due to the first 64B should be reserved for EP0, non-ep0's fifo
  361. * starts from offset 64 and are divided into two equal parts for
  362. * TX or RX EPs for simplification.
  363. */
  364. static void get_ep_fifo_config(struct mtu3 *mtu)
  365. {
  366. struct mtu3_fifo_info *tx_fifo;
  367. struct mtu3_fifo_info *rx_fifo;
  368. u32 fifosize;
  369. if (mtu->is_u3_ip) {
  370. fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
  371. tx_fifo = &mtu->tx_fifo;
  372. tx_fifo->base = 0;
  373. tx_fifo->limit = fifosize / MTU3_U3IP_EP_FIFO_UNIT;
  374. bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
  375. fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
  376. rx_fifo = &mtu->rx_fifo;
  377. rx_fifo->base = 0;
  378. rx_fifo->limit = fifosize / MTU3_U3IP_EP_FIFO_UNIT;
  379. bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
  380. mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
  381. } else {
  382. fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
  383. tx_fifo = &mtu->tx_fifo;
  384. tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
  385. tx_fifo->limit = (fifosize / MTU3_U2IP_EP_FIFO_UNIT) >> 1;
  386. bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
  387. rx_fifo = &mtu->rx_fifo;
  388. rx_fifo->base = tx_fifo->base +
  389. tx_fifo->limit * MTU3_U2IP_EP_FIFO_UNIT;
  390. rx_fifo->limit = tx_fifo->limit;
  391. bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
  392. mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
  393. }
  394. dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
  395. __func__, tx_fifo->base, tx_fifo->limit,
  396. rx_fifo->base, rx_fifo->limit);
  397. }
  398. void mtu3_ep0_setup(struct mtu3 *mtu)
  399. {
  400. u32 maxpacket = mtu->g.ep0->maxpacket;
  401. u32 csr;
  402. dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
  403. csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
  404. csr &= ~EP0_MAXPKTSZ_MSK;
  405. csr |= EP0_MAXPKTSZ(maxpacket);
  406. csr &= EP0_W1C_BITS;
  407. mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
  408. /* Enable EP0 interrupt */
  409. mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
  410. }
  411. static int mtu3_mem_alloc(struct mtu3 *mtu)
  412. {
  413. void __iomem *mbase = mtu->mac_base;
  414. struct mtu3_ep *ep_array;
  415. int in_ep_num, out_ep_num;
  416. u32 cap_epinfo;
  417. int i;
  418. cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
  419. in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
  420. out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
  421. dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
  422. mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
  423. mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
  424. /* one for ep0, another is reserved */
  425. mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
  426. ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
  427. if (!ep_array)
  428. return -ENOMEM;
  429. mtu->ep_array = ep_array;
  430. mtu->in_eps = ep_array;
  431. mtu->out_eps = &ep_array[mtu->num_eps];
  432. /* ep0 uses in_eps[0], out_eps[0] is reserved */
  433. mtu->ep0 = mtu->in_eps;
  434. mtu->ep0->mtu = mtu;
  435. mtu->ep0->epnum = 0;
  436. for (i = 1; i < mtu->num_eps; i++) {
  437. struct mtu3_ep *mep = mtu->in_eps + i;
  438. mep->fifo = &mtu->tx_fifo;
  439. mep = mtu->out_eps + i;
  440. mep->fifo = &mtu->rx_fifo;
  441. }
  442. get_ep_fifo_config(mtu);
  443. mtu3_qmu_init(mtu);
  444. return 0;
  445. }
  446. static void mtu3_mem_free(struct mtu3 *mtu)
  447. {
  448. mtu3_qmu_exit(mtu);
  449. kfree(mtu->ep_array);
  450. }
  451. static void mtu3_regs_init(struct mtu3 *mtu)
  452. {
  453. void __iomem *mbase = mtu->mac_base;
  454. /* be sure interrupts are disabled before registration of ISR */
  455. mtu3_intr_disable(mtu);
  456. if (mtu->is_u3_ip) {
  457. /* disable LGO_U1/U2 by default */
  458. mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
  459. SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
  460. /* enable accept LGO_U1/U2 link command from host */
  461. mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
  462. SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
  463. /* device responses to u3_exit from host automatically */
  464. mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
  465. /* automatically build U2 link when U3 detect fail */
  466. mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
  467. /* auto clear SOFT_CONN when clear USB3_EN if work as HS */
  468. mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
  469. }
  470. /* delay about 0.1us from detecting reset to send chirp-K */
  471. mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
  472. /* U2/U3 detected by HW */
  473. mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
  474. /* enable automatical HWRW from L1 */
  475. mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
  476. mtu3_set_speed(mtu, mtu->max_speed);
  477. ssusb_set_force_mode(mtu->ssusb, MTU3_DR_FORCE_DEVICE);
  478. if (mtu->force_vbus)
  479. mtu3_setbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
  480. else /* vbus detected by HW */
  481. mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
  482. }
  483. static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
  484. {
  485. void __iomem *mbase = mtu->mac_base;
  486. enum usb_device_speed udev_speed;
  487. u32 maxpkt = 64;
  488. u32 link;
  489. u32 speed;
  490. link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
  491. link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
  492. mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
  493. dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
  494. if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
  495. return IRQ_NONE;
  496. speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
  497. switch (speed) {
  498. case MTU3_SPEED_FULL:
  499. udev_speed = USB_SPEED_FULL;
  500. /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
  501. mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
  502. | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
  503. mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
  504. LPM_BESL_STALL | LPM_BESLD_STALL);
  505. break;
  506. case MTU3_SPEED_HIGH:
  507. udev_speed = USB_SPEED_HIGH;
  508. /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
  509. mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
  510. | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
  511. mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
  512. LPM_BESL_STALL | LPM_BESLD_STALL);
  513. break;
  514. case MTU3_SPEED_SUPER:
  515. udev_speed = USB_SPEED_SUPER;
  516. maxpkt = 512;
  517. break;
  518. case MTU3_SPEED_SUPER_PLUS:
  519. udev_speed = USB_SPEED_SUPER_PLUS;
  520. maxpkt = 512;
  521. break;
  522. default:
  523. udev_speed = USB_SPEED_UNKNOWN;
  524. break;
  525. }
  526. dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
  527. mtu->g.speed = udev_speed;
  528. mtu->g.ep0->maxpacket = maxpkt;
  529. mtu->ep0_state = MU3D_EP0_STATE_SETUP;
  530. if (udev_speed == USB_SPEED_UNKNOWN)
  531. mtu3_gadget_disconnect(mtu);
  532. else
  533. mtu3_ep0_setup(mtu);
  534. return IRQ_HANDLED;
  535. }
  536. static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
  537. {
  538. void __iomem *mbase = mtu->mac_base;
  539. u32 ltssm;
  540. ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
  541. ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
  542. mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
  543. dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
  544. if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
  545. mtu3_gadget_reset(mtu);
  546. if (ltssm & VBUS_FALL_INTR) {
  547. mtu3_ss_func_set(mtu, false);
  548. mtu3_gadget_reset(mtu);
  549. }
  550. if (ltssm & VBUS_RISE_INTR)
  551. mtu3_ss_func_set(mtu, true);
  552. if (ltssm & EXIT_U3_INTR)
  553. mtu3_gadget_resume(mtu);
  554. if (ltssm & ENTER_U3_INTR)
  555. mtu3_gadget_suspend(mtu);
  556. return IRQ_HANDLED;
  557. }
  558. static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
  559. {
  560. void __iomem *mbase = mtu->mac_base;
  561. u32 u2comm;
  562. u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
  563. u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
  564. mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
  565. dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
  566. if (u2comm & SUSPEND_INTR)
  567. mtu3_gadget_suspend(mtu);
  568. if (u2comm & RESUME_INTR)
  569. mtu3_gadget_resume(mtu);
  570. if (u2comm & RESET_INTR)
  571. mtu3_gadget_reset(mtu);
  572. return IRQ_HANDLED;
  573. }
  574. irqreturn_t mtu3_irq(int irq, void *data)
  575. {
  576. struct mtu3 *mtu = (struct mtu3 *)data;
  577. unsigned long flags;
  578. u32 level1;
  579. spin_lock_irqsave(&mtu->lock, flags);
  580. /* U3D_LV1ISR is RU */
  581. level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
  582. level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
  583. if (level1 & EP_CTRL_INTR)
  584. mtu3_link_isr(mtu);
  585. if (level1 & MAC2_INTR)
  586. mtu3_u2_common_isr(mtu);
  587. if (level1 & MAC3_INTR)
  588. mtu3_u3_ltssm_isr(mtu);
  589. if (level1 & BMU_INTR)
  590. mtu3_ep0_isr(mtu);
  591. if (level1 & QMU_INTR)
  592. mtu3_qmu_isr(mtu);
  593. spin_unlock_irqrestore(&mtu->lock, flags);
  594. return IRQ_HANDLED;
  595. }
  596. static void mtu3_check_params(struct mtu3 *mtu)
  597. {
  598. /* check the max_speed parameter */
  599. switch (mtu->max_speed) {
  600. case USB_SPEED_FULL:
  601. case USB_SPEED_HIGH:
  602. case USB_SPEED_SUPER:
  603. case USB_SPEED_SUPER_PLUS:
  604. break;
  605. default:
  606. dev_err(mtu->dev, "invalid max_speed: %d\n", mtu->max_speed);
  607. /* fall through */
  608. case USB_SPEED_UNKNOWN:
  609. /* default as SS */
  610. mtu->max_speed = USB_SPEED_SUPER;
  611. break;
  612. }
  613. if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
  614. mtu->max_speed = USB_SPEED_HIGH;
  615. mtu->speed = mtu->max_speed;
  616. dev_info(mtu->dev, "max_speed: %s\n", usb_speed_string(mtu->speed));
  617. }
  618. static int mtu3_hw_init(struct mtu3 *mtu)
  619. {
  620. u32 value;
  621. int ret;
  622. value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
  623. mtu->hw_version = IP_TRUNK_VERS(value);
  624. mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
  625. value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
  626. mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
  627. dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
  628. mtu->is_u3_ip ? "U3" : "U2");
  629. mtu3_check_params(mtu);
  630. mtu3_device_reset(mtu);
  631. ret = mtu3_device_enable(mtu);
  632. if (ret) {
  633. dev_err(mtu->dev, "device enable failed %d\n", ret);
  634. return ret;
  635. }
  636. ret = mtu3_mem_alloc(mtu);
  637. if (ret)
  638. return ret;
  639. mtu3_regs_init(mtu);
  640. return 0;
  641. }
  642. static void mtu3_hw_exit(struct mtu3 *mtu)
  643. {
  644. mtu3_device_disable(mtu);
  645. mtu3_mem_free(mtu);
  646. }
  647. int ssusb_gadget_init(struct ssusb_mtk *ssusb)
  648. {
  649. struct mtu3 *mtu = ssusb->u3d;
  650. struct udevice *dev = mtu->dev;
  651. int ret = -ENOMEM;
  652. spin_lock_init(&mtu->lock);
  653. mtu->ippc_base = ssusb->ippc_base;
  654. mtu->mac_base = ssusb->mac_base;
  655. mtu->ssusb = ssusb;
  656. mtu->max_speed = usb_get_maximum_speed(dev_ofnode(dev));
  657. mtu->force_vbus = dev_read_bool(dev, "mediatek,force-vbus");
  658. ret = mtu3_hw_init(mtu);
  659. if (ret) {
  660. dev_err(dev, "mtu3 hw init failed:%d\n", ret);
  661. return ret;
  662. }
  663. ret = mtu3_gadget_setup(mtu);
  664. if (ret) {
  665. dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
  666. goto gadget_err;
  667. }
  668. dev_info(dev, "%s() done...\n", __func__);
  669. return 0;
  670. gadget_err:
  671. mtu3_hw_exit(mtu);
  672. ssusb->u3d = NULL;
  673. dev_err(dev, "%s() fail...\n", __func__);
  674. return ret;
  675. }
  676. void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
  677. {
  678. struct mtu3 *mtu = ssusb->u3d;
  679. mtu3_gadget_cleanup(mtu);
  680. mtu3_hw_exit(mtu);
  681. }