xhci-dwc3.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. *
  5. * DWC3 controller driver
  6. *
  7. * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <generic-phy.h>
  12. #include <log.h>
  13. #include <usb.h>
  14. #include <dwc3-uboot.h>
  15. #include <linux/delay.h>
  16. #include <usb/xhci.h>
  17. #include <asm/io.h>
  18. #include <linux/usb/dwc3.h>
  19. #include <linux/usb/otg.h>
  20. struct xhci_dwc3_plat {
  21. struct phy_bulk phys;
  22. };
  23. void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
  24. {
  25. clrsetbits_le32(&dwc3_reg->g_ctl,
  26. DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
  27. DWC3_GCTL_PRTCAPDIR(mode));
  28. }
  29. static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
  30. {
  31. /* Assert USB3 PHY reset */
  32. setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  33. /* Assert USB2 PHY reset */
  34. setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  35. mdelay(100);
  36. /* Clear USB3 PHY reset */
  37. clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  38. /* Clear USB2 PHY reset */
  39. clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  40. }
  41. void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
  42. {
  43. /* Before Resetting PHY, put Core in Reset */
  44. setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  45. /* reset USB3 phy - if required */
  46. dwc3_phy_reset(dwc3_reg);
  47. mdelay(100);
  48. /* After PHYs are stable we can take Core out of reset state */
  49. clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  50. }
  51. int dwc3_core_init(struct dwc3 *dwc3_reg)
  52. {
  53. u32 reg;
  54. u32 revision;
  55. unsigned int dwc3_hwparams1;
  56. revision = readl(&dwc3_reg->g_snpsid);
  57. /* This should read as U3 followed by revision number */
  58. if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
  59. puts("this is not a DesignWare USB3 DRD Core\n");
  60. return -1;
  61. }
  62. dwc3_core_soft_reset(dwc3_reg);
  63. dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
  64. reg = readl(&dwc3_reg->g_ctl);
  65. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  66. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  67. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
  68. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  69. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  70. break;
  71. default:
  72. debug("No power optimization available\n");
  73. }
  74. /*
  75. * WORKAROUND: DWC3 revisions <1.90a have a bug
  76. * where the device can fail to connect at SuperSpeed
  77. * and falls back to high-speed mode which causes
  78. * the device to enter a Connect/Disconnect loop
  79. */
  80. if ((revision & DWC3_REVISION_MASK) < 0x190a)
  81. reg |= DWC3_GCTL_U2RSTECN;
  82. writel(reg, &dwc3_reg->g_ctl);
  83. return 0;
  84. }
  85. void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
  86. {
  87. setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
  88. GFLADJ_30MHZ(val));
  89. }
  90. #if CONFIG_IS_ENABLED(DM_USB)
  91. static int xhci_dwc3_probe(struct udevice *dev)
  92. {
  93. struct xhci_hcor *hcor;
  94. struct xhci_hccr *hccr;
  95. struct dwc3 *dwc3_reg;
  96. enum usb_dr_mode dr_mode;
  97. struct xhci_dwc3_plat *plat = dev_get_plat(dev);
  98. const char *phy;
  99. u32 reg;
  100. int ret;
  101. hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev));
  102. hcor = (struct xhci_hcor *)((uintptr_t)hccr +
  103. HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
  104. ret = dwc3_setup_phy(dev, &plat->phys);
  105. if (ret && (ret != -ENOTSUPP))
  106. return ret;
  107. dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
  108. dwc3_core_init(dwc3_reg);
  109. /* Set dwc3 usb2 phy config */
  110. reg = readl(&dwc3_reg->g_usb2phycfg[0]);
  111. phy = dev_read_string(dev, "phy_type");
  112. if (phy && strcmp(phy, "utmi_wide") == 0) {
  113. reg |= DWC3_GUSB2PHYCFG_PHYIF;
  114. reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
  115. reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
  116. }
  117. if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
  118. reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  119. if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
  120. reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
  121. if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
  122. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  123. writel(reg, &dwc3_reg->g_usb2phycfg[0]);
  124. dr_mode = usb_get_dr_mode(dev_ofnode(dev));
  125. if (dr_mode == USB_DR_MODE_UNKNOWN)
  126. /* by default set dual role mode to HOST */
  127. dr_mode = USB_DR_MODE_HOST;
  128. dwc3_set_mode(dwc3_reg, dr_mode);
  129. return xhci_register(dev, hccr, hcor);
  130. }
  131. static int xhci_dwc3_remove(struct udevice *dev)
  132. {
  133. struct xhci_dwc3_plat *plat = dev_get_plat(dev);
  134. dwc3_shutdown_phy(dev, &plat->phys);
  135. return xhci_deregister(dev);
  136. }
  137. static const struct udevice_id xhci_dwc3_ids[] = {
  138. { .compatible = "snps,dwc3" },
  139. { }
  140. };
  141. U_BOOT_DRIVER(xhci_dwc3) = {
  142. .name = "xhci-dwc3",
  143. .id = UCLASS_USB,
  144. .of_match = xhci_dwc3_ids,
  145. .probe = xhci_dwc3_probe,
  146. .remove = xhci_dwc3_remove,
  147. .ops = &xhci_usb_ops,
  148. .priv_auto = sizeof(struct xhci_ctrl),
  149. .plat_auto = sizeof(struct xhci_dwc3_plat),
  150. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  151. };
  152. #endif