dwc2_udc_otg.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/usb/gadget/dwc2_udc_otg.c
  4. * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
  5. *
  6. * Copyright (C) 2008 for Samsung Electronics
  7. *
  8. * BSP Support for Samsung's UDC driver
  9. * available at:
  10. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  11. *
  12. * State machine bugfixes:
  13. * Marek Szyprowski <m.szyprowski@samsung.com>
  14. *
  15. * Ported to u-boot:
  16. * Marek Szyprowski <m.szyprowski@samsung.com>
  17. * Lukasz Majewski <l.majewski@samsumg.com>
  18. */
  19. #undef DEBUG
  20. #include <common.h>
  21. #include <clk.h>
  22. #include <dm.h>
  23. #include <generic-phy.h>
  24. #include <log.h>
  25. #include <malloc.h>
  26. #include <reset.h>
  27. #include <dm/device_compat.h>
  28. #include <dm/devres.h>
  29. #include <linux/bug.h>
  30. #include <linux/delay.h>
  31. #include <linux/errno.h>
  32. #include <linux/list.h>
  33. #include <linux/usb/ch9.h>
  34. #include <linux/usb/otg.h>
  35. #include <linux/usb/gadget.h>
  36. #include <phys2bus.h>
  37. #include <asm/byteorder.h>
  38. #include <asm/unaligned.h>
  39. #include <asm/io.h>
  40. #include <asm/mach-types.h>
  41. #include <power/regulator.h>
  42. #include "dwc2_udc_otg_regs.h"
  43. #include "dwc2_udc_otg_priv.h"
  44. /***********************************************************/
  45. #define OTG_DMA_MODE 1
  46. #define DEBUG_SETUP 0
  47. #define DEBUG_EP0 0
  48. #define DEBUG_ISR 0
  49. #define DEBUG_OUT_EP 0
  50. #define DEBUG_IN_EP 0
  51. #include <usb/dwc2_udc.h>
  52. #define EP0_CON 0
  53. #define EP_MASK 0xF
  54. static char *state_names[] = {
  55. "WAIT_FOR_SETUP",
  56. "DATA_STATE_XMIT",
  57. "DATA_STATE_NEED_ZLP",
  58. "WAIT_FOR_OUT_STATUS",
  59. "DATA_STATE_RECV",
  60. "WAIT_FOR_COMPLETE",
  61. "WAIT_FOR_OUT_COMPLETE",
  62. "WAIT_FOR_IN_COMPLETE",
  63. "WAIT_FOR_NULL_COMPLETE",
  64. };
  65. #define DRIVER_VERSION "15 March 2009"
  66. struct dwc2_udc *the_controller;
  67. static const char driver_name[] = "dwc2-udc";
  68. static const char ep0name[] = "ep0-control";
  69. /* Max packet size*/
  70. static unsigned int ep0_fifo_size = 64;
  71. static unsigned int ep_fifo_size = 512;
  72. static unsigned int ep_fifo_size2 = 1024;
  73. static int reset_available = 1;
  74. static struct usb_ctrlrequest *usb_ctrl;
  75. static dma_addr_t usb_ctrl_dma_addr;
  76. /*
  77. Local declarations.
  78. */
  79. static int dwc2_ep_enable(struct usb_ep *ep,
  80. const struct usb_endpoint_descriptor *);
  81. static int dwc2_ep_disable(struct usb_ep *ep);
  82. static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
  83. gfp_t gfp_flags);
  84. static void dwc2_free_request(struct usb_ep *ep, struct usb_request *);
  85. static int dwc2_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
  86. static int dwc2_dequeue(struct usb_ep *ep, struct usb_request *);
  87. static int dwc2_fifo_status(struct usb_ep *ep);
  88. static void dwc2_fifo_flush(struct usb_ep *ep);
  89. static void dwc2_ep0_read(struct dwc2_udc *dev);
  90. static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep);
  91. static void dwc2_handle_ep0(struct dwc2_udc *dev);
  92. static int dwc2_ep0_write(struct dwc2_udc *dev);
  93. static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req);
  94. static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status);
  95. static void stop_activity(struct dwc2_udc *dev,
  96. struct usb_gadget_driver *driver);
  97. static int udc_enable(struct dwc2_udc *dev);
  98. static void udc_set_address(struct dwc2_udc *dev, unsigned char address);
  99. static void reconfig_usbd(struct dwc2_udc *dev);
  100. static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed);
  101. static void nuke(struct dwc2_ep *ep, int status);
  102. static int dwc2_udc_set_halt(struct usb_ep *_ep, int value);
  103. static void dwc2_udc_set_nak(struct dwc2_ep *ep);
  104. void set_udc_gadget_private_data(void *p)
  105. {
  106. debug_cond(DEBUG_SETUP != 0,
  107. "%s: the_controller: 0x%p, p: 0x%p\n", __func__,
  108. the_controller, p);
  109. the_controller->gadget.dev.device_data = p;
  110. }
  111. void *get_udc_gadget_private_data(struct usb_gadget *gadget)
  112. {
  113. return gadget->dev.device_data;
  114. }
  115. static struct usb_ep_ops dwc2_ep_ops = {
  116. .enable = dwc2_ep_enable,
  117. .disable = dwc2_ep_disable,
  118. .alloc_request = dwc2_alloc_request,
  119. .free_request = dwc2_free_request,
  120. .queue = dwc2_queue,
  121. .dequeue = dwc2_dequeue,
  122. .set_halt = dwc2_udc_set_halt,
  123. .fifo_status = dwc2_fifo_status,
  124. .fifo_flush = dwc2_fifo_flush,
  125. };
  126. #define create_proc_files() do {} while (0)
  127. #define remove_proc_files() do {} while (0)
  128. /***********************************************************/
  129. struct dwc2_usbotg_reg *reg;
  130. bool dfu_usb_get_reset(void)
  131. {
  132. return !!(readl(&reg->gintsts) & INT_RESET);
  133. }
  134. __weak void otg_phy_init(struct dwc2_udc *dev) {}
  135. __weak void otg_phy_off(struct dwc2_udc *dev) {}
  136. /***********************************************************/
  137. #include "dwc2_udc_otg_xfer_dma.c"
  138. /*
  139. * udc_disable - disable USB device controller
  140. */
  141. static void udc_disable(struct dwc2_udc *dev)
  142. {
  143. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  144. udc_set_address(dev, 0);
  145. dev->ep0state = WAIT_FOR_SETUP;
  146. dev->gadget.speed = USB_SPEED_UNKNOWN;
  147. dev->usb_address = 0;
  148. otg_phy_off(dev);
  149. }
  150. /*
  151. * udc_reinit - initialize software state
  152. */
  153. static void udc_reinit(struct dwc2_udc *dev)
  154. {
  155. unsigned int i;
  156. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  157. /* device/ep0 records init */
  158. INIT_LIST_HEAD(&dev->gadget.ep_list);
  159. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  160. dev->ep0state = WAIT_FOR_SETUP;
  161. /* basic endpoint records init */
  162. for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
  163. struct dwc2_ep *ep = &dev->ep[i];
  164. if (i != 0)
  165. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  166. ep->desc = 0;
  167. ep->stopped = 0;
  168. INIT_LIST_HEAD(&ep->queue);
  169. ep->pio_irqs = 0;
  170. }
  171. /* the rest was statically initialized, and is read-only */
  172. }
  173. #define BYTES2MAXP(x) (x / 8)
  174. #define MAXP2BYTES(x) (x * 8)
  175. /* until it's enabled, this UDC should be completely invisible
  176. * to any USB host.
  177. */
  178. static int udc_enable(struct dwc2_udc *dev)
  179. {
  180. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  181. otg_phy_init(dev);
  182. reconfig_usbd(dev);
  183. debug_cond(DEBUG_SETUP != 0,
  184. "DWC2 USB 2.0 OTG Controller Core Initialized : 0x%x\n",
  185. readl(&reg->gintmsk));
  186. dev->gadget.speed = USB_SPEED_UNKNOWN;
  187. return 0;
  188. }
  189. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  190. /*
  191. Register entry point for the peripheral controller driver.
  192. */
  193. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  194. {
  195. struct dwc2_udc *dev = the_controller;
  196. int retval = 0;
  197. unsigned long flags = 0;
  198. debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
  199. if (!driver
  200. || (driver->speed != USB_SPEED_FULL
  201. && driver->speed != USB_SPEED_HIGH)
  202. || !driver->bind || !driver->disconnect || !driver->setup)
  203. return -EINVAL;
  204. if (!dev)
  205. return -ENODEV;
  206. if (dev->driver)
  207. return -EBUSY;
  208. spin_lock_irqsave(&dev->lock, flags);
  209. /* first hook up the driver ... */
  210. dev->driver = driver;
  211. spin_unlock_irqrestore(&dev->lock, flags);
  212. if (retval) { /* TODO */
  213. printf("target device_add failed, error %d\n", retval);
  214. return retval;
  215. }
  216. retval = driver->bind(&dev->gadget);
  217. if (retval) {
  218. debug_cond(DEBUG_SETUP != 0,
  219. "%s: bind to driver --> error %d\n",
  220. dev->gadget.name, retval);
  221. dev->driver = 0;
  222. return retval;
  223. }
  224. enable_irq(IRQ_OTG);
  225. debug_cond(DEBUG_SETUP != 0,
  226. "Registered gadget driver %s\n", dev->gadget.name);
  227. udc_enable(dev);
  228. return 0;
  229. }
  230. /*
  231. * Unregister entry point for the peripheral controller driver.
  232. */
  233. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  234. {
  235. struct dwc2_udc *dev = the_controller;
  236. unsigned long flags = 0;
  237. if (!dev)
  238. return -ENODEV;
  239. if (!driver || driver != dev->driver)
  240. return -EINVAL;
  241. spin_lock_irqsave(&dev->lock, flags);
  242. dev->driver = 0;
  243. stop_activity(dev, driver);
  244. spin_unlock_irqrestore(&dev->lock, flags);
  245. driver->unbind(&dev->gadget);
  246. disable_irq(IRQ_OTG);
  247. udc_disable(dev);
  248. return 0;
  249. }
  250. #else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  251. static int dwc2_gadget_start(struct usb_gadget *g,
  252. struct usb_gadget_driver *driver)
  253. {
  254. struct dwc2_udc *dev = the_controller;
  255. debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
  256. if (!driver ||
  257. (driver->speed != USB_SPEED_FULL &&
  258. driver->speed != USB_SPEED_HIGH) ||
  259. !driver->bind || !driver->disconnect || !driver->setup)
  260. return -EINVAL;
  261. if (!dev)
  262. return -ENODEV;
  263. if (dev->driver)
  264. return -EBUSY;
  265. /* first hook up the driver ... */
  266. dev->driver = driver;
  267. debug_cond(DEBUG_SETUP != 0,
  268. "Registered gadget driver %s\n", dev->gadget.name);
  269. return udc_enable(dev);
  270. }
  271. static int dwc2_gadget_stop(struct usb_gadget *g)
  272. {
  273. struct dwc2_udc *dev = the_controller;
  274. if (!dev)
  275. return -ENODEV;
  276. if (!dev->driver)
  277. return -EINVAL;
  278. dev->driver = 0;
  279. stop_activity(dev, dev->driver);
  280. udc_disable(dev);
  281. return 0;
  282. }
  283. #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  284. /*
  285. * done - retire a request; caller blocked irqs
  286. */
  287. static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status)
  288. {
  289. unsigned int stopped = ep->stopped;
  290. debug("%s: %s %p, req = %p, stopped = %d\n",
  291. __func__, ep->ep.name, ep, &req->req, stopped);
  292. list_del_init(&req->queue);
  293. if (likely(req->req.status == -EINPROGRESS))
  294. req->req.status = status;
  295. else
  296. status = req->req.status;
  297. if (status && status != -ESHUTDOWN) {
  298. debug("complete %s req %p stat %d len %u/%u\n",
  299. ep->ep.name, &req->req, status,
  300. req->req.actual, req->req.length);
  301. }
  302. /* don't modify queue heads during completion callback */
  303. ep->stopped = 1;
  304. #ifdef DEBUG
  305. printf("calling complete callback\n");
  306. {
  307. int i, len = req->req.length;
  308. printf("pkt[%d] = ", req->req.length);
  309. if (len > 64)
  310. len = 64;
  311. for (i = 0; i < len; i++) {
  312. printf("%02x", ((u8 *)req->req.buf)[i]);
  313. if ((i & 7) == 7)
  314. printf(" ");
  315. }
  316. printf("\n");
  317. }
  318. #endif
  319. spin_unlock(&ep->dev->lock);
  320. req->req.complete(&ep->ep, &req->req);
  321. spin_lock(&ep->dev->lock);
  322. debug("callback completed\n");
  323. ep->stopped = stopped;
  324. }
  325. /*
  326. * nuke - dequeue ALL requests
  327. */
  328. static void nuke(struct dwc2_ep *ep, int status)
  329. {
  330. struct dwc2_request *req;
  331. debug("%s: %s %p\n", __func__, ep->ep.name, ep);
  332. /* called with irqs blocked */
  333. while (!list_empty(&ep->queue)) {
  334. req = list_entry(ep->queue.next, struct dwc2_request, queue);
  335. done(ep, req, status);
  336. }
  337. }
  338. static void stop_activity(struct dwc2_udc *dev,
  339. struct usb_gadget_driver *driver)
  340. {
  341. int i;
  342. /* don't disconnect drivers more than once */
  343. if (dev->gadget.speed == USB_SPEED_UNKNOWN)
  344. driver = 0;
  345. dev->gadget.speed = USB_SPEED_UNKNOWN;
  346. /* prevent new request submissions, kill any outstanding requests */
  347. for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
  348. struct dwc2_ep *ep = &dev->ep[i];
  349. ep->stopped = 1;
  350. nuke(ep, -ESHUTDOWN);
  351. }
  352. /* report disconnect; the driver is already quiesced */
  353. if (driver) {
  354. spin_unlock(&dev->lock);
  355. driver->disconnect(&dev->gadget);
  356. spin_lock(&dev->lock);
  357. }
  358. /* re-init driver-visible data structures */
  359. udc_reinit(dev);
  360. }
  361. static void reconfig_usbd(struct dwc2_udc *dev)
  362. {
  363. /* 2. Soft-reset OTG Core and then unreset again. */
  364. int i;
  365. unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
  366. uint32_t dflt_gusbcfg;
  367. uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
  368. u32 max_hw_ep;
  369. int pdata_hw_ep;
  370. debug("Reseting OTG controller\n");
  371. dflt_gusbcfg =
  372. 0<<15 /* PHY Low Power Clock sel*/
  373. |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
  374. |0x5<<10 /* Turnaround time*/
  375. |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
  376. /* 1:SRP enable] H1= 1,1*/
  377. |0<<7 /* Ulpi DDR sel*/
  378. |0<<6 /* 0: high speed utmi+, 1: full speed serial*/
  379. |0<<4 /* 0: utmi+, 1:ulpi*/
  380. #ifdef CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
  381. |0<<3 /* phy i/f 0:8bit, 1:16bit*/
  382. #else
  383. |1<<3 /* phy i/f 0:8bit, 1:16bit*/
  384. #endif
  385. |0x7<<0; /* HS/FS Timeout**/
  386. if (dev->pdata->usb_gusbcfg)
  387. dflt_gusbcfg = dev->pdata->usb_gusbcfg;
  388. writel(dflt_gusbcfg, &reg->gusbcfg);
  389. /* 3. Put the OTG device core in the disconnected state.*/
  390. uTemp = readl(&reg->dctl);
  391. uTemp |= SOFT_DISCONNECT;
  392. writel(uTemp, &reg->dctl);
  393. udelay(20);
  394. /* 4. Make the OTG device core exit from the disconnected state.*/
  395. uTemp = readl(&reg->dctl);
  396. uTemp = uTemp & ~SOFT_DISCONNECT;
  397. writel(uTemp, &reg->dctl);
  398. /* 5. Configure OTG Core to initial settings of device mode.*/
  399. /* [][1: full speed(30Mhz) 0:high speed]*/
  400. writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->dcfg);
  401. mdelay(1);
  402. /* 6. Unmask the core interrupts*/
  403. writel(GINTMSK_INIT, &reg->gintmsk);
  404. /* 7. Set NAK bit of EP0, EP1, EP2*/
  405. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
  406. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
  407. for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) {
  408. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
  409. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
  410. }
  411. /* 8. Unmask EPO interrupts*/
  412. writel(((1 << EP0_CON) << DAINT_OUT_BIT)
  413. | (1 << EP0_CON), &reg->daintmsk);
  414. /* 9. Unmask device OUT EP common interrupts*/
  415. writel(DOEPMSK_INIT, &reg->doepmsk);
  416. /* 10. Unmask device IN EP common interrupts*/
  417. writel(DIEPMSK_INIT, &reg->diepmsk);
  418. rx_fifo_sz = RX_FIFO_SIZE;
  419. np_tx_fifo_sz = NPTX_FIFO_SIZE;
  420. tx_fifo_sz = PTX_FIFO_SIZE;
  421. if (dev->pdata->rx_fifo_sz)
  422. rx_fifo_sz = dev->pdata->rx_fifo_sz;
  423. if (dev->pdata->np_tx_fifo_sz)
  424. np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz;
  425. if (dev->pdata->tx_fifo_sz)
  426. tx_fifo_sz = dev->pdata->tx_fifo_sz;
  427. /* 11. Set Rx FIFO Size (in 32-bit words) */
  428. writel(rx_fifo_sz, &reg->grxfsiz);
  429. /* 12. Set Non Periodic Tx FIFO Size */
  430. writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
  431. &reg->gnptxfsiz);
  432. /* retrieve the number of IN Endpoints (excluding ep0) */
  433. max_hw_ep = (readl(&reg->ghwcfg4) & GHWCFG4_NUM_IN_EPS_MASK) >>
  434. GHWCFG4_NUM_IN_EPS_SHIFT;
  435. pdata_hw_ep = dev->pdata->tx_fifo_sz_nb;
  436. /* tx_fifo_sz_nb should equal to number of IN Endpoint */
  437. if (pdata_hw_ep && max_hw_ep != pdata_hw_ep)
  438. pr_warn("Got %d hw endpoint but %d tx-fifo-size in array !!\n",
  439. max_hw_ep, pdata_hw_ep);
  440. for (i = 0; i < max_hw_ep; i++) {
  441. if (pdata_hw_ep)
  442. tx_fifo_sz = dev->pdata->tx_fifo_sz_array[i];
  443. writel((rx_fifo_sz + np_tx_fifo_sz + (tx_fifo_sz * i)) |
  444. tx_fifo_sz << 16, &reg->dieptxf[i]);
  445. }
  446. /* Flush the RX FIFO */
  447. writel(RX_FIFO_FLUSH, &reg->grstctl);
  448. while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
  449. debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
  450. /* Flush all the Tx FIFO's */
  451. writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
  452. writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
  453. while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
  454. debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
  455. /* 13. Clear NAK bit of EP0, EP1, EP2*/
  456. /* For Slave mode*/
  457. /* EP0: Control OUT */
  458. writel(DEPCTL_EPDIS | DEPCTL_CNAK,
  459. &reg->out_endp[EP0_CON].doepctl);
  460. /* 14. Initialize OTG Link Core.*/
  461. writel(GAHBCFG_INIT, &reg->gahbcfg);
  462. }
  463. static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed)
  464. {
  465. unsigned int ep_ctrl;
  466. int i;
  467. if (speed == USB_SPEED_HIGH) {
  468. ep0_fifo_size = 64;
  469. ep_fifo_size = 512;
  470. ep_fifo_size2 = 1024;
  471. dev->gadget.speed = USB_SPEED_HIGH;
  472. } else {
  473. ep0_fifo_size = 64;
  474. ep_fifo_size = 64;
  475. ep_fifo_size2 = 64;
  476. dev->gadget.speed = USB_SPEED_FULL;
  477. }
  478. dev->ep[0].ep.maxpacket = ep0_fifo_size;
  479. for (i = 1; i < DWC2_MAX_ENDPOINTS; i++)
  480. dev->ep[i].ep.maxpacket = ep_fifo_size;
  481. /* EP0 - Control IN (64 bytes)*/
  482. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  483. writel(ep_ctrl|(0<<0), &reg->in_endp[EP0_CON].diepctl);
  484. /* EP0 - Control OUT (64 bytes)*/
  485. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  486. writel(ep_ctrl|(0<<0), &reg->out_endp[EP0_CON].doepctl);
  487. }
  488. static int dwc2_ep_enable(struct usb_ep *_ep,
  489. const struct usb_endpoint_descriptor *desc)
  490. {
  491. struct dwc2_ep *ep;
  492. struct dwc2_udc *dev;
  493. unsigned long flags = 0;
  494. debug("%s: %p\n", __func__, _ep);
  495. ep = container_of(_ep, struct dwc2_ep, ep);
  496. if (!_ep || !desc || ep->desc || _ep->name == ep0name
  497. || desc->bDescriptorType != USB_DT_ENDPOINT
  498. || ep->bEndpointAddress != desc->bEndpointAddress
  499. || ep_maxpacket(ep) <
  500. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
  501. debug("%s: bad ep or descriptor\n", __func__);
  502. return -EINVAL;
  503. }
  504. /* xfer types must match, except that interrupt ~= bulk */
  505. if (ep->bmAttributes != desc->bmAttributes
  506. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  507. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  508. debug("%s: %s type mismatch\n", __func__, _ep->name);
  509. return -EINVAL;
  510. }
  511. /* hardware _could_ do smaller, but driver doesn't */
  512. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK &&
  513. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) >
  514. ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
  515. debug("%s: bad %s maxpacket\n", __func__, _ep->name);
  516. return -ERANGE;
  517. }
  518. dev = ep->dev;
  519. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
  520. debug("%s: bogus device state\n", __func__);
  521. return -ESHUTDOWN;
  522. }
  523. ep->stopped = 0;
  524. ep->desc = desc;
  525. ep->pio_irqs = 0;
  526. ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
  527. /* Reset halt state */
  528. dwc2_udc_set_nak(ep);
  529. dwc2_udc_set_halt(_ep, 0);
  530. spin_lock_irqsave(&ep->dev->lock, flags);
  531. dwc2_udc_ep_activate(ep);
  532. spin_unlock_irqrestore(&ep->dev->lock, flags);
  533. debug("%s: enabled %s, stopped = %d, maxpacket = %d\n",
  534. __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
  535. return 0;
  536. }
  537. /*
  538. * Disable EP
  539. */
  540. static int dwc2_ep_disable(struct usb_ep *_ep)
  541. {
  542. struct dwc2_ep *ep;
  543. unsigned long flags = 0;
  544. debug("%s: %p\n", __func__, _ep);
  545. ep = container_of(_ep, struct dwc2_ep, ep);
  546. if (!_ep || !ep->desc) {
  547. debug("%s: %s not enabled\n", __func__,
  548. _ep ? ep->ep.name : NULL);
  549. return -EINVAL;
  550. }
  551. spin_lock_irqsave(&ep->dev->lock, flags);
  552. /* Nuke all pending requests */
  553. nuke(ep, -ESHUTDOWN);
  554. ep->desc = 0;
  555. ep->stopped = 1;
  556. spin_unlock_irqrestore(&ep->dev->lock, flags);
  557. debug("%s: disabled %s\n", __func__, _ep->name);
  558. return 0;
  559. }
  560. static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
  561. gfp_t gfp_flags)
  562. {
  563. struct dwc2_request *req;
  564. debug("%s: %s %p\n", __func__, ep->name, ep);
  565. req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req));
  566. if (!req)
  567. return 0;
  568. memset(req, 0, sizeof *req);
  569. INIT_LIST_HEAD(&req->queue);
  570. return &req->req;
  571. }
  572. static void dwc2_free_request(struct usb_ep *ep, struct usb_request *_req)
  573. {
  574. struct dwc2_request *req;
  575. debug("%s: %p\n", __func__, ep);
  576. req = container_of(_req, struct dwc2_request, req);
  577. WARN_ON(!list_empty(&req->queue));
  578. kfree(req);
  579. }
  580. /* dequeue JUST ONE request */
  581. static int dwc2_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  582. {
  583. struct dwc2_ep *ep;
  584. struct dwc2_request *req;
  585. unsigned long flags = 0;
  586. debug("%s: %p\n", __func__, _ep);
  587. ep = container_of(_ep, struct dwc2_ep, ep);
  588. if (!_ep || ep->ep.name == ep0name)
  589. return -EINVAL;
  590. spin_lock_irqsave(&ep->dev->lock, flags);
  591. /* make sure it's actually queued on this endpoint */
  592. list_for_each_entry(req, &ep->queue, queue) {
  593. if (&req->req == _req)
  594. break;
  595. }
  596. if (&req->req != _req) {
  597. spin_unlock_irqrestore(&ep->dev->lock, flags);
  598. return -EINVAL;
  599. }
  600. done(ep, req, -ECONNRESET);
  601. spin_unlock_irqrestore(&ep->dev->lock, flags);
  602. return 0;
  603. }
  604. /*
  605. * Return bytes in EP FIFO
  606. */
  607. static int dwc2_fifo_status(struct usb_ep *_ep)
  608. {
  609. int count = 0;
  610. struct dwc2_ep *ep;
  611. ep = container_of(_ep, struct dwc2_ep, ep);
  612. if (!_ep) {
  613. debug("%s: bad ep\n", __func__);
  614. return -ENODEV;
  615. }
  616. debug("%s: %d\n", __func__, ep_index(ep));
  617. /* LPD can't report unclaimed bytes from IN fifos */
  618. if (ep_is_in(ep))
  619. return -EOPNOTSUPP;
  620. return count;
  621. }
  622. /*
  623. * Flush EP FIFO
  624. */
  625. static void dwc2_fifo_flush(struct usb_ep *_ep)
  626. {
  627. struct dwc2_ep *ep;
  628. ep = container_of(_ep, struct dwc2_ep, ep);
  629. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  630. debug("%s: bad ep\n", __func__);
  631. return;
  632. }
  633. debug("%s: %d\n", __func__, ep_index(ep));
  634. }
  635. static const struct usb_gadget_ops dwc2_udc_ops = {
  636. /* current versions must always be self-powered */
  637. #if CONFIG_IS_ENABLED(DM_USB_GADGET)
  638. .udc_start = dwc2_gadget_start,
  639. .udc_stop = dwc2_gadget_stop,
  640. #endif
  641. };
  642. static struct dwc2_udc memory = {
  643. .usb_address = 0,
  644. .gadget = {
  645. .ops = &dwc2_udc_ops,
  646. .ep0 = &memory.ep[0].ep,
  647. .name = driver_name,
  648. },
  649. /* control endpoint */
  650. .ep[0] = {
  651. .ep = {
  652. .name = ep0name,
  653. .ops = &dwc2_ep_ops,
  654. .maxpacket = EP0_FIFO_SIZE,
  655. },
  656. .dev = &memory,
  657. .bEndpointAddress = 0,
  658. .bmAttributes = 0,
  659. .ep_type = ep_control,
  660. },
  661. /* first group of endpoints */
  662. .ep[1] = {
  663. .ep = {
  664. .name = "ep1in-bulk",
  665. .ops = &dwc2_ep_ops,
  666. .maxpacket = EP_FIFO_SIZE,
  667. },
  668. .dev = &memory,
  669. .bEndpointAddress = USB_DIR_IN | 1,
  670. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  671. .ep_type = ep_bulk_out,
  672. .fifo_num = 1,
  673. },
  674. .ep[2] = {
  675. .ep = {
  676. .name = "ep2out-bulk",
  677. .ops = &dwc2_ep_ops,
  678. .maxpacket = EP_FIFO_SIZE,
  679. },
  680. .dev = &memory,
  681. .bEndpointAddress = USB_DIR_OUT | 2,
  682. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  683. .ep_type = ep_bulk_in,
  684. .fifo_num = 2,
  685. },
  686. .ep[3] = {
  687. .ep = {
  688. .name = "ep3in-int",
  689. .ops = &dwc2_ep_ops,
  690. .maxpacket = EP_FIFO_SIZE,
  691. },
  692. .dev = &memory,
  693. .bEndpointAddress = USB_DIR_IN | 3,
  694. .bmAttributes = USB_ENDPOINT_XFER_INT,
  695. .ep_type = ep_interrupt,
  696. .fifo_num = 3,
  697. },
  698. };
  699. /*
  700. * probe - binds to the platform device
  701. */
  702. int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata)
  703. {
  704. struct dwc2_udc *dev = &memory;
  705. int retval = 0;
  706. debug("%s: %p\n", __func__, pdata);
  707. dev->pdata = pdata;
  708. reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
  709. dev->gadget.is_dualspeed = 1; /* Hack only*/
  710. dev->gadget.is_otg = 0;
  711. dev->gadget.is_a_peripheral = 0;
  712. dev->gadget.b_hnp_enable = 0;
  713. dev->gadget.a_hnp_support = 0;
  714. dev->gadget.a_alt_hnp_support = 0;
  715. the_controller = dev;
  716. usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE,
  717. ROUND(sizeof(struct usb_ctrlrequest),
  718. CONFIG_SYS_CACHELINE_SIZE));
  719. if (!usb_ctrl) {
  720. pr_err("No memory available for UDC!\n");
  721. return -ENOMEM;
  722. }
  723. usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl;
  724. udc_reinit(dev);
  725. return retval;
  726. }
  727. int dwc2_udc_handle_interrupt(void)
  728. {
  729. u32 intr_status = readl(&reg->gintsts);
  730. u32 gintmsk = readl(&reg->gintmsk);
  731. if (intr_status & gintmsk)
  732. return dwc2_udc_irq(1, (void *)the_controller);
  733. return 0;
  734. }
  735. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  736. int usb_gadget_handle_interrupts(int index)
  737. {
  738. return dwc2_udc_handle_interrupt();
  739. }
  740. #else /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
  741. struct dwc2_priv_data {
  742. struct clk_bulk clks;
  743. struct reset_ctl_bulk resets;
  744. struct phy_bulk phys;
  745. struct udevice *usb33d_supply;
  746. };
  747. int dm_usb_gadget_handle_interrupts(struct udevice *dev)
  748. {
  749. return dwc2_udc_handle_interrupt();
  750. }
  751. static int dwc2_phy_setup(struct udevice *dev, struct phy_bulk *phys)
  752. {
  753. int ret;
  754. ret = generic_phy_get_bulk(dev, phys);
  755. if (ret)
  756. return ret;
  757. ret = generic_phy_init_bulk(phys);
  758. if (ret)
  759. return ret;
  760. ret = generic_phy_power_on_bulk(phys);
  761. if (ret)
  762. generic_phy_exit_bulk(phys);
  763. return ret;
  764. }
  765. static void dwc2_phy_shutdown(struct udevice *dev, struct phy_bulk *phys)
  766. {
  767. generic_phy_power_off_bulk(phys);
  768. generic_phy_exit_bulk(phys);
  769. }
  770. static int dwc2_udc_otg_of_to_plat(struct udevice *dev)
  771. {
  772. struct dwc2_plat_otg_data *plat = dev_get_plat(dev);
  773. ulong drvdata;
  774. void (*set_params)(struct dwc2_plat_otg_data *data);
  775. int ret;
  776. if (usb_get_dr_mode(dev_ofnode(dev)) != USB_DR_MODE_PERIPHERAL &&
  777. usb_get_dr_mode(dev_ofnode(dev)) != USB_DR_MODE_OTG) {
  778. dev_dbg(dev, "Invalid mode\n");
  779. return -ENODEV;
  780. }
  781. plat->regs_otg = dev_read_addr(dev);
  782. plat->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0);
  783. plat->np_tx_fifo_sz = dev_read_u32_default(dev, "g-np-tx-fifo-size", 0);
  784. plat->tx_fifo_sz_nb =
  785. dev_read_size(dev, "g-tx-fifo-size") / sizeof(u32);
  786. if (plat->tx_fifo_sz_nb > DWC2_MAX_HW_ENDPOINTS)
  787. plat->tx_fifo_sz_nb = DWC2_MAX_HW_ENDPOINTS;
  788. if (plat->tx_fifo_sz_nb) {
  789. ret = dev_read_u32_array(dev, "g-tx-fifo-size",
  790. plat->tx_fifo_sz_array,
  791. plat->tx_fifo_sz_nb);
  792. if (ret)
  793. return ret;
  794. }
  795. plat->force_b_session_valid =
  796. dev_read_bool(dev, "u-boot,force-b-session-valid");
  797. plat->force_vbus_detection =
  798. dev_read_bool(dev, "u-boot,force-vbus-detection");
  799. /* force plat according compatible */
  800. drvdata = dev_get_driver_data(dev);
  801. if (drvdata) {
  802. set_params = (void *)drvdata;
  803. set_params(plat);
  804. }
  805. return 0;
  806. }
  807. static void dwc2_set_stm32mp1_hsotg_params(struct dwc2_plat_otg_data *p)
  808. {
  809. p->activate_stm_id_vb_detection = true;
  810. p->usb_gusbcfg =
  811. 0 << 15 /* PHY Low Power Clock sel*/
  812. | 0x9 << 10 /* USB Turnaround time (0x9 for HS phy) */
  813. | 0 << 9 /* [0:HNP disable,1:HNP enable]*/
  814. | 0 << 8 /* [0:SRP disable 1:SRP enable]*/
  815. | 0 << 6 /* 0: high speed utmi+, 1: full speed serial*/
  816. | 0x7 << 0; /* FS timeout calibration**/
  817. if (p->force_b_session_valid)
  818. p->usb_gusbcfg |= 1 << 30; /* FDMOD: Force device mode */
  819. }
  820. static int dwc2_udc_otg_reset_init(struct udevice *dev,
  821. struct reset_ctl_bulk *resets)
  822. {
  823. int ret;
  824. ret = reset_get_bulk(dev, resets);
  825. if (ret == -ENOTSUPP || ret == -ENOENT)
  826. return 0;
  827. if (ret)
  828. return ret;
  829. ret = reset_assert_bulk(resets);
  830. if (!ret) {
  831. udelay(2);
  832. ret = reset_deassert_bulk(resets);
  833. }
  834. if (ret) {
  835. reset_release_bulk(resets);
  836. return ret;
  837. }
  838. return 0;
  839. }
  840. static int dwc2_udc_otg_clk_init(struct udevice *dev,
  841. struct clk_bulk *clks)
  842. {
  843. int ret;
  844. ret = clk_get_bulk(dev, clks);
  845. if (ret == -ENOSYS)
  846. return 0;
  847. if (ret)
  848. return ret;
  849. ret = clk_enable_bulk(clks);
  850. if (ret) {
  851. clk_release_bulk(clks);
  852. return ret;
  853. }
  854. return 0;
  855. }
  856. static int dwc2_udc_otg_probe(struct udevice *dev)
  857. {
  858. struct dwc2_plat_otg_data *plat = dev_get_plat(dev);
  859. struct dwc2_priv_data *priv = dev_get_priv(dev);
  860. struct dwc2_usbotg_reg *usbotg_reg =
  861. (struct dwc2_usbotg_reg *)plat->regs_otg;
  862. int ret;
  863. ret = dwc2_udc_otg_clk_init(dev, &priv->clks);
  864. if (ret)
  865. return ret;
  866. ret = dwc2_udc_otg_reset_init(dev, &priv->resets);
  867. if (ret)
  868. return ret;
  869. ret = dwc2_phy_setup(dev, &priv->phys);
  870. if (ret)
  871. return ret;
  872. if (plat->activate_stm_id_vb_detection) {
  873. if (CONFIG_IS_ENABLED(DM_REGULATOR) &&
  874. (!plat->force_b_session_valid ||
  875. plat->force_vbus_detection)) {
  876. ret = device_get_supply_regulator(dev, "usb33d-supply",
  877. &priv->usb33d_supply);
  878. if (ret) {
  879. dev_err(dev, "can't get voltage level detector supply\n");
  880. return ret;
  881. }
  882. ret = regulator_set_enable(priv->usb33d_supply, true);
  883. if (ret) {
  884. dev_err(dev, "can't enable voltage level detector supply\n");
  885. return ret;
  886. }
  887. }
  888. if (plat->force_b_session_valid &&
  889. !plat->force_vbus_detection) {
  890. /* Override VBUS detection: enable then value*/
  891. setbits_le32(&usbotg_reg->gotgctl, VB_VALOEN);
  892. setbits_le32(&usbotg_reg->gotgctl, VB_VALOVAL);
  893. } else {
  894. /* Enable VBUS sensing */
  895. setbits_le32(&usbotg_reg->ggpio,
  896. GGPIO_STM32_OTG_GCCFG_VBDEN);
  897. }
  898. if (plat->force_b_session_valid) {
  899. /* Override B session bits: enable then value */
  900. setbits_le32(&usbotg_reg->gotgctl, A_VALOEN | B_VALOEN);
  901. setbits_le32(&usbotg_reg->gotgctl,
  902. A_VALOVAL | B_VALOVAL);
  903. } else {
  904. /* Enable ID detection */
  905. setbits_le32(&usbotg_reg->ggpio,
  906. GGPIO_STM32_OTG_GCCFG_IDEN);
  907. }
  908. }
  909. ret = dwc2_udc_probe(plat);
  910. if (ret)
  911. return ret;
  912. the_controller->driver = 0;
  913. ret = usb_add_gadget_udc((struct device *)dev, &the_controller->gadget);
  914. return ret;
  915. }
  916. static int dwc2_udc_otg_remove(struct udevice *dev)
  917. {
  918. struct dwc2_priv_data *priv = dev_get_priv(dev);
  919. usb_del_gadget_udc(&the_controller->gadget);
  920. reset_release_bulk(&priv->resets);
  921. clk_release_bulk(&priv->clks);
  922. dwc2_phy_shutdown(dev, &priv->phys);
  923. return dm_scan_fdt_dev(dev);
  924. }
  925. static const struct udevice_id dwc2_udc_otg_ids[] = {
  926. { .compatible = "snps,dwc2" },
  927. { .compatible = "brcm,bcm2835-usb" },
  928. { .compatible = "st,stm32mp1-hsotg",
  929. .data = (ulong)dwc2_set_stm32mp1_hsotg_params },
  930. {},
  931. };
  932. U_BOOT_DRIVER(dwc2_udc_otg) = {
  933. .name = "dwc2-udc-otg",
  934. .id = UCLASS_USB_GADGET_GENERIC,
  935. .of_match = dwc2_udc_otg_ids,
  936. .of_to_plat = dwc2_udc_otg_of_to_plat,
  937. .probe = dwc2_udc_otg_probe,
  938. .remove = dwc2_udc_otg_remove,
  939. .plat_auto = sizeof(struct dwc2_plat_otg_data),
  940. .priv_auto = sizeof(struct dwc2_priv_data),
  941. };
  942. int dwc2_udc_B_session_valid(struct udevice *dev)
  943. {
  944. struct dwc2_plat_otg_data *plat = dev_get_plat(dev);
  945. struct dwc2_usbotg_reg *usbotg_reg =
  946. (struct dwc2_usbotg_reg *)plat->regs_otg;
  947. return readl(&usbotg_reg->gotgctl) & B_SESSION_VALID;
  948. }
  949. #endif /* CONFIG_IS_ENABLED(DM_USB_GADGET) */