core.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * core.c - DesignWare USB3 DRD Controller Core file
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
  11. * to uboot.
  12. *
  13. * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <malloc.h>
  18. #include <dwc3-uboot.h>
  19. #include <dm/device_compat.h>
  20. #include <dm/devres.h>
  21. #include <linux/bug.h>
  22. #include <linux/delay.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/err.h>
  25. #include <linux/ioport.h>
  26. #include <dm.h>
  27. #include <generic-phy.h>
  28. #include <linux/usb/ch9.h>
  29. #include <linux/usb/gadget.h>
  30. #include "core.h"
  31. #include "gadget.h"
  32. #include "io.h"
  33. #include "linux-compat.h"
  34. static LIST_HEAD(dwc3_list);
  35. /* -------------------------------------------------------------------------- */
  36. static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  37. {
  38. u32 reg;
  39. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  40. reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  41. reg |= DWC3_GCTL_PRTCAPDIR(mode);
  42. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  43. }
  44. /**
  45. * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  46. * @dwc: pointer to our context structure
  47. */
  48. static int dwc3_core_soft_reset(struct dwc3 *dwc)
  49. {
  50. u32 reg;
  51. /* Before Resetting PHY, put Core in Reset */
  52. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  53. reg |= DWC3_GCTL_CORESOFTRESET;
  54. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  55. /* Assert USB3 PHY reset */
  56. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  57. reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  58. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  59. /* Assert USB2 PHY reset */
  60. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  61. reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  62. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  63. mdelay(100);
  64. /* Clear USB3 PHY reset */
  65. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  66. reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  67. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  68. /* Clear USB2 PHY reset */
  69. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  70. reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  71. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  72. mdelay(100);
  73. /* After PHYs are stable we can take Core out of reset state */
  74. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  75. reg &= ~DWC3_GCTL_CORESOFTRESET;
  76. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  77. return 0;
  78. }
  79. /**
  80. * dwc3_free_one_event_buffer - Frees one event buffer
  81. * @dwc: Pointer to our controller context structure
  82. * @evt: Pointer to event buffer to be freed
  83. */
  84. static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
  85. struct dwc3_event_buffer *evt)
  86. {
  87. dma_free_coherent(evt->buf);
  88. }
  89. /**
  90. * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
  91. * @dwc: Pointer to our controller context structure
  92. * @length: size of the event buffer
  93. *
  94. * Returns a pointer to the allocated event buffer structure on success
  95. * otherwise ERR_PTR(errno).
  96. */
  97. static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
  98. unsigned length)
  99. {
  100. struct dwc3_event_buffer *evt;
  101. evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
  102. GFP_KERNEL);
  103. if (!evt)
  104. return ERR_PTR(-ENOMEM);
  105. evt->dwc = dwc;
  106. evt->length = length;
  107. evt->buf = dma_alloc_coherent(length,
  108. (unsigned long *)&evt->dma);
  109. if (!evt->buf)
  110. return ERR_PTR(-ENOMEM);
  111. dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
  112. return evt;
  113. }
  114. /**
  115. * dwc3_free_event_buffers - frees all allocated event buffers
  116. * @dwc: Pointer to our controller context structure
  117. */
  118. static void dwc3_free_event_buffers(struct dwc3 *dwc)
  119. {
  120. struct dwc3_event_buffer *evt;
  121. int i;
  122. for (i = 0; i < dwc->num_event_buffers; i++) {
  123. evt = dwc->ev_buffs[i];
  124. if (evt)
  125. dwc3_free_one_event_buffer(dwc, evt);
  126. }
  127. }
  128. /**
  129. * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
  130. * @dwc: pointer to our controller context structure
  131. * @length: size of event buffer
  132. *
  133. * Returns 0 on success otherwise negative errno. In the error case, dwc
  134. * may contain some buffers allocated but not all which were requested.
  135. */
  136. static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
  137. {
  138. int num;
  139. int i;
  140. num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
  141. dwc->num_event_buffers = num;
  142. dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
  143. sizeof(*dwc->ev_buffs) * num);
  144. if (!dwc->ev_buffs)
  145. return -ENOMEM;
  146. for (i = 0; i < num; i++) {
  147. struct dwc3_event_buffer *evt;
  148. evt = dwc3_alloc_one_event_buffer(dwc, length);
  149. if (IS_ERR(evt)) {
  150. dev_err(dwc->dev, "can't allocate event buffer\n");
  151. return PTR_ERR(evt);
  152. }
  153. dwc->ev_buffs[i] = evt;
  154. }
  155. return 0;
  156. }
  157. /**
  158. * dwc3_event_buffers_setup - setup our allocated event buffers
  159. * @dwc: pointer to our controller context structure
  160. *
  161. * Returns 0 on success otherwise negative errno.
  162. */
  163. static int dwc3_event_buffers_setup(struct dwc3 *dwc)
  164. {
  165. struct dwc3_event_buffer *evt;
  166. int n;
  167. for (n = 0; n < dwc->num_event_buffers; n++) {
  168. evt = dwc->ev_buffs[n];
  169. dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
  170. evt->buf, (unsigned long long) evt->dma,
  171. evt->length);
  172. evt->lpos = 0;
  173. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
  174. lower_32_bits(evt->dma));
  175. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
  176. upper_32_bits(evt->dma));
  177. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
  178. DWC3_GEVNTSIZ_SIZE(evt->length));
  179. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  180. }
  181. return 0;
  182. }
  183. static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
  184. {
  185. struct dwc3_event_buffer *evt;
  186. int n;
  187. for (n = 0; n < dwc->num_event_buffers; n++) {
  188. evt = dwc->ev_buffs[n];
  189. evt->lpos = 0;
  190. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
  191. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
  192. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
  193. | DWC3_GEVNTSIZ_SIZE(0));
  194. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  195. }
  196. }
  197. static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
  198. {
  199. if (!dwc->has_hibernation)
  200. return 0;
  201. if (!dwc->nr_scratch)
  202. return 0;
  203. dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
  204. DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
  205. if (!dwc->scratchbuf)
  206. return -ENOMEM;
  207. return 0;
  208. }
  209. static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
  210. {
  211. dma_addr_t scratch_addr;
  212. u32 param;
  213. int ret;
  214. if (!dwc->has_hibernation)
  215. return 0;
  216. if (!dwc->nr_scratch)
  217. return 0;
  218. scratch_addr = dma_map_single(dwc->scratchbuf,
  219. dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  220. DMA_BIDIRECTIONAL);
  221. if (dma_mapping_error(dwc->dev, scratch_addr)) {
  222. dev_err(dwc->dev, "failed to map scratch buffer\n");
  223. ret = -EFAULT;
  224. goto err0;
  225. }
  226. dwc->scratch_addr = scratch_addr;
  227. param = lower_32_bits(scratch_addr);
  228. ret = dwc3_send_gadget_generic_command(dwc,
  229. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
  230. if (ret < 0)
  231. goto err1;
  232. param = upper_32_bits(scratch_addr);
  233. ret = dwc3_send_gadget_generic_command(dwc,
  234. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
  235. if (ret < 0)
  236. goto err1;
  237. return 0;
  238. err1:
  239. dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  240. DMA_BIDIRECTIONAL);
  241. err0:
  242. return ret;
  243. }
  244. static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
  245. {
  246. if (!dwc->has_hibernation)
  247. return;
  248. if (!dwc->nr_scratch)
  249. return;
  250. dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
  251. DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  252. kfree(dwc->scratchbuf);
  253. }
  254. static void dwc3_core_num_eps(struct dwc3 *dwc)
  255. {
  256. struct dwc3_hwparams *parms = &dwc->hwparams;
  257. dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
  258. dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
  259. dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
  260. dwc->num_in_eps, dwc->num_out_eps);
  261. }
  262. static void dwc3_cache_hwparams(struct dwc3 *dwc)
  263. {
  264. struct dwc3_hwparams *parms = &dwc->hwparams;
  265. parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
  266. parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
  267. parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
  268. parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
  269. parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
  270. parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
  271. parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
  272. parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
  273. parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
  274. }
  275. static void dwc3_hsphy_mode_setup(struct dwc3 *dwc)
  276. {
  277. enum usb_phy_interface hsphy_mode = dwc->hsphy_mode;
  278. u32 reg;
  279. /* Set dwc3 usb2 phy config */
  280. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  281. switch (hsphy_mode) {
  282. case USBPHY_INTERFACE_MODE_UTMI:
  283. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  284. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  285. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
  286. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
  287. break;
  288. case USBPHY_INTERFACE_MODE_UTMIW:
  289. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  290. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  291. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
  292. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
  293. break;
  294. default:
  295. break;
  296. }
  297. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  298. }
  299. /**
  300. * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
  301. * @dwc: Pointer to our controller context structure
  302. */
  303. static void dwc3_phy_setup(struct dwc3 *dwc)
  304. {
  305. u32 reg;
  306. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  307. /*
  308. * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
  309. * to '0' during coreConsultant configuration. So default value
  310. * will be '0' when the core is reset. Application needs to set it
  311. * to '1' after the core initialization is completed.
  312. */
  313. if (dwc->revision > DWC3_REVISION_194A)
  314. reg |= DWC3_GUSB3PIPECTL_SUSPHY;
  315. if (dwc->u2ss_inp3_quirk)
  316. reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
  317. if (dwc->req_p1p2p3_quirk)
  318. reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
  319. if (dwc->del_p1p2p3_quirk)
  320. reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
  321. if (dwc->del_phy_power_chg_quirk)
  322. reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
  323. if (dwc->lfps_filter_quirk)
  324. reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
  325. if (dwc->rx_detect_poll_quirk)
  326. reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
  327. if (dwc->tx_de_emphasis_quirk)
  328. reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
  329. if (dwc->dis_u3_susphy_quirk)
  330. reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
  331. if (dwc->dis_del_phy_power_chg_quirk)
  332. reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
  333. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  334. dwc3_hsphy_mode_setup(dwc);
  335. mdelay(100);
  336. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  337. /*
  338. * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
  339. * '0' during coreConsultant configuration. So default value will
  340. * be '0' when the core is reset. Application needs to set it to
  341. * '1' after the core initialization is completed.
  342. */
  343. if (dwc->revision > DWC3_REVISION_194A)
  344. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  345. if (dwc->dis_u2_susphy_quirk)
  346. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  347. if (dwc->dis_enblslpm_quirk)
  348. reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  349. if (dwc->dis_u2_freeclk_exists_quirk)
  350. reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
  351. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  352. mdelay(100);
  353. }
  354. /**
  355. * dwc3_core_init - Low-level initialization of DWC3 Core
  356. * @dwc: Pointer to our controller context structure
  357. *
  358. * Returns 0 on success otherwise negative errno.
  359. */
  360. static int dwc3_core_init(struct dwc3 *dwc)
  361. {
  362. unsigned long timeout;
  363. u32 hwparams4 = dwc->hwparams.hwparams4;
  364. u32 reg;
  365. int ret;
  366. reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
  367. /* This should read as U3 followed by revision number */
  368. if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
  369. dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
  370. ret = -ENODEV;
  371. goto err0;
  372. }
  373. dwc->revision = reg;
  374. /* Handle USB2.0-only core configuration */
  375. if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  376. DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
  377. if (dwc->maximum_speed == USB_SPEED_SUPER)
  378. dwc->maximum_speed = USB_SPEED_HIGH;
  379. }
  380. /* issue device SoftReset too */
  381. timeout = 5000;
  382. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
  383. while (timeout--) {
  384. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  385. if (!(reg & DWC3_DCTL_CSFTRST))
  386. break;
  387. };
  388. if (!timeout) {
  389. dev_err(dwc->dev, "Reset Timed Out\n");
  390. ret = -ETIMEDOUT;
  391. goto err0;
  392. }
  393. dwc3_phy_setup(dwc);
  394. ret = dwc3_core_soft_reset(dwc);
  395. if (ret)
  396. goto err0;
  397. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  398. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  399. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
  400. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  401. /**
  402. * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
  403. * issue which would cause xHCI compliance tests to fail.
  404. *
  405. * Because of that we cannot enable clock gating on such
  406. * configurations.
  407. *
  408. * Refers to:
  409. *
  410. * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
  411. * SOF/ITP Mode Used
  412. */
  413. if ((dwc->dr_mode == USB_DR_MODE_HOST ||
  414. dwc->dr_mode == USB_DR_MODE_OTG) &&
  415. (dwc->revision >= DWC3_REVISION_210A &&
  416. dwc->revision <= DWC3_REVISION_250A))
  417. reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
  418. else
  419. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  420. break;
  421. case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
  422. /* enable hibernation here */
  423. dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
  424. /*
  425. * REVISIT Enabling this bit so that host-mode hibernation
  426. * will work. Device-mode hibernation is not yet implemented.
  427. */
  428. reg |= DWC3_GCTL_GBLHIBERNATIONEN;
  429. break;
  430. default:
  431. dev_dbg(dwc->dev, "No power optimization available\n");
  432. }
  433. /* check if current dwc3 is on simulation board */
  434. if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
  435. dev_dbg(dwc->dev, "it is on FPGA board\n");
  436. dwc->is_fpga = true;
  437. }
  438. if(dwc->disable_scramble_quirk && !dwc->is_fpga)
  439. WARN(true,
  440. "disable_scramble cannot be used on non-FPGA builds\n");
  441. if (dwc->disable_scramble_quirk && dwc->is_fpga)
  442. reg |= DWC3_GCTL_DISSCRAMBLE;
  443. else
  444. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  445. if (dwc->u2exit_lfps_quirk)
  446. reg |= DWC3_GCTL_U2EXIT_LFPS;
  447. /*
  448. * WORKAROUND: DWC3 revisions <1.90a have a bug
  449. * where the device can fail to connect at SuperSpeed
  450. * and falls back to high-speed mode which causes
  451. * the device to enter a Connect/Disconnect loop
  452. */
  453. if (dwc->revision < DWC3_REVISION_190A)
  454. reg |= DWC3_GCTL_U2RSTECN;
  455. dwc3_core_num_eps(dwc);
  456. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  457. ret = dwc3_alloc_scratch_buffers(dwc);
  458. if (ret)
  459. goto err0;
  460. ret = dwc3_setup_scratch_buffers(dwc);
  461. if (ret)
  462. goto err1;
  463. return 0;
  464. err1:
  465. dwc3_free_scratch_buffers(dwc);
  466. err0:
  467. return ret;
  468. }
  469. static void dwc3_core_exit(struct dwc3 *dwc)
  470. {
  471. dwc3_free_scratch_buffers(dwc);
  472. }
  473. static int dwc3_core_init_mode(struct dwc3 *dwc)
  474. {
  475. int ret;
  476. switch (dwc->dr_mode) {
  477. case USB_DR_MODE_PERIPHERAL:
  478. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  479. ret = dwc3_gadget_init(dwc);
  480. if (ret) {
  481. dev_err(dwc->dev, "failed to initialize gadget\n");
  482. return ret;
  483. }
  484. break;
  485. case USB_DR_MODE_HOST:
  486. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
  487. ret = dwc3_host_init(dwc);
  488. if (ret) {
  489. dev_err(dwc->dev, "failed to initialize host\n");
  490. return ret;
  491. }
  492. break;
  493. case USB_DR_MODE_OTG:
  494. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  495. ret = dwc3_host_init(dwc);
  496. if (ret) {
  497. dev_err(dwc->dev, "failed to initialize host\n");
  498. return ret;
  499. }
  500. ret = dwc3_gadget_init(dwc);
  501. if (ret) {
  502. dev_err(dwc->dev, "failed to initialize gadget\n");
  503. return ret;
  504. }
  505. break;
  506. default:
  507. dev_err(dwc->dev,
  508. "Unsupported mode of operation %d\n", dwc->dr_mode);
  509. return -EINVAL;
  510. }
  511. return 0;
  512. }
  513. static void dwc3_gadget_run(struct dwc3 *dwc)
  514. {
  515. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
  516. mdelay(100);
  517. }
  518. static void dwc3_core_exit_mode(struct dwc3 *dwc)
  519. {
  520. switch (dwc->dr_mode) {
  521. case USB_DR_MODE_PERIPHERAL:
  522. dwc3_gadget_exit(dwc);
  523. break;
  524. case USB_DR_MODE_HOST:
  525. dwc3_host_exit(dwc);
  526. break;
  527. case USB_DR_MODE_OTG:
  528. dwc3_host_exit(dwc);
  529. dwc3_gadget_exit(dwc);
  530. break;
  531. default:
  532. /* do nothing */
  533. break;
  534. }
  535. /*
  536. * switch back to peripheral mode
  537. * This enables the phy to enter idle and then, if enabled, suspend.
  538. */
  539. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  540. dwc3_gadget_run(dwc);
  541. }
  542. #define DWC3_ALIGN_MASK (16 - 1)
  543. /**
  544. * dwc3_uboot_init - dwc3 core uboot initialization code
  545. * @dwc3_dev: struct dwc3_device containing initialization data
  546. *
  547. * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
  548. * kernel driver). Pointer to dwc3_device should be passed containing
  549. * base address and other initialization data. Returns '0' on success and
  550. * a negative value on failure.
  551. *
  552. * Generally called from board_usb_init() implemented in board file.
  553. */
  554. int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
  555. {
  556. struct dwc3 *dwc;
  557. struct device *dev = NULL;
  558. u8 lpm_nyet_threshold;
  559. u8 tx_de_emphasis;
  560. u8 hird_threshold;
  561. int ret;
  562. void *mem;
  563. mem = devm_kzalloc((struct udevice *)dev,
  564. sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
  565. if (!mem)
  566. return -ENOMEM;
  567. dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
  568. dwc->mem = mem;
  569. dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
  570. DWC3_GLOBALS_REGS_START);
  571. /* default to highest possible threshold */
  572. lpm_nyet_threshold = 0xff;
  573. /* default to -3.5dB de-emphasis */
  574. tx_de_emphasis = 1;
  575. /*
  576. * default to assert utmi_sleep_n and use maximum allowed HIRD
  577. * threshold value of 0b1100
  578. */
  579. hird_threshold = 12;
  580. dwc->maximum_speed = dwc3_dev->maximum_speed;
  581. dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
  582. if (dwc3_dev->lpm_nyet_threshold)
  583. lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
  584. dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
  585. if (dwc3_dev->hird_threshold)
  586. hird_threshold = dwc3_dev->hird_threshold;
  587. dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
  588. dwc->dr_mode = dwc3_dev->dr_mode;
  589. dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
  590. dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
  591. dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
  592. dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
  593. dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
  594. dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
  595. dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
  596. dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
  597. dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
  598. dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
  599. dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
  600. dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk;
  601. dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
  602. dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
  603. dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
  604. if (dwc3_dev->tx_de_emphasis)
  605. tx_de_emphasis = dwc3_dev->tx_de_emphasis;
  606. /* default to superspeed if no maximum_speed passed */
  607. if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
  608. dwc->maximum_speed = USB_SPEED_SUPER;
  609. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  610. dwc->tx_de_emphasis = tx_de_emphasis;
  611. dwc->hird_threshold = hird_threshold
  612. | (dwc->is_utmi_l1_suspend << 4);
  613. dwc->hsphy_mode = dwc3_dev->hsphy_mode;
  614. dwc->index = dwc3_dev->index;
  615. dwc3_cache_hwparams(dwc);
  616. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  617. if (ret) {
  618. dev_err(dwc->dev, "failed to allocate event buffers\n");
  619. return -ENOMEM;
  620. }
  621. if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  622. dwc->dr_mode = USB_DR_MODE_HOST;
  623. else if (!IS_ENABLED(CONFIG_USB_HOST))
  624. dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
  625. if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  626. dwc->dr_mode = USB_DR_MODE_OTG;
  627. ret = dwc3_core_init(dwc);
  628. if (ret) {
  629. dev_err(dwc->dev, "failed to initialize core\n");
  630. goto err0;
  631. }
  632. ret = dwc3_event_buffers_setup(dwc);
  633. if (ret) {
  634. dev_err(dwc->dev, "failed to setup event buffers\n");
  635. goto err1;
  636. }
  637. ret = dwc3_core_init_mode(dwc);
  638. if (ret)
  639. goto err2;
  640. list_add_tail(&dwc->list, &dwc3_list);
  641. return 0;
  642. err2:
  643. dwc3_event_buffers_cleanup(dwc);
  644. err1:
  645. dwc3_core_exit(dwc);
  646. err0:
  647. dwc3_free_event_buffers(dwc);
  648. return ret;
  649. }
  650. /**
  651. * dwc3_uboot_exit - dwc3 core uboot cleanup code
  652. * @index: index of this controller
  653. *
  654. * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
  655. * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
  656. * should be passed and should match with the index passed in
  657. * dwc3_device during init.
  658. *
  659. * Generally called from board file.
  660. */
  661. void dwc3_uboot_exit(int index)
  662. {
  663. struct dwc3 *dwc;
  664. list_for_each_entry(dwc, &dwc3_list, list) {
  665. if (dwc->index != index)
  666. continue;
  667. dwc3_core_exit_mode(dwc);
  668. dwc3_event_buffers_cleanup(dwc);
  669. dwc3_free_event_buffers(dwc);
  670. dwc3_core_exit(dwc);
  671. list_del(&dwc->list);
  672. kfree(dwc->mem);
  673. break;
  674. }
  675. }
  676. /**
  677. * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
  678. * @index: index of this controller
  679. *
  680. * Invokes dwc3 gadget interrupts.
  681. *
  682. * Generally called from board file.
  683. */
  684. void dwc3_uboot_handle_interrupt(int index)
  685. {
  686. struct dwc3 *dwc = NULL;
  687. list_for_each_entry(dwc, &dwc3_list, list) {
  688. if (dwc->index != index)
  689. continue;
  690. dwc3_gadget_uboot_handle_interrupt(dwc);
  691. break;
  692. }
  693. }
  694. MODULE_ALIAS("platform:dwc3");
  695. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  696. MODULE_LICENSE("GPL v2");
  697. MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
  698. #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
  699. int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
  700. {
  701. int ret;
  702. ret = generic_phy_get_bulk(dev, phys);
  703. if (ret)
  704. return ret;
  705. ret = generic_phy_init_bulk(phys);
  706. if (ret)
  707. return ret;
  708. ret = generic_phy_power_on_bulk(phys);
  709. if (ret)
  710. generic_phy_exit_bulk(phys);
  711. return ret;
  712. }
  713. int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
  714. {
  715. int ret;
  716. ret = generic_phy_power_off_bulk(phys);
  717. ret |= generic_phy_exit_bulk(phys);
  718. return ret;
  719. }
  720. #endif
  721. #if CONFIG_IS_ENABLED(DM_USB)
  722. void dwc3_of_parse(struct dwc3 *dwc)
  723. {
  724. const u8 *tmp;
  725. struct udevice *dev = dwc->dev;
  726. u8 lpm_nyet_threshold;
  727. u8 tx_de_emphasis;
  728. u8 hird_threshold;
  729. /* default to highest possible threshold */
  730. lpm_nyet_threshold = 0xff;
  731. /* default to -3.5dB de-emphasis */
  732. tx_de_emphasis = 1;
  733. /*
  734. * default to assert utmi_sleep_n and use maximum allowed HIRD
  735. * threshold value of 0b1100
  736. */
  737. hird_threshold = 12;
  738. dwc->hsphy_mode = usb_get_phy_mode(dev_ofnode(dev));
  739. dwc->has_lpm_erratum = dev_read_bool(dev,
  740. "snps,has-lpm-erratum");
  741. tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
  742. if (tmp)
  743. lpm_nyet_threshold = *tmp;
  744. dwc->is_utmi_l1_suspend = dev_read_bool(dev,
  745. "snps,is-utmi-l1-suspend");
  746. tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
  747. if (tmp)
  748. hird_threshold = *tmp;
  749. dwc->disable_scramble_quirk = dev_read_bool(dev,
  750. "snps,disable_scramble_quirk");
  751. dwc->u2exit_lfps_quirk = dev_read_bool(dev,
  752. "snps,u2exit_lfps_quirk");
  753. dwc->u2ss_inp3_quirk = dev_read_bool(dev,
  754. "snps,u2ss_inp3_quirk");
  755. dwc->req_p1p2p3_quirk = dev_read_bool(dev,
  756. "snps,req_p1p2p3_quirk");
  757. dwc->del_p1p2p3_quirk = dev_read_bool(dev,
  758. "snps,del_p1p2p3_quirk");
  759. dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
  760. "snps,del_phy_power_chg_quirk");
  761. dwc->lfps_filter_quirk = dev_read_bool(dev,
  762. "snps,lfps_filter_quirk");
  763. dwc->rx_detect_poll_quirk = dev_read_bool(dev,
  764. "snps,rx_detect_poll_quirk");
  765. dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
  766. "snps,dis_u3_susphy_quirk");
  767. dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
  768. "snps,dis_u2_susphy_quirk");
  769. dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
  770. "snps,dis-del-phy-power-chg-quirk");
  771. dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev,
  772. "snps,dis-tx-ipgap-linecheck-quirk");
  773. dwc->dis_enblslpm_quirk = dev_read_bool(dev,
  774. "snps,dis_enblslpm_quirk");
  775. dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
  776. "snps,dis-u2-freeclk-exists-quirk");
  777. dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
  778. "snps,tx_de_emphasis_quirk");
  779. tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
  780. if (tmp)
  781. tx_de_emphasis = *tmp;
  782. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  783. dwc->tx_de_emphasis = tx_de_emphasis;
  784. dwc->hird_threshold = hird_threshold
  785. | (dwc->is_utmi_l1_suspend << 4);
  786. }
  787. int dwc3_init(struct dwc3 *dwc)
  788. {
  789. int ret;
  790. u32 reg;
  791. dwc3_cache_hwparams(dwc);
  792. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  793. if (ret) {
  794. dev_err(dwc->dev, "failed to allocate event buffers\n");
  795. return -ENOMEM;
  796. }
  797. ret = dwc3_core_init(dwc);
  798. if (ret) {
  799. dev_err(dwc->dev, "failed to initialize core\n");
  800. goto core_fail;
  801. }
  802. ret = dwc3_event_buffers_setup(dwc);
  803. if (ret) {
  804. dev_err(dwc->dev, "failed to setup event buffers\n");
  805. goto event_fail;
  806. }
  807. if (dwc->revision >= DWC3_REVISION_250A) {
  808. reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
  809. /*
  810. * Enable hardware control of sending remote wakeup
  811. * in HS when the device is in the L1 state.
  812. */
  813. if (dwc->revision >= DWC3_REVISION_290A)
  814. reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
  815. if (dwc->dis_tx_ipgap_linecheck_quirk)
  816. reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
  817. dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
  818. }
  819. if (dwc->dr_mode == USB_DR_MODE_HOST ||
  820. dwc->dr_mode == USB_DR_MODE_OTG) {
  821. reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
  822. reg |= DWC3_GUCTL_HSTINAUTORETRY;
  823. dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
  824. }
  825. ret = dwc3_core_init_mode(dwc);
  826. if (ret)
  827. goto mode_fail;
  828. return 0;
  829. mode_fail:
  830. dwc3_event_buffers_cleanup(dwc);
  831. event_fail:
  832. dwc3_core_exit(dwc);
  833. core_fail:
  834. dwc3_free_event_buffers(dwc);
  835. return ret;
  836. }
  837. void dwc3_remove(struct dwc3 *dwc)
  838. {
  839. dwc3_core_exit_mode(dwc);
  840. dwc3_event_buffers_cleanup(dwc);
  841. dwc3_free_event_buffers(dwc);
  842. dwc3_core_exit(dwc);
  843. kfree(dwc->mem);
  844. }
  845. #endif