fsl_dspi.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2003
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
  7. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  8. * Chao Fu (B44548@freescale.com)
  9. * Haikun Wang (B53464@freescale.com)
  10. */
  11. #include <linux/math64.h>
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <errno.h>
  15. #include <common.h>
  16. #include <log.h>
  17. #include <spi.h>
  18. #include <malloc.h>
  19. #include <asm/io.h>
  20. #include <fdtdec.h>
  21. #ifndef CONFIG_M68K
  22. #include <asm/arch/clock.h>
  23. #endif
  24. #include <fsl_dspi.h>
  25. #include <linux/bitops.h>
  26. #include <linux/delay.h>
  27. /* linux/include/time.h */
  28. #define NSEC_PER_SEC 1000000000L
  29. DECLARE_GLOBAL_DATA_PTR;
  30. /* fsl_dspi_plat flags */
  31. #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
  32. /* idle data value */
  33. #define DSPI_IDLE_VAL 0x0
  34. /* max chipselect signals number */
  35. #define FSL_DSPI_MAX_CHIPSELECT 6
  36. /* default SCK frequency, unit: HZ */
  37. #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
  38. /* tx/rx data wait timeout value, unit: us */
  39. #define DSPI_TXRX_WAIT_TIMEOUT 1000000
  40. /* CTAR register pre-configure value */
  41. #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
  42. DSPI_CTAR_PCSSCK_1CLK | \
  43. DSPI_CTAR_PASC(0) | \
  44. DSPI_CTAR_PDT(0) | \
  45. DSPI_CTAR_CSSCK(0) | \
  46. DSPI_CTAR_ASC(0) | \
  47. DSPI_CTAR_DT(0))
  48. /* CTAR register pre-configure mask */
  49. #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
  50. DSPI_CTAR_PCSSCK(3) | \
  51. DSPI_CTAR_PASC(3) | \
  52. DSPI_CTAR_PDT(3) | \
  53. DSPI_CTAR_CSSCK(15) | \
  54. DSPI_CTAR_ASC(15) | \
  55. DSPI_CTAR_DT(15))
  56. /**
  57. * struct fsl_dspi_plat - platform data for Freescale DSPI
  58. *
  59. * @flags: Flags for DSPI DSPI_FLAG_...
  60. * @speed_hz: Default SCK frequency
  61. * @num_chipselect: Number of DSPI chipselect signals
  62. * @regs_addr: Base address of DSPI registers
  63. */
  64. struct fsl_dspi_plat {
  65. uint flags;
  66. uint speed_hz;
  67. uint num_chipselect;
  68. fdt_addr_t regs_addr;
  69. };
  70. /**
  71. * struct fsl_dspi_priv - private data for Freescale DSPI
  72. *
  73. * @flags: Flags for DSPI DSPI_FLAG_...
  74. * @mode: SPI mode to use for slave device (see SPI mode flags)
  75. * @mcr_val: MCR register configure value
  76. * @bus_clk: DSPI input clk frequency
  77. * @speed_hz: Default SCK frequency
  78. * @charbit: How many bits in every transfer
  79. * @num_chipselect: Number of DSPI chipselect signals
  80. * @ctar_val: CTAR register configure value of per chipselect slave device
  81. * @regs: Point to DSPI register structure for I/O access
  82. */
  83. struct fsl_dspi_priv {
  84. uint flags;
  85. uint mode;
  86. uint mcr_val;
  87. uint bus_clk;
  88. uint speed_hz;
  89. uint charbit;
  90. uint num_chipselect;
  91. uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
  92. struct dspi *regs;
  93. };
  94. __weak void cpu_dspi_port_conf(void)
  95. {
  96. }
  97. __weak int cpu_dspi_claim_bus(uint bus, uint cs)
  98. {
  99. return 0;
  100. }
  101. __weak void cpu_dspi_release_bus(uint bus, uint cs)
  102. {
  103. }
  104. static uint dspi_read32(uint flags, uint *addr)
  105. {
  106. return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
  107. in_be32(addr) : in_le32(addr);
  108. }
  109. static void dspi_write32(uint flags, uint *addr, uint val)
  110. {
  111. flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
  112. out_be32(addr, val) : out_le32(addr, val);
  113. }
  114. static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
  115. {
  116. uint mcr_val;
  117. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  118. if (halt)
  119. mcr_val |= DSPI_MCR_HALT;
  120. else
  121. mcr_val &= ~DSPI_MCR_HALT;
  122. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  123. }
  124. static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
  125. {
  126. /* halt DSPI module */
  127. dspi_halt(priv, 1);
  128. dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
  129. /* resume module */
  130. dspi_halt(priv, 0);
  131. priv->mcr_val = cfg_val;
  132. }
  133. static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
  134. uint cs, uint state)
  135. {
  136. uint mcr_val;
  137. dspi_halt(priv, 1);
  138. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  139. if (state & SPI_CS_HIGH)
  140. /* CSx inactive state is low */
  141. mcr_val &= ~DSPI_MCR_PCSIS(cs);
  142. else
  143. /* CSx inactive state is high */
  144. mcr_val |= DSPI_MCR_PCSIS(cs);
  145. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  146. dspi_halt(priv, 0);
  147. }
  148. static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
  149. uint cs, uint mode)
  150. {
  151. uint bus_setup;
  152. bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
  153. bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
  154. bus_setup |= priv->ctar_val[cs];
  155. bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
  156. if (mode & SPI_CPOL)
  157. bus_setup |= DSPI_CTAR_CPOL;
  158. if (mode & SPI_CPHA)
  159. bus_setup |= DSPI_CTAR_CPHA;
  160. if (mode & SPI_LSB_FIRST)
  161. bus_setup |= DSPI_CTAR_LSBFE;
  162. dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
  163. priv->charbit =
  164. ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
  165. DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
  166. return 0;
  167. }
  168. static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
  169. {
  170. uint mcr_val;
  171. dspi_halt(priv, 1);
  172. mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
  173. /* flush RX and TX FIFO */
  174. mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  175. dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
  176. dspi_halt(priv, 0);
  177. }
  178. static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
  179. {
  180. int timeout = DSPI_TXRX_WAIT_TIMEOUT;
  181. /* wait for empty entries in TXFIFO or timeout */
  182. while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
  183. timeout--)
  184. udelay(1);
  185. if (timeout >= 0)
  186. dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
  187. else
  188. debug("dspi_tx: waiting timeout!\n");
  189. }
  190. static u16 dspi_rx(struct fsl_dspi_priv *priv)
  191. {
  192. int timeout = DSPI_TXRX_WAIT_TIMEOUT;
  193. /* wait for valid entries in RXFIFO or timeout */
  194. while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
  195. timeout--)
  196. udelay(1);
  197. if (timeout >= 0)
  198. return (u16)DSPI_RFR_RXDATA(
  199. dspi_read32(priv->flags, &priv->regs->rfr));
  200. else {
  201. debug("dspi_rx: waiting timeout!\n");
  202. return (u16)(~0);
  203. }
  204. }
  205. static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
  206. const void *dout, void *din, unsigned long flags)
  207. {
  208. u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
  209. u8 *spi_rd = NULL, *spi_wr = NULL;
  210. static u32 ctrl;
  211. uint len = bitlen >> 3;
  212. if (priv->charbit == 16) {
  213. bitlen >>= 1;
  214. spi_wr16 = (u16 *)dout;
  215. spi_rd16 = (u16 *)din;
  216. } else {
  217. spi_wr = (u8 *)dout;
  218. spi_rd = (u8 *)din;
  219. }
  220. if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
  221. ctrl |= DSPI_TFR_CONT;
  222. ctrl = ctrl & DSPI_TFR_CONT;
  223. ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
  224. if (len > 1) {
  225. int tmp_len = len - 1;
  226. while (tmp_len--) {
  227. if ((dout != NULL) && (din != NULL)) {
  228. if (priv->charbit == 16) {
  229. dspi_tx(priv, ctrl, *spi_wr16++);
  230. *spi_rd16++ = dspi_rx(priv);
  231. }
  232. else {
  233. dspi_tx(priv, ctrl, *spi_wr++);
  234. *spi_rd++ = dspi_rx(priv);
  235. }
  236. }
  237. else if (dout != NULL) {
  238. if (priv->charbit == 16)
  239. dspi_tx(priv, ctrl, *spi_wr16++);
  240. else
  241. dspi_tx(priv, ctrl, *spi_wr++);
  242. dspi_rx(priv);
  243. }
  244. else if (din != NULL) {
  245. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  246. if (priv->charbit == 16)
  247. *spi_rd16++ = dspi_rx(priv);
  248. else
  249. *spi_rd++ = dspi_rx(priv);
  250. }
  251. }
  252. len = 1; /* remaining byte */
  253. }
  254. if ((flags & SPI_XFER_END) == SPI_XFER_END)
  255. ctrl &= ~DSPI_TFR_CONT;
  256. if (len) {
  257. if ((dout != NULL) && (din != NULL)) {
  258. if (priv->charbit == 16) {
  259. dspi_tx(priv, ctrl, *spi_wr16++);
  260. *spi_rd16++ = dspi_rx(priv);
  261. }
  262. else {
  263. dspi_tx(priv, ctrl, *spi_wr++);
  264. *spi_rd++ = dspi_rx(priv);
  265. }
  266. }
  267. else if (dout != NULL) {
  268. if (priv->charbit == 16)
  269. dspi_tx(priv, ctrl, *spi_wr16);
  270. else
  271. dspi_tx(priv, ctrl, *spi_wr);
  272. dspi_rx(priv);
  273. }
  274. else if (din != NULL) {
  275. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  276. if (priv->charbit == 16)
  277. *spi_rd16 = dspi_rx(priv);
  278. else
  279. *spi_rd = dspi_rx(priv);
  280. }
  281. } else {
  282. /* dummy read */
  283. dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
  284. dspi_rx(priv);
  285. }
  286. return 0;
  287. }
  288. /**
  289. * Calculate the divide value between input clk frequency and expected SCK frequency
  290. * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
  291. * Dbr: use default value 0
  292. *
  293. * @pbr: return Baud Rate Prescaler value
  294. * @br: return Baud Rate Scaler value
  295. * @speed_hz: expected SCK frequency
  296. * @clkrate: input clk frequency
  297. */
  298. static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
  299. int speed_hz, uint clkrate)
  300. {
  301. /* Valid baud rate pre-scaler values */
  302. int pbr_tbl[4] = {2, 3, 5, 7};
  303. int brs[16] = {2, 4, 6, 8,
  304. 16, 32, 64, 128,
  305. 256, 512, 1024, 2048,
  306. 4096, 8192, 16384, 32768};
  307. int temp, i = 0, j = 0;
  308. temp = clkrate / speed_hz;
  309. for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
  310. for (j = 0; j < ARRAY_SIZE(brs); j++) {
  311. if (pbr_tbl[i] * brs[j] >= temp) {
  312. *pbr = i;
  313. *br = j;
  314. return 0;
  315. }
  316. }
  317. debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
  318. debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
  319. *pbr = ARRAY_SIZE(pbr_tbl) - 1;
  320. *br = ARRAY_SIZE(brs) - 1;
  321. return -EINVAL;
  322. }
  323. static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
  324. unsigned long clkrate)
  325. {
  326. int scale_needed, scale, minscale = INT_MAX;
  327. int pscale_tbl[4] = {1, 3, 5, 7};
  328. u32 remainder;
  329. int i, j;
  330. scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
  331. &remainder);
  332. if (remainder)
  333. scale_needed++;
  334. for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
  335. for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
  336. scale = pscale_tbl[i] * (2 << j);
  337. if (scale >= scale_needed) {
  338. if (scale < minscale) {
  339. minscale = scale;
  340. *psc = i;
  341. *sc = j;
  342. }
  343. break;
  344. }
  345. }
  346. if (minscale == INT_MAX) {
  347. pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
  348. delay_ns, clkrate);
  349. *psc = ARRAY_SIZE(pscale_tbl) - 1;
  350. *sc = DSPI_CTAR_SCALE_BITS;
  351. }
  352. }
  353. static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
  354. {
  355. int ret;
  356. uint bus_setup;
  357. int best_i, best_j, bus_clk;
  358. bus_clk = priv->bus_clk;
  359. debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
  360. speed, bus_clk);
  361. bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
  362. bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
  363. ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
  364. if (ret) {
  365. speed = priv->speed_hz;
  366. debug("DSPI set_speed use default SCK rate %u.\n", speed);
  367. fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
  368. }
  369. bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
  370. dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
  371. priv->speed_hz = speed;
  372. return 0;
  373. }
  374. static int fsl_dspi_child_pre_probe(struct udevice *dev)
  375. {
  376. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  377. struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
  378. u32 cs_sck_delay = 0, sck_cs_delay = 0;
  379. unsigned char pcssck = 0, cssck = 0;
  380. unsigned char pasc = 0, asc = 0;
  381. if (slave_plat->cs >= priv->num_chipselect) {
  382. debug("DSPI invalid chipselect number %d(max %d)!\n",
  383. slave_plat->cs, priv->num_chipselect - 1);
  384. return -EINVAL;
  385. }
  386. ofnode_read_u32(dev_ofnode(dev), "fsl,spi-cs-sck-delay",
  387. &cs_sck_delay);
  388. ofnode_read_u32(dev_ofnode(dev), "fsl,spi-sck-cs-delay",
  389. &sck_cs_delay);
  390. /* Set PCS to SCK delay scale values */
  391. ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
  392. /* Set After SCK delay scale values */
  393. ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
  394. priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
  395. DSPI_CTAR_PCSSCK(pcssck) |
  396. DSPI_CTAR_PASC(pasc);
  397. debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
  398. slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
  399. return 0;
  400. }
  401. static int fsl_dspi_probe(struct udevice *bus)
  402. {
  403. struct fsl_dspi_plat *plat = dev_get_plat(bus);
  404. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  405. struct dm_spi_bus *dm_spi_bus;
  406. uint mcr_cfg_val;
  407. dm_spi_bus = dev_get_uclass_priv(bus);
  408. /* cpu speical pin muxing configure */
  409. cpu_dspi_port_conf();
  410. /* get input clk frequency */
  411. priv->regs = (struct dspi *)plat->regs_addr;
  412. priv->flags = plat->flags;
  413. #ifdef CONFIG_M68K
  414. priv->bus_clk = gd->bus_clk;
  415. #else
  416. priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
  417. #endif
  418. priv->num_chipselect = plat->num_chipselect;
  419. priv->speed_hz = plat->speed_hz;
  420. /* frame data length in bits, default 8bits */
  421. priv->charbit = 8;
  422. dm_spi_bus->max_hz = plat->speed_hz;
  423. /* default: all CS signals inactive state is high */
  424. mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
  425. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  426. fsl_dspi_init_mcr(priv, mcr_cfg_val);
  427. debug("%s probe done, bus-num %d.\n", bus->name, dev_seq(bus));
  428. return 0;
  429. }
  430. static int fsl_dspi_claim_bus(struct udevice *dev)
  431. {
  432. uint sr_val;
  433. struct fsl_dspi_priv *priv;
  434. struct udevice *bus = dev->parent;
  435. struct dm_spi_slave_plat *slave_plat =
  436. dev_get_parent_plat(dev);
  437. priv = dev_get_priv(bus);
  438. /* processor special preparation work */
  439. cpu_dspi_claim_bus(dev_seq(bus), slave_plat->cs);
  440. /* configure transfer mode */
  441. fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
  442. /* configure active state of CSX */
  443. fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
  444. priv->mode);
  445. fsl_dspi_clr_fifo(priv);
  446. /* check module TX and RX status */
  447. sr_val = dspi_read32(priv->flags, &priv->regs->sr);
  448. if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
  449. debug("DSPI RX/TX not ready!\n");
  450. return -EIO;
  451. }
  452. return 0;
  453. }
  454. static int fsl_dspi_release_bus(struct udevice *dev)
  455. {
  456. struct udevice *bus = dev->parent;
  457. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  458. struct dm_spi_slave_plat *slave_plat =
  459. dev_get_parent_plat(dev);
  460. /* halt module */
  461. dspi_halt(priv, 1);
  462. /* processor special release work */
  463. cpu_dspi_release_bus(dev_seq(bus), slave_plat->cs);
  464. return 0;
  465. }
  466. /**
  467. * This function doesn't do anything except help with debugging
  468. */
  469. static int fsl_dspi_bind(struct udevice *bus)
  470. {
  471. debug("%s assigned seq %d.\n", bus->name, dev_seq(bus));
  472. return 0;
  473. }
  474. static int fsl_dspi_of_to_plat(struct udevice *bus)
  475. {
  476. fdt_addr_t addr;
  477. struct fsl_dspi_plat *plat = dev_get_plat(bus);
  478. const void *blob = gd->fdt_blob;
  479. int node = dev_of_offset(bus);
  480. if (fdtdec_get_bool(blob, node, "big-endian"))
  481. plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
  482. plat->num_chipselect =
  483. fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
  484. addr = dev_read_addr(bus);
  485. if (addr == FDT_ADDR_T_NONE) {
  486. debug("DSPI: Can't get base address or size\n");
  487. return -ENOMEM;
  488. }
  489. plat->regs_addr = addr;
  490. plat->speed_hz = fdtdec_get_int(blob,
  491. node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
  492. debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
  493. &plat->regs_addr, plat->speed_hz,
  494. plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
  495. plat->num_chipselect);
  496. return 0;
  497. }
  498. static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
  499. const void *dout, void *din, unsigned long flags)
  500. {
  501. struct fsl_dspi_priv *priv;
  502. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  503. struct udevice *bus;
  504. bus = dev->parent;
  505. priv = dev_get_priv(bus);
  506. return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
  507. }
  508. static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
  509. {
  510. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  511. return fsl_dspi_cfg_speed(priv, speed);
  512. }
  513. static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
  514. {
  515. struct fsl_dspi_priv *priv = dev_get_priv(bus);
  516. debug("DSPI set_mode: mode 0x%x.\n", mode);
  517. /*
  518. * We store some chipselect special configure value in priv->ctar_val,
  519. * and we can't get the correct chipselect number here,
  520. * so just store mode value.
  521. * Do really configuration when claim_bus.
  522. */
  523. priv->mode = mode;
  524. return 0;
  525. }
  526. static const struct dm_spi_ops fsl_dspi_ops = {
  527. .claim_bus = fsl_dspi_claim_bus,
  528. .release_bus = fsl_dspi_release_bus,
  529. .xfer = fsl_dspi_xfer,
  530. .set_speed = fsl_dspi_set_speed,
  531. .set_mode = fsl_dspi_set_mode,
  532. };
  533. static const struct udevice_id fsl_dspi_ids[] = {
  534. { .compatible = "fsl,vf610-dspi" },
  535. { }
  536. };
  537. U_BOOT_DRIVER(fsl_dspi) = {
  538. .name = "fsl_dspi",
  539. .id = UCLASS_SPI,
  540. .of_match = fsl_dspi_ids,
  541. .ops = &fsl_dspi_ops,
  542. .of_to_plat = fsl_dspi_of_to_plat,
  543. .plat_auto = sizeof(struct fsl_dspi_plat),
  544. .priv_auto = sizeof(struct fsl_dspi_priv),
  545. .probe = fsl_dspi_probe,
  546. .child_pre_probe = fsl_dspi_child_pre_probe,
  547. .bind = fsl_dspi_bind,
  548. };