pbias_regulator.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
  4. * Jean-Jacques Hiblot <jjhiblot@ti.com>
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <linux/delay.h>
  11. #include <linux/err.h>
  12. #include <power/pmic.h>
  13. #include <power/regulator.h>
  14. #include <regmap.h>
  15. #include <syscon.h>
  16. #include <linux/bitops.h>
  17. #include <linux/ioport.h>
  18. #include <dm/device-internal.h>
  19. #include <dm/read.h>
  20. #ifdef CONFIG_MMC_OMAP36XX_PINS
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/io.h>
  23. #include <asm/arch/mux.h>
  24. #endif
  25. struct pbias_reg_info {
  26. u32 enable;
  27. u32 enable_mask;
  28. u32 disable_val;
  29. u32 vmode;
  30. unsigned int enable_time;
  31. char *name;
  32. };
  33. struct pbias_priv {
  34. struct regmap *regmap;
  35. int offset;
  36. };
  37. static const struct pmic_child_info pmic_children_info[] = {
  38. { .prefix = "pbias", .driver = "pbias_regulator"},
  39. { },
  40. };
  41. static int pbias_write(struct udevice *dev, uint reg, const uint8_t *buff,
  42. int len)
  43. {
  44. struct pbias_priv *priv = dev_get_priv(dev);
  45. u32 val = *(u32 *)buff;
  46. if (len != 4)
  47. return -EINVAL;
  48. return regmap_write(priv->regmap, priv->offset, val);
  49. }
  50. static int pbias_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
  51. {
  52. struct pbias_priv *priv = dev_get_priv(dev);
  53. if (len != 4)
  54. return -EINVAL;
  55. return regmap_read(priv->regmap, priv->offset, (u32 *)buff);
  56. }
  57. static int pbias_of_to_plat(struct udevice *dev)
  58. {
  59. struct pbias_priv *priv = dev_get_priv(dev);
  60. struct udevice *syscon;
  61. struct regmap *regmap;
  62. struct resource res;
  63. int err;
  64. err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  65. "syscon", &syscon);
  66. if (err) {
  67. pr_err("%s: unable to find syscon device (%d)\n", __func__,
  68. err);
  69. return err;
  70. }
  71. regmap = syscon_get_regmap(syscon);
  72. if (IS_ERR(regmap)) {
  73. pr_err("%s: unable to find regmap (%ld)\n", __func__,
  74. PTR_ERR(regmap));
  75. return PTR_ERR(regmap);
  76. }
  77. priv->regmap = regmap;
  78. err = dev_read_resource(dev, 0, &res);
  79. if (err) {
  80. pr_err("%s: unable to find offset (%d)\n", __func__, err);
  81. return err;
  82. }
  83. priv->offset = res.start;
  84. return 0;
  85. }
  86. static int pbias_bind(struct udevice *dev)
  87. {
  88. int children;
  89. children = pmic_bind_children(dev, dev_ofnode(dev),
  90. pmic_children_info);
  91. if (!children)
  92. debug("%s: %s - no child found\n", __func__, dev->name);
  93. return 0;
  94. }
  95. static struct dm_pmic_ops pbias_ops = {
  96. .read = pbias_read,
  97. .write = pbias_write,
  98. };
  99. static const struct udevice_id pbias_ids[] = {
  100. { .compatible = "ti,pbias-dra7" },
  101. { .compatible = "ti,pbias-omap2" },
  102. { .compatible = "ti,pbias-omap3" },
  103. { .compatible = "ti,pbias-omap4" },
  104. { .compatible = "ti,pbias-omap5" },
  105. { }
  106. };
  107. U_BOOT_DRIVER(pbias_pmic) = {
  108. .name = "pbias_pmic",
  109. .id = UCLASS_PMIC,
  110. .of_match = pbias_ids,
  111. .bind = pbias_bind,
  112. .ops = &pbias_ops,
  113. .of_to_plat = pbias_of_to_plat,
  114. .priv_auto = sizeof(struct pbias_priv),
  115. };
  116. static const struct pbias_reg_info pbias_mmc_omap2430 = {
  117. .enable = BIT(1),
  118. .enable_mask = BIT(1),
  119. .vmode = BIT(0),
  120. .disable_val = 0,
  121. .enable_time = 100,
  122. .name = "pbias_mmc_omap2430"
  123. };
  124. static const struct pbias_reg_info pbias_sim_omap3 = {
  125. .enable = BIT(9),
  126. .enable_mask = BIT(9),
  127. .vmode = BIT(8),
  128. .enable_time = 100,
  129. .name = "pbias_sim_omap3"
  130. };
  131. static const struct pbias_reg_info pbias_mmc_omap4 = {
  132. .enable = BIT(26) | BIT(22),
  133. .enable_mask = BIT(26) | BIT(25) | BIT(22),
  134. .disable_val = BIT(25),
  135. .vmode = BIT(21),
  136. .enable_time = 100,
  137. .name = "pbias_mmc_omap4"
  138. };
  139. static const struct pbias_reg_info pbias_mmc_omap5 = {
  140. .enable = BIT(27) | BIT(26),
  141. .enable_mask = BIT(27) | BIT(25) | BIT(26),
  142. .disable_val = BIT(25),
  143. .vmode = BIT(21),
  144. .enable_time = 100,
  145. .name = "pbias_mmc_omap5"
  146. };
  147. static const struct pbias_reg_info *pbias_reg_infos[] = {
  148. &pbias_mmc_omap5,
  149. &pbias_mmc_omap4,
  150. &pbias_sim_omap3,
  151. &pbias_mmc_omap2430,
  152. NULL
  153. };
  154. static int pbias_regulator_probe(struct udevice *dev)
  155. {
  156. const struct pbias_reg_info **p = pbias_reg_infos;
  157. struct dm_regulator_uclass_plat *uc_pdata;
  158. uc_pdata = dev_get_uclass_plat(dev);
  159. while (*p) {
  160. int rc;
  161. rc = dev_read_stringlist_search(dev, "regulator-name",
  162. (*p)->name);
  163. if (rc >= 0) {
  164. debug("found regulator %s\n", (*p)->name);
  165. break;
  166. } else if (rc != -ENODATA) {
  167. return rc;
  168. }
  169. p++;
  170. }
  171. if (!*p) {
  172. int i = 0;
  173. const char *s;
  174. debug("regulator ");
  175. while (dev_read_string_index(dev, "regulator-name", i++, &s) >= 0)
  176. debug("%s'%s' ", (i > 1) ? ", " : "", s);
  177. debug("%s not supported\n", (i > 2) ? "are" : "is");
  178. return -EINVAL;
  179. }
  180. uc_pdata->type = REGULATOR_TYPE_OTHER;
  181. dev_set_priv(dev, (void *)*p);
  182. return 0;
  183. }
  184. static int pbias_regulator_get_value(struct udevice *dev)
  185. {
  186. const struct pbias_reg_info *p = dev_get_priv(dev);
  187. int rc;
  188. u32 reg;
  189. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  190. if (rc)
  191. return rc;
  192. debug("%s voltage id %s\n", p->name,
  193. (reg & p->vmode) ? "3.0v" : "1.8v");
  194. return (reg & p->vmode) ? 3000000 : 1800000;
  195. }
  196. static int pbias_regulator_set_value(struct udevice *dev, int uV)
  197. {
  198. const struct pbias_reg_info *p = dev_get_priv(dev);
  199. int rc, ret;
  200. u32 reg;
  201. #ifdef CONFIG_MMC_OMAP36XX_PINS
  202. u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
  203. #endif
  204. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  205. if (rc)
  206. return rc;
  207. if (uV == 3300000)
  208. reg |= p->vmode;
  209. else if (uV == 1800000)
  210. reg &= ~p->vmode;
  211. else
  212. return -EINVAL;
  213. debug("Setting %s voltage to %s\n", p->name,
  214. (reg & p->vmode) ? "3.0v" : "1.8v");
  215. #ifdef CONFIG_MMC_OMAP36XX_PINS
  216. if (get_cpu_family() == CPU_OMAP36XX) {
  217. /* Disable extended drain IO before changing PBIAS */
  218. wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
  219. writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
  220. }
  221. #endif
  222. ret = pmic_write(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  223. #ifdef CONFIG_MMC_OMAP36XX_PINS
  224. if (get_cpu_family() == CPU_OMAP36XX) {
  225. /* Enable extended drain IO after changing PBIAS */
  226. writel(wkup_ctrl |
  227. OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
  228. OMAP34XX_CTRL_WKUP_CTRL);
  229. }
  230. #endif
  231. return ret;
  232. }
  233. static int pbias_regulator_get_enable(struct udevice *dev)
  234. {
  235. const struct pbias_reg_info *p = dev_get_priv(dev);
  236. int rc;
  237. u32 reg;
  238. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  239. if (rc)
  240. return rc;
  241. debug("%s id %s\n", p->name,
  242. (reg & p->enable_mask) == (p->disable_val) ? "on" : "off");
  243. return (reg & p->enable_mask) == (p->disable_val);
  244. }
  245. static int pbias_regulator_set_enable(struct udevice *dev, bool enable)
  246. {
  247. const struct pbias_reg_info *p = dev_get_priv(dev);
  248. int rc;
  249. u32 reg;
  250. #ifdef CONFIG_MMC_OMAP36XX_PINS
  251. u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
  252. #endif
  253. debug("Turning %s %s\n", enable ? "on" : "off", p->name);
  254. #ifdef CONFIG_MMC_OMAP36XX_PINS
  255. if (get_cpu_family() == CPU_OMAP36XX) {
  256. /* Disable extended drain IO before changing PBIAS */
  257. wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
  258. writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
  259. }
  260. #endif
  261. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  262. if (rc)
  263. return rc;
  264. reg &= ~p->enable_mask;
  265. if (enable)
  266. reg |= p->enable;
  267. else
  268. reg |= p->disable_val;
  269. rc = pmic_write(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  270. #ifdef CONFIG_MMC_OMAP36XX_PINS
  271. if (get_cpu_family() == CPU_OMAP36XX) {
  272. /* Enable extended drain IO after changing PBIAS */
  273. writel(wkup_ctrl |
  274. OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
  275. OMAP34XX_CTRL_WKUP_CTRL);
  276. }
  277. #endif
  278. if (rc)
  279. return rc;
  280. if (enable)
  281. udelay(p->enable_time);
  282. return 0;
  283. }
  284. static const struct dm_regulator_ops pbias_regulator_ops = {
  285. .get_value = pbias_regulator_get_value,
  286. .set_value = pbias_regulator_set_value,
  287. .get_enable = pbias_regulator_get_enable,
  288. .set_enable = pbias_regulator_set_enable,
  289. };
  290. U_BOOT_DRIVER(pbias_regulator) = {
  291. .name = "pbias_regulator",
  292. .id = UCLASS_REGULATOR,
  293. .ops = &pbias_regulator_ops,
  294. .probe = pbias_regulator_probe,
  295. };