smi.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Marvell International Ltd.
  4. */
  5. #include <dm.h>
  6. #include <malloc.h>
  7. #include <miiphy.h>
  8. #include <misc.h>
  9. #include <pci.h>
  10. #include <pci_ids.h>
  11. #include <phy.h>
  12. #include <asm/io.h>
  13. #include <linux/ctype.h>
  14. #include <linux/delay.h>
  15. #define PCI_DEVICE_ID_OCTEONTX_SMI 0xA02B
  16. DECLARE_GLOBAL_DATA_PTR;
  17. enum octeontx_smi_mode {
  18. CLAUSE22 = 0,
  19. CLAUSE45 = 1,
  20. };
  21. enum {
  22. SMI_OP_C22_WRITE = 0,
  23. SMI_OP_C22_READ = 1,
  24. SMI_OP_C45_ADDR = 0,
  25. SMI_OP_C45_WRITE = 1,
  26. SMI_OP_C45_PRIA = 2,
  27. SMI_OP_C45_READ = 3,
  28. };
  29. union smi_x_clk {
  30. u64 u;
  31. struct smi_x_clk_s {
  32. int phase:8;
  33. int sample:4;
  34. int preamble:1;
  35. int clk_idle:1;
  36. int reserved_14_14:1;
  37. int sample_mode:1;
  38. int sample_hi:5;
  39. int reserved_21_23:3;
  40. int mode:1;
  41. } s;
  42. };
  43. union smi_x_cmd {
  44. u64 u;
  45. struct smi_x_cmd_s {
  46. int reg_adr:5;
  47. int reserved_5_7:3;
  48. int phy_adr:5;
  49. int reserved_13_15:3;
  50. int phy_op:2;
  51. } s;
  52. };
  53. union smi_x_wr_dat {
  54. u64 u;
  55. struct smi_x_wr_dat_s {
  56. unsigned int dat:16;
  57. int val:1;
  58. int pending:1;
  59. } s;
  60. };
  61. union smi_x_rd_dat {
  62. u64 u;
  63. struct smi_x_rd_dat_s {
  64. unsigned int dat:16;
  65. int val:1;
  66. int pending:1;
  67. } s;
  68. };
  69. union smi_x_en {
  70. u64 u;
  71. struct smi_x_en_s {
  72. int en:1;
  73. } s;
  74. };
  75. #define SMI_X_RD_DAT 0x10ull
  76. #define SMI_X_WR_DAT 0x08ull
  77. #define SMI_X_CMD 0x00ull
  78. #define SMI_X_CLK 0x18ull
  79. #define SMI_X_EN 0x20ull
  80. struct octeontx_smi_priv {
  81. void __iomem *baseaddr;
  82. enum octeontx_smi_mode mode;
  83. };
  84. #define MDIO_TIMEOUT 10000
  85. void octeontx_smi_setmode(struct mii_dev *bus, enum octeontx_smi_mode mode)
  86. {
  87. struct octeontx_smi_priv *priv = bus->priv;
  88. union smi_x_clk smix_clk;
  89. smix_clk.u = readq(priv->baseaddr + SMI_X_CLK);
  90. smix_clk.s.mode = mode;
  91. smix_clk.s.preamble = mode == CLAUSE45;
  92. writeq(smix_clk.u, priv->baseaddr + SMI_X_CLK);
  93. priv->mode = mode;
  94. }
  95. int octeontx_c45_addr(struct mii_dev *bus, int addr, int devad, int regnum)
  96. {
  97. struct octeontx_smi_priv *priv = bus->priv;
  98. union smi_x_cmd smix_cmd;
  99. union smi_x_wr_dat smix_wr_dat;
  100. unsigned long timeout = MDIO_TIMEOUT;
  101. smix_wr_dat.u = 0;
  102. smix_wr_dat.s.dat = regnum;
  103. writeq(smix_wr_dat.u, priv->baseaddr + SMI_X_WR_DAT);
  104. smix_cmd.u = 0;
  105. smix_cmd.s.phy_op = SMI_OP_C45_ADDR;
  106. smix_cmd.s.phy_adr = addr;
  107. smix_cmd.s.reg_adr = devad;
  108. writeq(smix_cmd.u, priv->baseaddr + SMI_X_CMD);
  109. do {
  110. smix_wr_dat.u = readq(priv->baseaddr + SMI_X_WR_DAT);
  111. udelay(100);
  112. timeout--;
  113. } while (smix_wr_dat.s.pending && timeout);
  114. return timeout == 0;
  115. }
  116. int octeontx_phy_read(struct mii_dev *bus, int addr, int devad, int regnum)
  117. {
  118. struct octeontx_smi_priv *priv = bus->priv;
  119. union smi_x_cmd smix_cmd;
  120. union smi_x_rd_dat smix_rd_dat;
  121. unsigned long timeout = MDIO_TIMEOUT;
  122. int ret;
  123. enum octeontx_smi_mode mode = (devad < 0) ? CLAUSE22 : CLAUSE45;
  124. debug("RD: Mode: %u, baseaddr: %p, addr: %d, devad: %d, reg: %d\n",
  125. mode, priv->baseaddr, addr, devad, regnum);
  126. octeontx_smi_setmode(bus, mode);
  127. if (mode == CLAUSE45) {
  128. ret = octeontx_c45_addr(bus, addr, devad, regnum);
  129. debug("RD: ret: %u\n", ret);
  130. if (ret)
  131. return 0;
  132. }
  133. smix_cmd.u = 0;
  134. smix_cmd.s.phy_adr = addr;
  135. if (mode == CLAUSE45) {
  136. smix_cmd.s.reg_adr = devad;
  137. smix_cmd.s.phy_op = SMI_OP_C45_READ;
  138. } else {
  139. smix_cmd.s.reg_adr = regnum;
  140. smix_cmd.s.phy_op = SMI_OP_C22_READ;
  141. }
  142. writeq(smix_cmd.u, priv->baseaddr + SMI_X_CMD);
  143. do {
  144. smix_rd_dat.u = readq(priv->baseaddr + SMI_X_RD_DAT);
  145. udelay(10);
  146. timeout--;
  147. } while (smix_rd_dat.s.pending && timeout);
  148. debug("SMIX_RD_DAT: %lx\n", (unsigned long)smix_rd_dat.u);
  149. return smix_rd_dat.s.dat;
  150. }
  151. int octeontx_phy_write(struct mii_dev *bus, int addr, int devad, int regnum,
  152. u16 value)
  153. {
  154. struct octeontx_smi_priv *priv = bus->priv;
  155. union smi_x_cmd smix_cmd;
  156. union smi_x_wr_dat smix_wr_dat;
  157. unsigned long timeout = MDIO_TIMEOUT;
  158. int ret;
  159. enum octeontx_smi_mode mode = (devad < 0) ? CLAUSE22 : CLAUSE45;
  160. debug("WR: Mode: %u, baseaddr: %p, addr: %d, devad: %d, reg: %d\n",
  161. mode, priv->baseaddr, addr, devad, regnum);
  162. if (mode == CLAUSE45) {
  163. ret = octeontx_c45_addr(bus, addr, devad, regnum);
  164. debug("WR: ret: %u\n", ret);
  165. if (ret)
  166. return ret;
  167. }
  168. smix_wr_dat.u = 0;
  169. smix_wr_dat.s.dat = value;
  170. writeq(smix_wr_dat.u, priv->baseaddr + SMI_X_WR_DAT);
  171. smix_cmd.u = 0;
  172. smix_cmd.s.phy_adr = addr;
  173. if (mode == CLAUSE45) {
  174. smix_cmd.s.reg_adr = devad;
  175. smix_cmd.s.phy_op = SMI_OP_C45_WRITE;
  176. } else {
  177. smix_cmd.s.reg_adr = regnum;
  178. smix_cmd.s.phy_op = SMI_OP_C22_WRITE;
  179. }
  180. writeq(smix_cmd.u, priv->baseaddr + SMI_X_CMD);
  181. do {
  182. smix_wr_dat.u = readq(priv->baseaddr + SMI_X_WR_DAT);
  183. udelay(10);
  184. timeout--;
  185. } while (smix_wr_dat.s.pending && timeout);
  186. debug("SMIX_WR_DAT: %lx\n", (unsigned long)smix_wr_dat.u);
  187. return timeout == 0;
  188. }
  189. int octeontx_smi_reset(struct mii_dev *bus)
  190. {
  191. struct octeontx_smi_priv *priv = bus->priv;
  192. union smi_x_en smi_en;
  193. smi_en.s.en = 0;
  194. writeq(smi_en.u, priv->baseaddr + SMI_X_EN);
  195. smi_en.s.en = 1;
  196. writeq(smi_en.u, priv->baseaddr + SMI_X_EN);
  197. octeontx_smi_setmode(bus, CLAUSE22);
  198. return 0;
  199. }
  200. /* PHY XS initialization, primarily for RXAUI
  201. *
  202. */
  203. int rxaui_phy_xs_init(struct mii_dev *bus, int phy_addr)
  204. {
  205. int reg;
  206. ulong start_time;
  207. int phy_id1, phy_id2;
  208. int oui, model_number;
  209. phy_id1 = octeontx_phy_read(bus, phy_addr, 1, 0x2);
  210. phy_id2 = octeontx_phy_read(bus, phy_addr, 1, 0x3);
  211. model_number = (phy_id2 >> 4) & 0x3F;
  212. debug("%s model %x\n", __func__, model_number);
  213. oui = phy_id1;
  214. oui <<= 6;
  215. oui |= (phy_id2 >> 10) & 0x3F;
  216. debug("%s oui %x\n", __func__, oui);
  217. switch (oui) {
  218. case 0x5016:
  219. if (model_number == 9) {
  220. debug("%s +\n", __func__);
  221. /* Perform hardware reset in XGXS control */
  222. reg = octeontx_phy_read(bus, phy_addr, 4, 0x0);
  223. if ((reg & 0xffff) < 0)
  224. goto read_error;
  225. reg |= 0x8000;
  226. octeontx_phy_write(bus, phy_addr, 4, 0x0, reg);
  227. start_time = get_timer(0);
  228. do {
  229. reg = octeontx_phy_read(bus, phy_addr, 4, 0x0);
  230. if ((reg & 0xffff) < 0)
  231. goto read_error;
  232. } while ((reg & 0x8000) && get_timer(start_time) < 500);
  233. if (reg & 0x8000) {
  234. printf("HW reset for M88X3120 PHY failed");
  235. printf("MII_BMCR: 0x%x\n", reg);
  236. return -1;
  237. }
  238. /* program 4.49155 with 0x5 */
  239. octeontx_phy_write(bus, phy_addr, 4, 0xc003, 0x5);
  240. }
  241. break;
  242. default:
  243. break;
  244. }
  245. return 0;
  246. read_error:
  247. debug("M88X3120 PHY config read failed\n");
  248. return -1;
  249. }
  250. int octeontx_smi_probe(struct udevice *dev)
  251. {
  252. int ret, subnode, cnt = 0, node = dev_ofnode(dev).of_offset;
  253. struct mii_dev *bus;
  254. struct octeontx_smi_priv *priv;
  255. pci_dev_t bdf = dm_pci_get_bdf(dev);
  256. debug("SMI PCI device: %x\n", bdf);
  257. if (!dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM)) {
  258. printf("Failed to map PCI region for bdf %x\n", bdf);
  259. return -1;
  260. }
  261. fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
  262. ret = fdt_node_check_compatible(gd->fdt_blob, subnode,
  263. "cavium,thunder-8890-mdio");
  264. if (ret)
  265. continue;
  266. bus = mdio_alloc();
  267. priv = malloc(sizeof(*priv));
  268. if (!bus || !priv) {
  269. printf("Failed to allocate OcteonTX MDIO bus # %u\n",
  270. dev_seq(dev));
  271. return -1;
  272. }
  273. bus->read = octeontx_phy_read;
  274. bus->write = octeontx_phy_write;
  275. bus->reset = octeontx_smi_reset;
  276. bus->priv = priv;
  277. priv->mode = CLAUSE22;
  278. priv->baseaddr = (void __iomem *)fdtdec_get_addr(gd->fdt_blob,
  279. subnode,
  280. "reg");
  281. debug("mdio base addr %p\n", priv->baseaddr);
  282. /* use given name or generate its own unique name */
  283. snprintf(bus->name, MDIO_NAME_LEN, "smi%d", cnt++);
  284. ret = mdio_register(bus);
  285. if (ret)
  286. return ret;
  287. }
  288. return 0;
  289. }
  290. static const struct udevice_id octeontx_smi_ids[] = {
  291. { .compatible = "cavium,thunder-8890-mdio-nexus" },
  292. {}
  293. };
  294. U_BOOT_DRIVER(octeontx_smi) = {
  295. .name = "octeontx_smi",
  296. .id = UCLASS_MISC,
  297. .probe = octeontx_smi_probe,
  298. .of_match = octeontx_smi_ids,
  299. };
  300. static struct pci_device_id octeontx_smi_supported[] = {
  301. { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_SMI) },
  302. {}
  303. };
  304. U_BOOT_PCI_DEVICE(octeontx_smi, octeontx_smi_supported);