fsl_enetc.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ENETC ethernet controller driver
  4. * Copyright 2017-2019 NXP
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <fdt_support.h>
  10. #include <malloc.h>
  11. #include <memalign.h>
  12. #include <net.h>
  13. #include <asm/cache.h>
  14. #include <asm/io.h>
  15. #include <pci.h>
  16. #include <miiphy.h>
  17. #include <linux/bug.h>
  18. #include <linux/delay.h>
  19. #include "fsl_enetc.h"
  20. #define ENETC_DRIVER_NAME "enetc_eth"
  21. /*
  22. * sets the MAC address in IERB registers, this setting is persistent and
  23. * carried over to Linux.
  24. */
  25. static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn,
  26. const u8 *enetaddr)
  27. {
  28. #ifdef CONFIG_ARCH_LS1028A
  29. /*
  30. * LS1028A is the only part with IERB at this time and there are plans to change
  31. * its structure, keep this LS1028A specific for now
  32. */
  33. #define IERB_BASE 0x1f0800000ULL
  34. #define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \
  35. + (n) * 4)
  36. static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
  37. u16 lower = *(const u16 *)(enetaddr + 4);
  38. u32 upper = *(const u32 *)enetaddr;
  39. if (ierb_fn_to_pf[devfn] < 0)
  40. return;
  41. out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper);
  42. out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower);
  43. #endif
  44. }
  45. /* sets up primary MAC addresses in DT/IERB */
  46. void fdt_fixup_enetc_mac(void *blob)
  47. {
  48. struct pci_child_plat *ppdata;
  49. struct eth_pdata *pdata;
  50. struct udevice *dev;
  51. struct uclass *uc;
  52. char path[256];
  53. int offset;
  54. int devfn;
  55. uclass_get(UCLASS_ETH, &uc);
  56. uclass_foreach_dev(dev, uc) {
  57. if (!dev->driver || !dev->driver->name ||
  58. strcmp(dev->driver->name, ENETC_DRIVER_NAME))
  59. continue;
  60. pdata = dev_get_plat(dev);
  61. ppdata = dev_get_parent_plat(dev);
  62. devfn = PCI_FUNC(ppdata->devfn);
  63. enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr);
  64. snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x",
  65. PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn));
  66. offset = fdt_path_offset(blob, path);
  67. if (offset < 0)
  68. continue;
  69. fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6);
  70. }
  71. }
  72. /*
  73. * Bind the device:
  74. * - set a more explicit name on the interface
  75. */
  76. static int enetc_bind(struct udevice *dev)
  77. {
  78. char name[16];
  79. static int eth_num_devices;
  80. /*
  81. * prefer using PCI function numbers to number interfaces, but these
  82. * are only available if dts nodes are present. For PCI they are
  83. * optional, handle that case too. Just in case some nodes are present
  84. * and some are not, use different naming scheme - enetc-N based on
  85. * PCI function # and enetc#N based on interface count
  86. */
  87. if (ofnode_valid(dev_ofnode(dev)))
  88. sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
  89. else
  90. sprintf(name, "enetc#%u", eth_num_devices++);
  91. device_set_name(dev, name);
  92. return 0;
  93. }
  94. /* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
  95. static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  96. {
  97. struct enetc_mdio_priv priv;
  98. priv.regs_base = bus->priv;
  99. return enetc_mdio_read_priv(&priv, addr, devad, reg);
  100. }
  101. static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  102. u16 val)
  103. {
  104. struct enetc_mdio_priv priv;
  105. priv.regs_base = bus->priv;
  106. return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
  107. }
  108. /* only interfaces that can pin out through serdes have internal MDIO */
  109. static bool enetc_has_imdio(struct udevice *dev)
  110. {
  111. struct enetc_priv *priv = dev_get_priv(dev);
  112. return !!(priv->imdio.priv);
  113. }
  114. /* set up serdes for SGMII */
  115. static int enetc_init_sgmii(struct udevice *dev)
  116. {
  117. struct enetc_priv *priv = dev_get_priv(dev);
  118. bool is2500 = false;
  119. u16 reg;
  120. if (!enetc_has_imdio(dev))
  121. return 0;
  122. if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
  123. is2500 = true;
  124. /*
  125. * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
  126. * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
  127. * on PLL configuration. Setting 1G for 2.5G here is counter intuitive
  128. * but intentional.
  129. */
  130. reg = ENETC_PCS_IF_MODE_SGMII;
  131. reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
  132. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
  133. ENETC_PCS_IF_MODE, reg);
  134. /* Dev ability - SGMII */
  135. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
  136. ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
  137. /* Adjust link timer for SGMII */
  138. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
  139. ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
  140. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
  141. ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
  142. reg = ENETC_PCS_CR_DEF_VAL;
  143. reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
  144. /* restart PCS AN */
  145. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
  146. ENETC_PCS_CR, reg);
  147. return 0;
  148. }
  149. /* set up MAC for RGMII */
  150. static int enetc_init_rgmii(struct udevice *dev)
  151. {
  152. struct enetc_priv *priv = dev_get_priv(dev);
  153. u32 if_mode;
  154. /* enable RGMII AN */
  155. if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
  156. if_mode |= ENETC_PM_IF_MODE_AN_ENA;
  157. enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
  158. return 0;
  159. }
  160. /* set up MAC configuration for the given interface type */
  161. static void enetc_setup_mac_iface(struct udevice *dev)
  162. {
  163. struct enetc_priv *priv = dev_get_priv(dev);
  164. u32 if_mode;
  165. switch (priv->if_type) {
  166. case PHY_INTERFACE_MODE_RGMII:
  167. case PHY_INTERFACE_MODE_RGMII_ID:
  168. case PHY_INTERFACE_MODE_RGMII_RXID:
  169. case PHY_INTERFACE_MODE_RGMII_TXID:
  170. enetc_init_rgmii(dev);
  171. break;
  172. case PHY_INTERFACE_MODE_XGMII:
  173. case PHY_INTERFACE_MODE_USXGMII:
  174. case PHY_INTERFACE_MODE_XFI:
  175. /* set ifmode to (US)XGMII */
  176. if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
  177. if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
  178. enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
  179. break;
  180. };
  181. }
  182. /* set up serdes for SXGMII */
  183. static int enetc_init_sxgmii(struct udevice *dev)
  184. {
  185. struct enetc_priv *priv = dev_get_priv(dev);
  186. if (!enetc_has_imdio(dev))
  187. return 0;
  188. /* Dev ability - SXGMII */
  189. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
  190. ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
  191. /* Restart PCS AN */
  192. enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
  193. ENETC_PCS_CR,
  194. ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
  195. return 0;
  196. }
  197. /* Apply protocol specific configuration to MAC, serdes as needed */
  198. static void enetc_start_pcs(struct udevice *dev)
  199. {
  200. struct enetc_priv *priv = dev_get_priv(dev);
  201. const char *if_str;
  202. priv->if_type = PHY_INTERFACE_MODE_NONE;
  203. /* register internal MDIO for debug purposes */
  204. if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
  205. priv->imdio.read = enetc_mdio_read;
  206. priv->imdio.write = enetc_mdio_write;
  207. priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
  208. strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
  209. if (!miiphy_get_dev_by_name(priv->imdio.name))
  210. mdio_register(&priv->imdio);
  211. }
  212. if (!ofnode_valid(dev_ofnode(dev))) {
  213. enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n");
  214. return;
  215. }
  216. if_str = ofnode_read_string(dev_ofnode(dev), "phy-mode");
  217. if (if_str)
  218. priv->if_type = phy_get_interface_by_name(if_str);
  219. else
  220. enetc_dbg(dev,
  221. "phy-mode property not found, defaulting to SGMII\n");
  222. if (priv->if_type < 0)
  223. priv->if_type = PHY_INTERFACE_MODE_NONE;
  224. switch (priv->if_type) {
  225. case PHY_INTERFACE_MODE_SGMII:
  226. case PHY_INTERFACE_MODE_SGMII_2500:
  227. enetc_init_sgmii(dev);
  228. break;
  229. case PHY_INTERFACE_MODE_XGMII:
  230. case PHY_INTERFACE_MODE_USXGMII:
  231. case PHY_INTERFACE_MODE_XFI:
  232. enetc_init_sxgmii(dev);
  233. break;
  234. };
  235. }
  236. /* Configure the actual/external ethernet PHY, if one is found */
  237. static void enetc_config_phy(struct udevice *dev)
  238. {
  239. struct enetc_priv *priv = dev_get_priv(dev);
  240. int supported;
  241. priv->phy = dm_eth_phy_connect(dev);
  242. if (!priv->phy)
  243. return;
  244. supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
  245. priv->phy->supported &= supported;
  246. priv->phy->advertising &= supported;
  247. phy_config(priv->phy);
  248. }
  249. /*
  250. * Probe ENETC driver:
  251. * - initialize port and station interface BARs
  252. */
  253. static int enetc_probe(struct udevice *dev)
  254. {
  255. struct enetc_priv *priv = dev_get_priv(dev);
  256. if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_available(dev_ofnode(dev))) {
  257. enetc_dbg(dev, "interface disabled\n");
  258. return -ENODEV;
  259. }
  260. priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
  261. sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
  262. priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
  263. sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
  264. if (!priv->enetc_txbd || !priv->enetc_rxbd) {
  265. /* free should be able to handle NULL, just free all pointers */
  266. free(priv->enetc_txbd);
  267. free(priv->enetc_rxbd);
  268. return -ENOMEM;
  269. }
  270. /* initialize register */
  271. priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
  272. if (!priv->regs_base) {
  273. enetc_dbg(dev, "failed to map BAR0\n");
  274. return -EINVAL;
  275. }
  276. priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
  277. dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
  278. enetc_start_pcs(dev);
  279. enetc_config_phy(dev);
  280. return 0;
  281. }
  282. /*
  283. * Remove the driver from an interface:
  284. * - free up allocated memory
  285. */
  286. static int enetc_remove(struct udevice *dev)
  287. {
  288. struct enetc_priv *priv = dev_get_priv(dev);
  289. free(priv->enetc_txbd);
  290. free(priv->enetc_rxbd);
  291. return 0;
  292. }
  293. /*
  294. * LS1028A is the only part with IERB at this time and there are plans to
  295. * change its structure, keep this LS1028A specific for now.
  296. */
  297. #define LS1028A_IERB_BASE 0x1f0800000ULL
  298. #define LS1028A_IERB_PSIPMAR0(pf, vf) (LS1028A_IERB_BASE + 0x8000 \
  299. + (pf) * 0x100 + (vf) * 8)
  300. #define LS1028A_IERB_PSIPMAR1(pf, vf) (LS1028A_IERB_PSIPMAR0(pf, vf) + 4)
  301. static int enetc_ls1028a_write_hwaddr(struct udevice *dev)
  302. {
  303. struct pci_child_plat *ppdata = dev_get_parent_plat(dev);
  304. const int devfn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
  305. struct eth_pdata *plat = dev_get_plat(dev);
  306. int devfn = PCI_FUNC(ppdata->devfn);
  307. u8 *addr = plat->enetaddr;
  308. u32 lower, upper;
  309. int pf;
  310. if (devfn >= ARRAY_SIZE(devfn_to_pf))
  311. return 0;
  312. pf = devfn_to_pf[devfn];
  313. if (pf < 0)
  314. return 0;
  315. lower = *(const u16 *)(addr + 4);
  316. upper = *(const u32 *)addr;
  317. out_le32(LS1028A_IERB_PSIPMAR0(pf, 0), upper);
  318. out_le32(LS1028A_IERB_PSIPMAR1(pf, 0), lower);
  319. return 0;
  320. }
  321. static int enetc_write_hwaddr(struct udevice *dev)
  322. {
  323. struct eth_pdata *plat = dev_get_plat(dev);
  324. struct enetc_priv *priv = dev_get_priv(dev);
  325. u8 *addr = plat->enetaddr;
  326. if (IS_ENABLED(CONFIG_ARCH_LS1028A))
  327. return enetc_ls1028a_write_hwaddr(dev);
  328. u16 lower = *(const u16 *)(addr + 4);
  329. u32 upper = *(const u32 *)addr;
  330. enetc_write_port(priv, ENETC_PSIPMAR0, upper);
  331. enetc_write_port(priv, ENETC_PSIPMAR1, lower);
  332. return 0;
  333. }
  334. /* Configure port parameters (# of rings, frame size, enable port) */
  335. static void enetc_enable_si_port(struct enetc_priv *priv)
  336. {
  337. u32 val;
  338. /* set Rx/Tx BDR count */
  339. val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
  340. val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
  341. enetc_write_port(priv, ENETC_PSICFGR(0), val);
  342. /* set Rx max frame size */
  343. enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
  344. /* enable MAC port */
  345. enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
  346. /* enable port */
  347. enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
  348. /* set SI cache policy */
  349. enetc_write(priv, ENETC_SICAR0,
  350. ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
  351. /* enable SI */
  352. enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
  353. }
  354. /* returns DMA address for a given buffer index */
  355. static inline u64 enetc_rxb_address(struct udevice *dev, int i)
  356. {
  357. return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
  358. }
  359. /*
  360. * Setup a single Tx BD Ring (ID = 0):
  361. * - set Tx buffer descriptor address
  362. * - set the BD count
  363. * - initialize the producer and consumer index
  364. */
  365. static void enetc_setup_tx_bdr(struct udevice *dev)
  366. {
  367. struct enetc_priv *priv = dev_get_priv(dev);
  368. struct bd_ring *tx_bdr = &priv->tx_bdr;
  369. u64 tx_bd_add = (u64)priv->enetc_txbd;
  370. /* used later to advance to the next Tx BD */
  371. tx_bdr->bd_count = ENETC_BD_CNT;
  372. tx_bdr->next_prod_idx = 0;
  373. tx_bdr->next_cons_idx = 0;
  374. tx_bdr->cons_idx = priv->regs_base +
  375. ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
  376. tx_bdr->prod_idx = priv->regs_base +
  377. ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
  378. /* set Tx BD address */
  379. enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
  380. lower_32_bits(tx_bd_add));
  381. enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
  382. upper_32_bits(tx_bd_add));
  383. /* set Tx 8 BD count */
  384. enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
  385. tx_bdr->bd_count);
  386. /* reset both producer/consumer indexes */
  387. enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
  388. enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
  389. /* enable TX ring */
  390. enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
  391. }
  392. /*
  393. * Setup a single Rx BD Ring (ID = 0):
  394. * - set Rx buffer descriptors address (one descriptor per buffer)
  395. * - set buffer size as max frame size
  396. * - enable Rx ring
  397. * - reset consumer and producer indexes
  398. * - set buffer for each descriptor
  399. */
  400. static void enetc_setup_rx_bdr(struct udevice *dev)
  401. {
  402. struct enetc_priv *priv = dev_get_priv(dev);
  403. struct bd_ring *rx_bdr = &priv->rx_bdr;
  404. u64 rx_bd_add = (u64)priv->enetc_rxbd;
  405. int i;
  406. /* used later to advance to the next BD produced by ENETC HW */
  407. rx_bdr->bd_count = ENETC_BD_CNT;
  408. rx_bdr->next_prod_idx = 0;
  409. rx_bdr->next_cons_idx = 0;
  410. rx_bdr->cons_idx = priv->regs_base +
  411. ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
  412. rx_bdr->prod_idx = priv->regs_base +
  413. ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
  414. /* set Rx BD address */
  415. enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
  416. lower_32_bits(rx_bd_add));
  417. enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
  418. upper_32_bits(rx_bd_add));
  419. /* set Rx BD count (multiple of 8) */
  420. enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
  421. rx_bdr->bd_count);
  422. /* set Rx buffer size */
  423. enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
  424. /* fill Rx BD */
  425. memset(priv->enetc_rxbd, 0,
  426. rx_bdr->bd_count * sizeof(union enetc_rx_bd));
  427. for (i = 0; i < rx_bdr->bd_count; i++) {
  428. priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
  429. /* each RX buffer must be aligned to 64B */
  430. WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
  431. }
  432. /* reset producer (ENETC owned) and consumer (SW owned) index */
  433. enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
  434. enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
  435. /* enable Rx ring */
  436. enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
  437. }
  438. /*
  439. * Start ENETC interface:
  440. * - perform FLR
  441. * - enable access to port and SI registers
  442. * - set mac address
  443. * - setup TX/RX buffer descriptors
  444. * - enable Tx/Rx rings
  445. */
  446. static int enetc_start(struct udevice *dev)
  447. {
  448. struct enetc_priv *priv = dev_get_priv(dev);
  449. /* reset and enable the PCI device */
  450. dm_pci_flr(dev);
  451. dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
  452. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  453. enetc_enable_si_port(priv);
  454. /* setup Tx/Rx buffer descriptors */
  455. enetc_setup_tx_bdr(dev);
  456. enetc_setup_rx_bdr(dev);
  457. enetc_setup_mac_iface(dev);
  458. if (priv->phy)
  459. phy_startup(priv->phy);
  460. return 0;
  461. }
  462. /*
  463. * Stop the network interface:
  464. * - just quiesce it, we can wipe all configuration as _start starts from
  465. * scratch each time
  466. */
  467. static void enetc_stop(struct udevice *dev)
  468. {
  469. /* FLR is sufficient to quiesce the device */
  470. dm_pci_flr(dev);
  471. /* leave the BARs accessible after we stop, this is needed to use
  472. * internal MDIO in command line.
  473. */
  474. dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
  475. }
  476. /*
  477. * ENETC transmit packet:
  478. * - check if Tx BD ring is full
  479. * - set buffer/packet address (dma address)
  480. * - set final fragment flag
  481. * - try while producer index equals consumer index or timeout
  482. */
  483. static int enetc_send(struct udevice *dev, void *packet, int length)
  484. {
  485. struct enetc_priv *priv = dev_get_priv(dev);
  486. struct bd_ring *txr = &priv->tx_bdr;
  487. void *nv_packet = (void *)packet;
  488. int tries = ENETC_POLL_TRIES;
  489. u32 pi, ci;
  490. pi = txr->next_prod_idx;
  491. ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
  492. /* Tx ring is full when */
  493. if (((pi + 1) % txr->bd_count) == ci) {
  494. enetc_dbg(dev, "Tx BDR full\n");
  495. return -ETIMEDOUT;
  496. }
  497. enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
  498. upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
  499. /* prepare Tx BD */
  500. memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
  501. priv->enetc_txbd[pi].addr =
  502. cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
  503. priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
  504. priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
  505. priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
  506. dmb();
  507. /* send frame: increment producer index */
  508. pi = (pi + 1) % txr->bd_count;
  509. txr->next_prod_idx = pi;
  510. enetc_write_reg(txr->prod_idx, pi);
  511. while ((--tries >= 0) &&
  512. (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
  513. udelay(10);
  514. return tries > 0 ? 0 : -ETIMEDOUT;
  515. }
  516. /*
  517. * Receive frame:
  518. * - wait for the next BD to get ready bit set
  519. * - clean up the descriptor
  520. * - move on and indicate to HW that the cleaned BD is available for Rx
  521. */
  522. static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
  523. {
  524. struct enetc_priv *priv = dev_get_priv(dev);
  525. struct bd_ring *rxr = &priv->rx_bdr;
  526. int tries = ENETC_POLL_TRIES;
  527. int pi = rxr->next_prod_idx;
  528. int ci = rxr->next_cons_idx;
  529. u32 status;
  530. int len;
  531. u8 rdy;
  532. do {
  533. dmb();
  534. status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
  535. /* check if current BD is ready to be consumed */
  536. rdy = ENETC_RXBD_STATUS_R(status);
  537. } while (--tries >= 0 && !rdy);
  538. if (!rdy)
  539. return -EAGAIN;
  540. dmb();
  541. len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
  542. *packetp = (uchar *)enetc_rxb_address(dev, pi);
  543. enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
  544. ENETC_RXBD_STATUS_ERRORS(status),
  545. upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
  546. /* BD clean up and advance to next in ring */
  547. memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
  548. priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
  549. rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
  550. ci = (ci + 1) % rxr->bd_count;
  551. rxr->next_cons_idx = ci;
  552. dmb();
  553. /* free up the slot in the ring for HW */
  554. enetc_write_reg(rxr->cons_idx, ci);
  555. return len;
  556. }
  557. static const struct eth_ops enetc_ops = {
  558. .start = enetc_start,
  559. .send = enetc_send,
  560. .recv = enetc_recv,
  561. .stop = enetc_stop,
  562. .write_hwaddr = enetc_write_hwaddr,
  563. };
  564. U_BOOT_DRIVER(eth_enetc) = {
  565. .name = ENETC_DRIVER_NAME,
  566. .id = UCLASS_ETH,
  567. .bind = enetc_bind,
  568. .probe = enetc_probe,
  569. .remove = enetc_remove,
  570. .ops = &enetc_ops,
  571. .priv_auto = sizeof(struct enetc_priv),
  572. .plat_auto = sizeof(struct eth_pdata),
  573. };
  574. static struct pci_device_id enetc_ids[] = {
  575. { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
  576. {}
  577. };
  578. U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);