eth.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. * Dave Liu <daveliu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <part.h>
  10. #include <asm/io.h>
  11. #ifdef CONFIG_DM_ETH
  12. #include <dm.h>
  13. #include <dm/ofnode.h>
  14. #include <linux/compat.h>
  15. #include <phy_interface.h>
  16. #endif
  17. #include <malloc.h>
  18. #include <net.h>
  19. #include <hwconfig.h>
  20. #include <fm_eth.h>
  21. #include <fsl_mdio.h>
  22. #include <miiphy.h>
  23. #include <phy.h>
  24. #include <fsl_dtsec.h>
  25. #include <fsl_tgec.h>
  26. #include <fsl_memac.h>
  27. #include <linux/delay.h>
  28. #include "fm.h"
  29. #ifndef CONFIG_DM_ETH
  30. static struct eth_device *devlist[NUM_FM_PORTS];
  31. static int num_controllers;
  32. #endif
  33. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
  34. #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
  35. TBIANA_FULL_DUPLEX)
  36. #define TBIANA_SGMII_ACK 0x4001
  37. #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
  38. TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
  39. /* Configure the TBI for SGMII operation */
  40. static void dtsec_configure_serdes(struct fm_eth *priv)
  41. {
  42. #ifdef CONFIG_SYS_FMAN_V3
  43. u32 value;
  44. struct mii_dev bus;
  45. bool sgmii_2500 = (priv->enet_if ==
  46. PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
  47. int i = 0, j;
  48. #ifndef CONFIG_DM_ETH
  49. bus.priv = priv->mac->phyregs;
  50. #else
  51. bus.priv = priv->pcs_mdio;
  52. bus.read = memac_mdio_read;
  53. bus.write = memac_mdio_write;
  54. bus.reset = memac_mdio_reset;
  55. #endif
  56. qsgmii_loop:
  57. /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
  58. if (sgmii_2500)
  59. value = PHY_SGMII_CR_PHY_RESET |
  60. PHY_SGMII_IF_SPEED_GIGABIT |
  61. PHY_SGMII_IF_MODE_SGMII;
  62. else
  63. value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
  64. for (j = 0; j <= 3; j++)
  65. debug("dump PCS reg %#x: %#x\n", j,
  66. memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
  67. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
  68. /* Dev ability according to SGMII specification */
  69. value = PHY_SGMII_DEV_ABILITY_SGMII;
  70. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
  71. if (sgmii_2500) {
  72. /* Adjust link timer for 2.5G SGMII,
  73. * 1.6 ms in units of 3.2 ns:
  74. * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
  75. */
  76. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
  77. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
  78. } else {
  79. /* Adjust link timer for SGMII,
  80. * 1.6 ms in units of 8 ns:
  81. * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
  82. */
  83. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
  84. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
  85. }
  86. /* Restart AN */
  87. value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
  88. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
  89. if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
  90. i++;
  91. goto qsgmii_loop;
  92. }
  93. #else
  94. struct dtsec *regs = priv->mac->base;
  95. struct tsec_mii_mng *phyregs = priv->mac->phyregs;
  96. /*
  97. * Access TBI PHY registers at given TSEC register offset as
  98. * opposed to the register offset used for external PHY accesses
  99. */
  100. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
  101. TBICON_CLK_SELECT);
  102. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
  103. TBIANA_SGMII_ACK);
  104. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
  105. TBI_CR, TBICR_SETTINGS);
  106. #endif
  107. }
  108. static void dtsec_init_phy(struct fm_eth *fm_eth)
  109. {
  110. #ifndef CONFIG_SYS_FMAN_V3
  111. struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
  112. /* Assign a Physical address to the TBI */
  113. out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
  114. #endif
  115. if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
  116. fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
  117. fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
  118. dtsec_configure_serdes(fm_eth);
  119. }
  120. #ifndef CONFIG_DM_ETH
  121. #ifdef CONFIG_PHYLIB
  122. static int tgec_is_fibre(struct fm_eth *fm)
  123. {
  124. char phyopt[20];
  125. sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
  126. return hwconfig_arg_cmp(phyopt, "xfi");
  127. }
  128. #endif
  129. #endif /* CONFIG_DM_ETH */
  130. #endif
  131. static u16 muram_readw(u16 *addr)
  132. {
  133. ulong base = (ulong)addr & ~0x3UL;
  134. u32 val32 = in_be32((void *)base);
  135. int byte_pos;
  136. u16 ret;
  137. byte_pos = (ulong)addr & 0x3UL;
  138. if (byte_pos)
  139. ret = (u16)(val32 & 0x0000ffff);
  140. else
  141. ret = (u16)((val32 & 0xffff0000) >> 16);
  142. return ret;
  143. }
  144. static void muram_writew(u16 *addr, u16 val)
  145. {
  146. ulong base = (ulong)addr & ~0x3UL;
  147. u32 org32 = in_be32((void *)base);
  148. u32 val32;
  149. int byte_pos;
  150. byte_pos = (ulong)addr & 0x3UL;
  151. if (byte_pos)
  152. val32 = (org32 & 0xffff0000) | val;
  153. else
  154. val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
  155. out_be32((void *)base, val32);
  156. }
  157. static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
  158. {
  159. int timeout = 1000000;
  160. clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
  161. /* wait until the rx port is not busy */
  162. while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
  163. ;
  164. if (!timeout)
  165. printf("%s - timeout\n", __func__);
  166. }
  167. static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
  168. {
  169. /* set BMI to independent mode, Rx port disable */
  170. out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
  171. /* clear FOF in IM case */
  172. out_be32(&rx_port->fmbm_rim, 0);
  173. /* Rx frame next engine -RISC */
  174. out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
  175. /* Rx command attribute - no order, MR[3] = 1 */
  176. clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
  177. setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
  178. /* enable Rx statistic counters */
  179. out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
  180. /* disable Rx performance counters */
  181. out_be32(&rx_port->fmbm_rpc, 0);
  182. }
  183. static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
  184. {
  185. int timeout = 1000000;
  186. clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
  187. /* wait until the tx port is not busy */
  188. while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
  189. ;
  190. if (!timeout)
  191. printf("%s - timeout\n", __func__);
  192. }
  193. static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
  194. {
  195. /* set BMI to independent mode, Tx port disable */
  196. out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
  197. /* Tx frame next engine -RISC */
  198. out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
  199. out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
  200. /* Tx command attribute - no order, MR[3] = 1 */
  201. clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
  202. setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
  203. /* enable Tx statistic counters */
  204. out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
  205. /* disable Tx performance counters */
  206. out_be32(&tx_port->fmbm_tpc, 0);
  207. }
  208. static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
  209. {
  210. struct fm_port_global_pram *pram;
  211. u32 pram_page_offset;
  212. void *rx_bd_ring_base;
  213. void *rx_buf_pool;
  214. u32 bd_ring_base_lo, bd_ring_base_hi;
  215. u32 buf_lo, buf_hi;
  216. struct fm_port_bd *rxbd;
  217. struct fm_port_qd *rxqd;
  218. struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
  219. int i;
  220. /* alloc global parameter ram at MURAM */
  221. pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
  222. FM_PRAM_SIZE, FM_PRAM_ALIGN);
  223. if (!pram) {
  224. printf("%s: No muram for Rx global parameter\n", __func__);
  225. return -ENOMEM;
  226. }
  227. fm_eth->rx_pram = pram;
  228. /* parameter page offset to MURAM */
  229. pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
  230. /* enable global mode- snooping data buffers and BDs */
  231. out_be32(&pram->mode, PRAM_MODE_GLOBAL);
  232. /* init the Rx queue descriptor pionter */
  233. out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
  234. /* set the max receive buffer length, power of 2 */
  235. muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
  236. /* alloc Rx buffer descriptors from main memory */
  237. rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
  238. * RX_BD_RING_SIZE);
  239. if (!rx_bd_ring_base)
  240. return -ENOMEM;
  241. memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
  242. * RX_BD_RING_SIZE);
  243. /* alloc Rx buffer from main memory */
  244. rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
  245. if (!rx_buf_pool)
  246. return -ENOMEM;
  247. memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
  248. debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
  249. /* save them to fm_eth */
  250. fm_eth->rx_bd_ring = rx_bd_ring_base;
  251. fm_eth->cur_rxbd = rx_bd_ring_base;
  252. fm_eth->rx_buf = rx_buf_pool;
  253. /* init Rx BDs ring */
  254. rxbd = (struct fm_port_bd *)rx_bd_ring_base;
  255. for (i = 0; i < RX_BD_RING_SIZE; i++) {
  256. muram_writew(&rxbd->status, RxBD_EMPTY);
  257. muram_writew(&rxbd->len, 0);
  258. buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
  259. i * MAX_RXBUF_LEN));
  260. buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
  261. i * MAX_RXBUF_LEN));
  262. muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
  263. out_be32(&rxbd->buf_ptr_lo, buf_lo);
  264. rxbd++;
  265. }
  266. /* set the Rx queue descriptor */
  267. rxqd = &pram->rxqd;
  268. muram_writew(&rxqd->gen, 0);
  269. bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
  270. bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
  271. muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
  272. out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
  273. muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
  274. * RX_BD_RING_SIZE);
  275. muram_writew(&rxqd->offset_in, 0);
  276. muram_writew(&rxqd->offset_out, 0);
  277. /* set IM parameter ram pointer to Rx Frame Queue ID */
  278. out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
  279. return 0;
  280. }
  281. static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
  282. {
  283. struct fm_port_global_pram *pram;
  284. u32 pram_page_offset;
  285. void *tx_bd_ring_base;
  286. u32 bd_ring_base_lo, bd_ring_base_hi;
  287. struct fm_port_bd *txbd;
  288. struct fm_port_qd *txqd;
  289. struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
  290. int i;
  291. /* alloc global parameter ram at MURAM */
  292. pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
  293. FM_PRAM_SIZE, FM_PRAM_ALIGN);
  294. if (!pram) {
  295. printf("%s: No muram for Tx global parameter\n", __func__);
  296. return -ENOMEM;
  297. }
  298. fm_eth->tx_pram = pram;
  299. /* parameter page offset to MURAM */
  300. pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
  301. /* enable global mode- snooping data buffers and BDs */
  302. out_be32(&pram->mode, PRAM_MODE_GLOBAL);
  303. /* init the Tx queue descriptor pionter */
  304. out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
  305. /* alloc Tx buffer descriptors from main memory */
  306. tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
  307. * TX_BD_RING_SIZE);
  308. if (!tx_bd_ring_base)
  309. return -ENOMEM;
  310. memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
  311. * TX_BD_RING_SIZE);
  312. /* save it to fm_eth */
  313. fm_eth->tx_bd_ring = tx_bd_ring_base;
  314. fm_eth->cur_txbd = tx_bd_ring_base;
  315. /* init Tx BDs ring */
  316. txbd = (struct fm_port_bd *)tx_bd_ring_base;
  317. for (i = 0; i < TX_BD_RING_SIZE; i++) {
  318. muram_writew(&txbd->status, TxBD_LAST);
  319. muram_writew(&txbd->len, 0);
  320. muram_writew(&txbd->buf_ptr_hi, 0);
  321. out_be32(&txbd->buf_ptr_lo, 0);
  322. txbd++;
  323. }
  324. /* set the Tx queue decriptor */
  325. txqd = &pram->txqd;
  326. bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
  327. bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
  328. muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
  329. out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
  330. muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
  331. * TX_BD_RING_SIZE);
  332. muram_writew(&txqd->offset_in, 0);
  333. muram_writew(&txqd->offset_out, 0);
  334. /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
  335. out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
  336. return 0;
  337. }
  338. static int fm_eth_init(struct fm_eth *fm_eth)
  339. {
  340. int ret;
  341. ret = fm_eth_rx_port_parameter_init(fm_eth);
  342. if (ret)
  343. return ret;
  344. ret = fm_eth_tx_port_parameter_init(fm_eth);
  345. if (ret)
  346. return ret;
  347. return 0;
  348. }
  349. static int fm_eth_startup(struct fm_eth *fm_eth)
  350. {
  351. struct fsl_enet_mac *mac;
  352. int ret;
  353. mac = fm_eth->mac;
  354. /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
  355. ret = fm_eth_init(fm_eth);
  356. if (ret)
  357. return ret;
  358. /* setup the MAC controller */
  359. mac->init_mac(mac);
  360. /* For some reason we need to set SPEED_100 */
  361. if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
  362. (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
  363. (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
  364. mac->set_if_mode)
  365. mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
  366. /* init bmi rx port, IM mode and disable */
  367. bmi_rx_port_init(fm_eth->rx_port);
  368. /* init bmi tx port, IM mode and disable */
  369. bmi_tx_port_init(fm_eth->tx_port);
  370. return 0;
  371. }
  372. static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
  373. {
  374. struct fm_port_global_pram *pram;
  375. pram = fm_eth->tx_pram;
  376. /* graceful stop transmission of frames */
  377. setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
  378. sync();
  379. }
  380. static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
  381. {
  382. struct fm_port_global_pram *pram;
  383. pram = fm_eth->tx_pram;
  384. /* re-enable transmission of frames */
  385. clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
  386. sync();
  387. }
  388. #ifndef CONFIG_DM_ETH
  389. static int fm_eth_open(struct eth_device *dev, struct bd_info *bd)
  390. #else
  391. static int fm_eth_open(struct udevice *dev)
  392. #endif
  393. {
  394. #ifndef CONFIG_DM_ETH
  395. struct fm_eth *fm_eth = dev->priv;
  396. #else
  397. struct eth_pdata *pdata = dev_get_plat(dev);
  398. struct fm_eth *fm_eth = dev_get_priv(dev);
  399. #endif
  400. unsigned char *enetaddr;
  401. struct fsl_enet_mac *mac;
  402. #ifdef CONFIG_PHYLIB
  403. int ret;
  404. #endif
  405. mac = fm_eth->mac;
  406. #ifndef CONFIG_DM_ETH
  407. enetaddr = &dev->enetaddr[0];
  408. #else
  409. enetaddr = pdata->enetaddr;
  410. #endif
  411. /* setup the MAC address */
  412. if (enetaddr[0] & 0x01) {
  413. printf("%s: MacAddress is multicast address\n", __func__);
  414. enetaddr[0] = 0;
  415. enetaddr[5] = fm_eth->num;
  416. }
  417. mac->set_mac_addr(mac, enetaddr);
  418. /* enable bmi Rx port */
  419. setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
  420. /* enable MAC rx/tx port */
  421. mac->enable_mac(mac);
  422. /* enable bmi Tx port */
  423. setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
  424. /* re-enable transmission of frame */
  425. fmc_tx_port_graceful_stop_disable(fm_eth);
  426. #ifdef CONFIG_PHYLIB
  427. if (fm_eth->phydev) {
  428. ret = phy_startup(fm_eth->phydev);
  429. if (ret) {
  430. #ifndef CONFIG_DM_ETH
  431. printf("%s: Could not initialize\n",
  432. fm_eth->phydev->dev->name);
  433. #else
  434. printf("%s: Could not initialize\n", dev->name);
  435. #endif
  436. return ret;
  437. }
  438. } else {
  439. return 0;
  440. }
  441. #else
  442. fm_eth->phydev->speed = SPEED_1000;
  443. fm_eth->phydev->link = 1;
  444. fm_eth->phydev->duplex = DUPLEX_FULL;
  445. #endif
  446. /* set the MAC-PHY mode */
  447. mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
  448. debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
  449. fm_eth->phydev->speed, fm_eth->phydev->link);
  450. if (!fm_eth->phydev->link)
  451. printf("%s: No link.\n", fm_eth->phydev->dev->name);
  452. return fm_eth->phydev->link ? 0 : -1;
  453. }
  454. #ifndef CONFIG_DM_ETH
  455. static void fm_eth_halt(struct eth_device *dev)
  456. #else
  457. static void fm_eth_halt(struct udevice *dev)
  458. #endif
  459. {
  460. struct fm_eth *fm_eth;
  461. struct fsl_enet_mac *mac;
  462. #ifndef CONFIG_DM_ETH
  463. fm_eth = (struct fm_eth *)dev->priv;
  464. #else
  465. fm_eth = dev_get_priv(dev);
  466. #endif
  467. mac = fm_eth->mac;
  468. /* graceful stop the transmission of frames */
  469. fmc_tx_port_graceful_stop_enable(fm_eth);
  470. /* disable bmi Tx port */
  471. bmi_tx_port_disable(fm_eth->tx_port);
  472. /* disable MAC rx/tx port */
  473. mac->disable_mac(mac);
  474. /* disable bmi Rx port */
  475. bmi_rx_port_disable(fm_eth->rx_port);
  476. #ifdef CONFIG_PHYLIB
  477. if (fm_eth->phydev)
  478. phy_shutdown(fm_eth->phydev);
  479. #endif
  480. }
  481. #ifndef CONFIG_DM_ETH
  482. static int fm_eth_send(struct eth_device *dev, void *buf, int len)
  483. #else
  484. static int fm_eth_send(struct udevice *dev, void *buf, int len)
  485. #endif
  486. {
  487. struct fm_eth *fm_eth;
  488. struct fm_port_global_pram *pram;
  489. struct fm_port_bd *txbd, *txbd_base;
  490. u16 offset_in;
  491. int i;
  492. #ifndef CONFIG_DM_ETH
  493. fm_eth = (struct fm_eth *)dev->priv;
  494. #else
  495. fm_eth = dev_get_priv(dev);
  496. #endif
  497. pram = fm_eth->tx_pram;
  498. txbd = fm_eth->cur_txbd;
  499. /* find one empty TxBD */
  500. for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
  501. udelay(100);
  502. if (i > 0x1000) {
  503. printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
  504. dev->name, muram_readw(&txbd->status));
  505. return 0;
  506. }
  507. }
  508. /* setup TxBD */
  509. muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
  510. out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
  511. muram_writew(&txbd->len, len);
  512. sync();
  513. muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
  514. sync();
  515. /* update TxQD, let RISC to send the packet */
  516. offset_in = muram_readw(&pram->txqd.offset_in);
  517. offset_in += sizeof(struct fm_port_bd);
  518. if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
  519. offset_in = 0;
  520. muram_writew(&pram->txqd.offset_in, offset_in);
  521. sync();
  522. /* wait for buffer to be transmitted */
  523. for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
  524. udelay(100);
  525. if (i > 0x10000) {
  526. printf("%s: Tx error, txbd->status = 0x%x\n",
  527. dev->name, muram_readw(&txbd->status));
  528. return 0;
  529. }
  530. }
  531. /* advance the TxBD */
  532. txbd++;
  533. txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
  534. if (txbd >= (txbd_base + TX_BD_RING_SIZE))
  535. txbd = txbd_base;
  536. /* update current txbd */
  537. fm_eth->cur_txbd = (void *)txbd;
  538. return 1;
  539. }
  540. static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
  541. struct fm_port_bd *rxbd)
  542. {
  543. struct fm_port_global_pram *pram;
  544. struct fm_port_bd *rxbd_base;
  545. u16 offset_out;
  546. pram = fm_eth->rx_pram;
  547. /* clear the RxBDs */
  548. muram_writew(&rxbd->status, RxBD_EMPTY);
  549. muram_writew(&rxbd->len, 0);
  550. sync();
  551. /* advance RxBD */
  552. rxbd++;
  553. rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
  554. if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
  555. rxbd = rxbd_base;
  556. /* update RxQD */
  557. offset_out = muram_readw(&pram->rxqd.offset_out);
  558. offset_out += sizeof(struct fm_port_bd);
  559. if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
  560. offset_out = 0;
  561. muram_writew(&pram->rxqd.offset_out, offset_out);
  562. sync();
  563. return rxbd;
  564. }
  565. #ifndef CONFIG_DM_ETH
  566. static int fm_eth_recv(struct eth_device *dev)
  567. #else
  568. static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  569. #endif
  570. {
  571. struct fm_eth *fm_eth;
  572. struct fm_port_bd *rxbd;
  573. u32 buf_lo, buf_hi;
  574. u16 status, len;
  575. int ret = -1;
  576. u8 *data;
  577. #ifndef CONFIG_DM_ETH
  578. fm_eth = (struct fm_eth *)dev->priv;
  579. #else
  580. fm_eth = dev_get_priv(dev);
  581. #endif
  582. rxbd = fm_eth->cur_rxbd;
  583. status = muram_readw(&rxbd->status);
  584. while (!(status & RxBD_EMPTY)) {
  585. if (!(status & RxBD_ERROR)) {
  586. buf_hi = muram_readw(&rxbd->buf_ptr_hi);
  587. buf_lo = in_be32(&rxbd->buf_ptr_lo);
  588. data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
  589. len = muram_readw(&rxbd->len);
  590. #ifndef CONFIG_DM_ETH
  591. net_process_received_packet(data, len);
  592. #else
  593. *packetp = data;
  594. return len;
  595. #endif
  596. } else {
  597. printf("%s: Rx error\n", dev->name);
  598. ret = 0;
  599. }
  600. /* free current bd, advance to next one */
  601. rxbd = fm_eth_free_one(fm_eth, rxbd);
  602. /* read next status */
  603. status = muram_readw(&rxbd->status);
  604. }
  605. fm_eth->cur_rxbd = (void *)rxbd;
  606. return ret;
  607. }
  608. #ifdef CONFIG_DM_ETH
  609. static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  610. {
  611. struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
  612. fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
  613. return 0;
  614. }
  615. #endif /* CONFIG_DM_ETH */
  616. #ifndef CONFIG_DM_ETH
  617. static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
  618. {
  619. struct fsl_enet_mac *mac;
  620. int num;
  621. void *base, *phyregs = NULL;
  622. num = fm_eth->num;
  623. #ifdef CONFIG_SYS_FMAN_V3
  624. #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  625. if (fm_eth->type == FM_ETH_10G_E) {
  626. /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
  627. * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
  628. * 10GEC1 uses mEMAC1 on T1024.
  629. * so it needs to change the num.
  630. */
  631. if (fm_eth->num >= 2)
  632. num -= 2;
  633. else
  634. num += 8;
  635. }
  636. #endif
  637. base = &reg->memac[num].fm_memac;
  638. phyregs = &reg->memac[num].fm_memac_mdio;
  639. #else
  640. /* Get the mac registers base address */
  641. if (fm_eth->type == FM_ETH_1G_E) {
  642. base = &reg->mac_1g[num].fm_dtesc;
  643. phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
  644. } else {
  645. base = &reg->mac_10g[num].fm_10gec;
  646. phyregs = &reg->mac_10g[num].fm_10gec_mdio;
  647. }
  648. #endif
  649. /* alloc mac controller */
  650. mac = malloc(sizeof(struct fsl_enet_mac));
  651. if (!mac)
  652. return -ENOMEM;
  653. memset(mac, 0, sizeof(struct fsl_enet_mac));
  654. /* save the mac to fm_eth struct */
  655. fm_eth->mac = mac;
  656. #ifdef CONFIG_SYS_FMAN_V3
  657. init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
  658. #else
  659. if (fm_eth->type == FM_ETH_1G_E)
  660. init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
  661. else
  662. init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
  663. #endif
  664. return 0;
  665. }
  666. #else /* CONFIG_DM_ETH */
  667. static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
  668. {
  669. #ifndef CONFIG_SYS_FMAN_V3
  670. void *mdio;
  671. #endif
  672. fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
  673. if (!fm_eth->mac)
  674. return -ENOMEM;
  675. #ifndef CONFIG_SYS_FMAN_V3
  676. mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
  677. debug("MDIO %d @ %p\n", fm_eth->num, mdio);
  678. #endif
  679. switch (fm_eth->mac_type) {
  680. #ifdef CONFIG_SYS_FMAN_V3
  681. case FM_MEMAC:
  682. init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
  683. break;
  684. #else
  685. case FM_DTSEC:
  686. init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
  687. break;
  688. case FM_TGEC:
  689. init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
  690. break;
  691. #endif
  692. }
  693. return 0;
  694. }
  695. #endif /* CONFIG_DM_ETH */
  696. static int init_phy(struct fm_eth *fm_eth)
  697. {
  698. #ifdef CONFIG_PHYLIB
  699. u32 supported = PHY_GBIT_FEATURES;
  700. #ifndef CONFIG_DM_ETH
  701. struct phy_device *phydev = NULL;
  702. #endif
  703. if (fm_eth->type == FM_ETH_10G_E)
  704. supported = PHY_10G_FEATURES;
  705. if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
  706. supported |= SUPPORTED_2500baseX_Full;
  707. #endif
  708. if (fm_eth->type == FM_ETH_1G_E)
  709. dtsec_init_phy(fm_eth);
  710. #ifdef CONFIG_DM_ETH
  711. #ifdef CONFIG_PHYLIB
  712. #ifdef CONFIG_DM_MDIO
  713. fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
  714. if (!fm_eth->phydev)
  715. return -ENODEV;
  716. #endif
  717. fm_eth->phydev->advertising &= supported;
  718. fm_eth->phydev->supported &= supported;
  719. phy_config(fm_eth->phydev);
  720. #endif
  721. #else /* CONFIG_DM_ETH */
  722. #ifdef CONFIG_PHYLIB
  723. if (fm_eth->bus) {
  724. phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
  725. fm_eth->enet_if);
  726. if (!phydev) {
  727. printf("Failed to connect\n");
  728. return -1;
  729. }
  730. } else {
  731. return 0;
  732. }
  733. if (fm_eth->type == FM_ETH_1G_E) {
  734. supported = (SUPPORTED_10baseT_Half |
  735. SUPPORTED_10baseT_Full |
  736. SUPPORTED_100baseT_Half |
  737. SUPPORTED_100baseT_Full |
  738. SUPPORTED_1000baseT_Full);
  739. } else {
  740. supported = SUPPORTED_10000baseT_Full;
  741. if (tgec_is_fibre(fm_eth))
  742. phydev->port = PORT_FIBRE;
  743. }
  744. phydev->supported &= supported;
  745. phydev->advertising = phydev->supported;
  746. fm_eth->phydev = phydev;
  747. phy_config(phydev);
  748. #endif
  749. #endif /* CONFIG_DM_ETH */
  750. return 0;
  751. }
  752. #ifndef CONFIG_DM_ETH
  753. int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
  754. {
  755. struct eth_device *dev;
  756. struct fm_eth *fm_eth;
  757. int i, num = info->num;
  758. int ret;
  759. /* alloc eth device */
  760. dev = (struct eth_device *)malloc(sizeof(struct eth_device));
  761. if (!dev)
  762. return -ENOMEM;
  763. memset(dev, 0, sizeof(struct eth_device));
  764. /* alloc the FMan ethernet private struct */
  765. fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
  766. if (!fm_eth)
  767. return -ENOMEM;
  768. memset(fm_eth, 0, sizeof(struct fm_eth));
  769. /* save off some things we need from the info struct */
  770. fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
  771. fm_eth->num = num;
  772. fm_eth->type = info->type;
  773. fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
  774. fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
  775. /* set the ethernet max receive length */
  776. fm_eth->max_rx_len = MAX_RXBUF_LEN;
  777. /* init global mac structure */
  778. ret = fm_eth_init_mac(fm_eth, reg);
  779. if (ret)
  780. return ret;
  781. /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
  782. if (fm_eth->type == FM_ETH_1G_E)
  783. sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
  784. else
  785. sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
  786. devlist[num_controllers++] = dev;
  787. dev->iobase = 0;
  788. dev->priv = (void *)fm_eth;
  789. dev->init = fm_eth_open;
  790. dev->halt = fm_eth_halt;
  791. dev->send = fm_eth_send;
  792. dev->recv = fm_eth_recv;
  793. fm_eth->dev = dev;
  794. fm_eth->bus = info->bus;
  795. fm_eth->phyaddr = info->phy_addr;
  796. fm_eth->enet_if = info->enet_if;
  797. /* startup the FM im */
  798. ret = fm_eth_startup(fm_eth);
  799. if (ret)
  800. return ret;
  801. init_phy(fm_eth);
  802. /* clear the ethernet address */
  803. for (i = 0; i < 6; i++)
  804. dev->enetaddr[i] = 0;
  805. eth_register(dev);
  806. return 0;
  807. }
  808. #else /* CONFIG_DM_ETH */
  809. #ifdef CONFIG_PHYLIB
  810. phy_interface_t fman_read_sys_if(struct udevice *dev)
  811. {
  812. const char *if_str;
  813. if_str = ofnode_read_string(dev_ofnode(dev), "phy-connection-type");
  814. debug("MAC system interface mode %s\n", if_str);
  815. return phy_get_interface_by_name(if_str);
  816. }
  817. #endif
  818. static int fm_eth_bind(struct udevice *dev)
  819. {
  820. char mac_name[11];
  821. u32 fm, num;
  822. if (ofnode_read_u32(ofnode_get_parent(dev_ofnode(dev)), "cell-index", &fm)) {
  823. printf("FMan node property cell-index missing\n");
  824. return -EINVAL;
  825. }
  826. if (dev && dev_read_u32(dev, "cell-index", &num)) {
  827. printf("FMan MAC node property cell-index missing\n");
  828. return -EINVAL;
  829. }
  830. sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
  831. device_set_name(dev, mac_name);
  832. debug("%s - binding %s\n", __func__, mac_name);
  833. return 0;
  834. }
  835. static struct udevice *fm_get_internal_mdio(struct udevice *dev)
  836. {
  837. struct ofnode_phandle_args phandle = {.node = ofnode_null()};
  838. struct udevice *mdiodev;
  839. if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
  840. 0, 0, &phandle) ||
  841. !ofnode_valid(phandle.node)) {
  842. if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
  843. 0, 0, &phandle) ||
  844. !ofnode_valid(phandle.node)) {
  845. printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
  846. dev->name);
  847. return NULL;
  848. }
  849. }
  850. if (uclass_get_device_by_ofnode(UCLASS_MDIO,
  851. ofnode_get_parent(phandle.node),
  852. &mdiodev)) {
  853. printf("can't find MDIO bus for node %s\n",
  854. ofnode_get_name(ofnode_get_parent(phandle.node)));
  855. return NULL;
  856. }
  857. debug("Found internal MDIO bus %p\n", mdiodev);
  858. return mdiodev;
  859. }
  860. static int fm_eth_probe(struct udevice *dev)
  861. {
  862. struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
  863. struct ofnode_phandle_args args;
  864. void *reg;
  865. int ret, index;
  866. debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
  867. (dev) ? dev->name : "-");
  868. if (fm_eth->dev) {
  869. printf("%s already probed, exit\n", (dev) ? dev->name : "-");
  870. return 0;
  871. }
  872. fm_eth->dev = dev;
  873. fm_eth->fm_index = fman_id(dev->parent);
  874. reg = (void *)(uintptr_t)dev_read_addr(dev);
  875. fm_eth->mac_type = dev_get_driver_data(dev);
  876. #ifdef CONFIG_PHYLIB
  877. fm_eth->enet_if = fman_read_sys_if(dev);
  878. #else
  879. fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
  880. printf("%s: warning - unable to determine interface type\n", __func__);
  881. #endif
  882. switch (fm_eth->mac_type) {
  883. #ifndef CONFIG_SYS_FMAN_V3
  884. case FM_TGEC:
  885. fm_eth->type = FM_ETH_10G_E;
  886. break;
  887. case FM_DTSEC:
  888. #else
  889. case FM_MEMAC:
  890. /* default to 1G, 10G is indicated by port property in dts */
  891. #endif
  892. fm_eth->type = FM_ETH_1G_E;
  893. break;
  894. }
  895. if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
  896. printf("FMan MAC node property cell-index missing\n");
  897. return -EINVAL;
  898. }
  899. if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
  900. 0, 0, &args))
  901. goto ports_ref_failure;
  902. index = ofnode_read_u32_default(args.node, "cell-index", 0);
  903. if (index <= 0)
  904. goto ports_ref_failure;
  905. fm_eth->rx_port = fman_port(dev->parent, index);
  906. if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
  907. fm_eth->type = FM_ETH_10G_E;
  908. if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
  909. 0, 1, &args))
  910. goto ports_ref_failure;
  911. index = ofnode_read_u32_default(args.node, "cell-index", 0);
  912. if (index <= 0)
  913. goto ports_ref_failure;
  914. fm_eth->tx_port = fman_port(dev->parent, index);
  915. /* set the ethernet max receive length */
  916. fm_eth->max_rx_len = MAX_RXBUF_LEN;
  917. switch (fm_eth->enet_if) {
  918. case PHY_INTERFACE_MODE_QSGMII:
  919. /* all PCS blocks are accessed on one controller */
  920. if (fm_eth->num != 0)
  921. break;
  922. case PHY_INTERFACE_MODE_SGMII:
  923. case PHY_INTERFACE_MODE_SGMII_2500:
  924. fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
  925. break;
  926. default:
  927. break;
  928. }
  929. /* init global mac structure */
  930. ret = fm_eth_init_mac(fm_eth, reg);
  931. if (ret)
  932. return ret;
  933. /* startup the FM im */
  934. ret = fm_eth_startup(fm_eth);
  935. if (!ret)
  936. ret = init_phy(fm_eth);
  937. return ret;
  938. ports_ref_failure:
  939. printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
  940. return -ENOENT;
  941. }
  942. static int fm_eth_remove(struct udevice *dev)
  943. {
  944. return 0;
  945. }
  946. static const struct eth_ops fm_eth_ops = {
  947. .start = fm_eth_open,
  948. .send = fm_eth_send,
  949. .recv = fm_eth_recv,
  950. .free_pkt = fm_eth_free_pkt,
  951. .stop = fm_eth_halt,
  952. };
  953. static const struct udevice_id fm_eth_ids[] = {
  954. #ifdef CONFIG_SYS_FMAN_V3
  955. { .compatible = "fsl,fman-memac", .data = FM_MEMAC },
  956. #else
  957. { .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
  958. { .compatible = "fsl,fman-xgec", .data = FM_TGEC },
  959. #endif
  960. {}
  961. };
  962. U_BOOT_DRIVER(eth_fman) = {
  963. .name = "eth_fman",
  964. .id = UCLASS_ETH,
  965. .of_match = fm_eth_ids,
  966. .bind = fm_eth_bind,
  967. .probe = fm_eth_probe,
  968. .remove = fm_eth_remove,
  969. .ops = &fm_eth_ops,
  970. .priv_auto = sizeof(struct fm_eth),
  971. .plat_auto = sizeof(struct eth_pdata),
  972. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  973. };
  974. #endif /* CONFIG_DM_ETH */