swap_case.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PCI emulation device which swaps the case of text
  4. *
  5. * Copyright (c) 2014 Google, Inc
  6. * Written by Simon Glass <sjg@chromium.org>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <pci.h>
  13. #include <asm/test.h>
  14. #include <linux/ctype.h>
  15. /**
  16. * struct swap_case_plat - platform data for this device
  17. *
  18. * @command: Current PCI command value
  19. * @bar: Current base address values
  20. */
  21. struct swap_case_plat {
  22. u16 command;
  23. u32 bar[6];
  24. };
  25. enum {
  26. MEM_TEXT_SIZE = 0x100,
  27. };
  28. enum swap_case_op {
  29. OP_TO_LOWER,
  30. OP_TO_UPPER,
  31. OP_SWAP,
  32. };
  33. static struct pci_bar {
  34. int type;
  35. u32 size;
  36. } barinfo[] = {
  37. { PCI_BASE_ADDRESS_SPACE_IO, 1 },
  38. { PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE },
  39. { 0, 0 },
  40. { 0, 0 },
  41. { 0, 0 },
  42. { 0, 0 },
  43. };
  44. struct swap_case_priv {
  45. enum swap_case_op op;
  46. char mem_text[MEM_TEXT_SIZE];
  47. };
  48. static int sandbox_swap_case_use_ea(const struct udevice *dev)
  49. {
  50. return !!ofnode_get_property(dev_ofnode(dev), "use-ea", NULL);
  51. }
  52. /* Please keep these macros in sync with ea_regs below */
  53. #define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4)
  54. #define PCI_CAP_ID_EA_ENTRY_CNT 4
  55. /* Hardcoded EA structure, excluding 1st DW. */
  56. static const u32 ea_regs[] = {
  57. /* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */
  58. (2 << 8) | 2,
  59. PCI_CAP_EA_BASE_LO0,
  60. 0,
  61. /* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */
  62. (1 << 4) | 2,
  63. PCI_CAP_EA_BASE_LO1,
  64. MEM_TEXT_SIZE - 1,
  65. /* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */
  66. (2 << 4) | 3,
  67. PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64,
  68. PCI_CAP_EA_SIZE_LO,
  69. PCI_CAP_EA_BASE_HI2,
  70. /* BEI=4, ES=4, BAR4 64b Base + 64b MaxOffset */
  71. (4 << 4) | 4,
  72. PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64,
  73. PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64,
  74. PCI_CAP_EA_BASE_HI4,
  75. PCI_CAP_EA_SIZE_HI,
  76. };
  77. static int sandbox_swap_case_read_ea(const struct udevice *emul, uint offset,
  78. ulong *valuep, enum pci_size_t size)
  79. {
  80. u32 reg;
  81. offset = offset - PCI_CAP_ID_EA_OFFSET - 4;
  82. reg = ea_regs[offset >> 2];
  83. reg >>= (offset % 4) * 8;
  84. *valuep = reg;
  85. return 0;
  86. }
  87. static int sandbox_swap_case_read_config(const struct udevice *emul,
  88. uint offset, ulong *valuep,
  89. enum pci_size_t size)
  90. {
  91. struct swap_case_plat *plat = dev_get_plat(emul);
  92. /*
  93. * The content of the EA capability structure is handled elsewhere to
  94. * keep the switch/case below sane
  95. */
  96. if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT &&
  97. offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE)
  98. return sandbox_swap_case_read_ea(emul, offset, valuep, size);
  99. switch (offset) {
  100. case PCI_COMMAND:
  101. *valuep = plat->command;
  102. break;
  103. case PCI_HEADER_TYPE:
  104. *valuep = 0;
  105. break;
  106. case PCI_VENDOR_ID:
  107. *valuep = SANDBOX_PCI_VENDOR_ID;
  108. break;
  109. case PCI_DEVICE_ID:
  110. *valuep = SANDBOX_PCI_SWAP_CASE_EMUL_ID;
  111. break;
  112. case PCI_CLASS_DEVICE:
  113. if (size == PCI_SIZE_8) {
  114. *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
  115. } else {
  116. *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
  117. SANDBOX_PCI_CLASS_SUB_CODE;
  118. }
  119. break;
  120. case PCI_CLASS_CODE:
  121. *valuep = SANDBOX_PCI_CLASS_CODE;
  122. break;
  123. case PCI_BASE_ADDRESS_0:
  124. case PCI_BASE_ADDRESS_1:
  125. case PCI_BASE_ADDRESS_2:
  126. case PCI_BASE_ADDRESS_3:
  127. case PCI_BASE_ADDRESS_4:
  128. case PCI_BASE_ADDRESS_5: {
  129. int barnum;
  130. u32 *bar;
  131. barnum = pci_offset_to_barnum(offset);
  132. bar = &plat->bar[barnum];
  133. *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
  134. barinfo[barnum].size);
  135. break;
  136. }
  137. case PCI_CAPABILITY_LIST:
  138. *valuep = PCI_CAP_ID_PM_OFFSET;
  139. break;
  140. case PCI_CAP_ID_PM_OFFSET:
  141. *valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM;
  142. break;
  143. case PCI_CAP_ID_PM_OFFSET + PCI_CAP_LIST_NEXT:
  144. *valuep = PCI_CAP_ID_EXP_OFFSET;
  145. break;
  146. case PCI_CAP_ID_EXP_OFFSET:
  147. *valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP;
  148. break;
  149. case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT:
  150. *valuep = PCI_CAP_ID_MSIX_OFFSET;
  151. break;
  152. case PCI_CAP_ID_MSIX_OFFSET:
  153. if (sandbox_swap_case_use_ea(emul))
  154. *valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX;
  155. else
  156. *valuep = PCI_CAP_ID_MSIX;
  157. break;
  158. case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT:
  159. if (sandbox_swap_case_use_ea(emul))
  160. *valuep = PCI_CAP_ID_EA_OFFSET;
  161. else
  162. *valuep = 0;
  163. break;
  164. case PCI_CAP_ID_EA_OFFSET:
  165. *valuep = (PCI_CAP_ID_EA_ENTRY_CNT << 16) | PCI_CAP_ID_EA;
  166. break;
  167. case PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT:
  168. *valuep = 0;
  169. break;
  170. case PCI_EXT_CAP_ID_ERR_OFFSET:
  171. *valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR;
  172. break;
  173. case PCI_EXT_CAP_ID_VC_OFFSET:
  174. *valuep = (PCI_EXT_CAP_ID_DSN_OFFSET << 20) | PCI_EXT_CAP_ID_VC;
  175. break;
  176. case PCI_EXT_CAP_ID_DSN_OFFSET:
  177. *valuep = PCI_EXT_CAP_ID_DSN;
  178. break;
  179. }
  180. return 0;
  181. }
  182. static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
  183. ulong value, enum pci_size_t size)
  184. {
  185. struct swap_case_plat *plat = dev_get_plat(emul);
  186. switch (offset) {
  187. case PCI_COMMAND:
  188. plat->command = value;
  189. break;
  190. case PCI_BASE_ADDRESS_0:
  191. case PCI_BASE_ADDRESS_1: {
  192. int barnum;
  193. u32 *bar;
  194. barnum = pci_offset_to_barnum(offset);
  195. bar = &plat->bar[barnum];
  196. debug("w bar %d=%lx\n", barnum, value);
  197. *bar = value;
  198. /* space indicator (bit#0) is read-only */
  199. *bar |= barinfo[barnum].type;
  200. break;
  201. }
  202. }
  203. return 0;
  204. }
  205. static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr,
  206. int *barnump, unsigned int *offsetp)
  207. {
  208. struct swap_case_plat *plat = dev_get_plat(emul);
  209. int barnum;
  210. for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
  211. unsigned int size = barinfo[barnum].size;
  212. u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
  213. if (addr >= base && addr < base + size) {
  214. *barnump = barnum;
  215. *offsetp = addr - base;
  216. return 0;
  217. }
  218. }
  219. *barnump = -1;
  220. return -ENOENT;
  221. }
  222. static void sandbox_swap_case_do_op(enum swap_case_op op, char *str, int len)
  223. {
  224. for (; len > 0; len--, str++) {
  225. switch (op) {
  226. case OP_TO_UPPER:
  227. *str = toupper(*str);
  228. break;
  229. case OP_TO_LOWER:
  230. *str = tolower(*str);
  231. break;
  232. case OP_SWAP:
  233. if (isupper(*str))
  234. *str = tolower(*str);
  235. else
  236. *str = toupper(*str);
  237. break;
  238. }
  239. }
  240. }
  241. static int sandbox_swap_case_read_io(struct udevice *dev, unsigned int addr,
  242. ulong *valuep, enum pci_size_t size)
  243. {
  244. struct swap_case_priv *priv = dev_get_priv(dev);
  245. unsigned int offset;
  246. int barnum;
  247. int ret;
  248. ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
  249. if (ret)
  250. return ret;
  251. if (barnum == 0 && offset == 0)
  252. *valuep = (*valuep & ~0xff) | priv->op;
  253. return 0;
  254. }
  255. static int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr,
  256. ulong value, enum pci_size_t size)
  257. {
  258. struct swap_case_priv *priv = dev_get_priv(dev);
  259. unsigned int offset;
  260. int barnum;
  261. int ret;
  262. ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
  263. if (ret)
  264. return ret;
  265. if (barnum == 0 && offset == 0)
  266. priv->op = value;
  267. return 0;
  268. }
  269. static int pci_ea_bar2_magic = PCI_EA_BAR2_MAGIC;
  270. static int pci_ea_bar4_magic = PCI_EA_BAR4_MAGIC;
  271. static int sandbox_swap_case_map_physmem(struct udevice *dev,
  272. phys_addr_t addr, unsigned long *lenp, void **ptrp)
  273. {
  274. struct swap_case_priv *priv = dev_get_priv(dev);
  275. unsigned int offset, avail;
  276. int barnum;
  277. int ret;
  278. if (sandbox_swap_case_use_ea(dev)) {
  279. /*
  280. * only support mapping base address in EA test for now, we
  281. * don't handle mapping an offset inside a BAR. Seems good
  282. * enough for the current test.
  283. */
  284. switch (addr) {
  285. case (phys_addr_t)PCI_CAP_EA_BASE_LO0:
  286. *ptrp = &priv->op;
  287. *lenp = 4;
  288. break;
  289. case (phys_addr_t)PCI_CAP_EA_BASE_LO1:
  290. *ptrp = priv->mem_text;
  291. *lenp = barinfo[1].size - 1;
  292. break;
  293. case (phys_addr_t)((PCI_CAP_EA_BASE_HI2 << 32) |
  294. PCI_CAP_EA_BASE_LO2):
  295. *ptrp = &pci_ea_bar2_magic;
  296. *lenp = PCI_CAP_EA_SIZE_LO;
  297. break;
  298. case (phys_addr_t)((PCI_CAP_EA_BASE_HI4 << 32) |
  299. PCI_CAP_EA_BASE_LO4):
  300. *ptrp = &pci_ea_bar4_magic;
  301. *lenp = (PCI_CAP_EA_SIZE_HI << 32) |
  302. PCI_CAP_EA_SIZE_LO;
  303. break;
  304. default:
  305. return -ENOENT;
  306. }
  307. return 0;
  308. }
  309. ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
  310. if (ret)
  311. return ret;
  312. if (barnum == 1) {
  313. *ptrp = priv->mem_text + offset;
  314. avail = barinfo[1].size - offset;
  315. if (avail > barinfo[1].size)
  316. *lenp = 0;
  317. else
  318. *lenp = min(*lenp, (ulong)avail);
  319. return 0;
  320. }
  321. return -ENOENT;
  322. }
  323. static int sandbox_swap_case_unmap_physmem(struct udevice *dev,
  324. const void *vaddr, unsigned long len)
  325. {
  326. struct swap_case_priv *priv = dev_get_priv(dev);
  327. sandbox_swap_case_do_op(priv->op, (void *)vaddr, len);
  328. return 0;
  329. }
  330. static struct dm_pci_emul_ops sandbox_swap_case_emul_ops = {
  331. .read_config = sandbox_swap_case_read_config,
  332. .write_config = sandbox_swap_case_write_config,
  333. .read_io = sandbox_swap_case_read_io,
  334. .write_io = sandbox_swap_case_write_io,
  335. .map_physmem = sandbox_swap_case_map_physmem,
  336. .unmap_physmem = sandbox_swap_case_unmap_physmem,
  337. };
  338. static const struct udevice_id sandbox_swap_case_ids[] = {
  339. { .compatible = "sandbox,swap-case" },
  340. { }
  341. };
  342. U_BOOT_DRIVER(sandbox_swap_case_emul) = {
  343. .name = "sandbox_swap_case_emul",
  344. .id = UCLASS_PCI_EMUL,
  345. .of_match = sandbox_swap_case_ids,
  346. .ops = &sandbox_swap_case_emul_ops,
  347. .priv_auto = sizeof(struct swap_case_priv),
  348. .plat_auto = sizeof(struct swap_case_plat),
  349. };
  350. static struct pci_device_id sandbox_swap_case_supported[] = {
  351. { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_SWAP_CASE_EMUL_ID),
  352. SWAP_CASE_DRV_DATA },
  353. {},
  354. };
  355. U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported);