g12a.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 - BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <asm/arch/clock-g12a.h>
  10. #include <asm/io.h>
  11. #include <clk-uclass.h>
  12. #include <dm.h>
  13. #include <regmap.h>
  14. #include <syscon.h>
  15. #include <div64.h>
  16. #include <dt-bindings/clock/g12a-clkc.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/err.h>
  20. #include <linux/kernel.h>
  21. #include "clk_meson.h"
  22. /* This driver support only basic clock tree operations :
  23. * - Can calculate clock frequency on a limited tree
  24. * - Can Read muxes and basic dividers (0-based only)
  25. * - Can enable/disable gates with limited propagation
  26. * - Can reparent without propagation, only on muxes
  27. * - Can set rates without reparenting
  28. * This driver is adapted to what is actually supported by U-Boot
  29. */
  30. /* Only the clocks ids we don't want to expose, such as the internal muxes
  31. * and dividers of composite clocks, will remain defined here.
  32. */
  33. #define CLKID_MPEG_SEL 8
  34. #define CLKID_MPEG_DIV 9
  35. #define CLKID_SD_EMMC_A_CLK0_SEL 63
  36. #define CLKID_SD_EMMC_A_CLK0_DIV 64
  37. #define CLKID_SD_EMMC_B_CLK0_SEL 65
  38. #define CLKID_SD_EMMC_B_CLK0_DIV 66
  39. #define CLKID_SD_EMMC_C_CLK0_SEL 67
  40. #define CLKID_SD_EMMC_C_CLK0_DIV 68
  41. #define CLKID_MPLL0_DIV 69
  42. #define CLKID_MPLL1_DIV 70
  43. #define CLKID_MPLL2_DIV 71
  44. #define CLKID_MPLL3_DIV 72
  45. #define CLKID_MPLL_PREDIV 73
  46. #define CLKID_FCLK_DIV2_DIV 75
  47. #define CLKID_FCLK_DIV3_DIV 76
  48. #define CLKID_FCLK_DIV4_DIV 77
  49. #define CLKID_FCLK_DIV5_DIV 78
  50. #define CLKID_FCLK_DIV7_DIV 79
  51. #define CLKID_FCLK_DIV2P5_DIV 100
  52. #define CLKID_FIXED_PLL_DCO 101
  53. #define CLKID_SYS_PLL_DCO 102
  54. #define CLKID_GP0_PLL_DCO 103
  55. #define CLKID_HIFI_PLL_DCO 104
  56. #define CLKID_VPU_0_DIV 111
  57. #define CLKID_VPU_1_DIV 114
  58. #define CLKID_VAPB_0_DIV 118
  59. #define CLKID_VAPB_1_DIV 121
  60. #define CLKID_HDMI_PLL_DCO 125
  61. #define CLKID_HDMI_PLL_OD 126
  62. #define CLKID_HDMI_PLL_OD2 127
  63. #define CLKID_VID_PLL_SEL 130
  64. #define CLKID_VID_PLL_DIV 131
  65. #define CLKID_VCLK_SEL 132
  66. #define CLKID_VCLK2_SEL 133
  67. #define CLKID_VCLK_INPUT 134
  68. #define CLKID_VCLK2_INPUT 135
  69. #define CLKID_VCLK_DIV 136
  70. #define CLKID_VCLK2_DIV 137
  71. #define CLKID_VCLK_DIV2_EN 140
  72. #define CLKID_VCLK_DIV4_EN 141
  73. #define CLKID_VCLK_DIV6_EN 142
  74. #define CLKID_VCLK_DIV12_EN 143
  75. #define CLKID_VCLK2_DIV2_EN 144
  76. #define CLKID_VCLK2_DIV4_EN 145
  77. #define CLKID_VCLK2_DIV6_EN 146
  78. #define CLKID_VCLK2_DIV12_EN 147
  79. #define CLKID_CTS_ENCI_SEL 158
  80. #define CLKID_CTS_ENCP_SEL 159
  81. #define CLKID_CTS_VDAC_SEL 160
  82. #define CLKID_HDMI_TX_SEL 161
  83. #define CLKID_HDMI_SEL 166
  84. #define CLKID_HDMI_DIV 167
  85. #define CLKID_MALI_0_DIV 170
  86. #define CLKID_MALI_1_DIV 173
  87. #define CLKID_XTAL 0x10000000
  88. #define XTAL_RATE 24000000
  89. struct meson_clk {
  90. struct regmap *map;
  91. };
  92. static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
  93. static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  94. ulong current_rate);
  95. static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  96. unsigned long parent_id);
  97. static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
  98. static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  99. ulong rate, ulong current_rate);
  100. static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
  101. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
  102. #define NUM_CLKS 178
  103. static struct meson_gate gates[NUM_CLKS] = {
  104. /* Everything Else (EE) domain gates */
  105. MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
  106. MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
  107. MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
  108. MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14),
  109. MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 4),
  110. MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
  111. MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
  112. MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
  113. MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
  114. MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 25),
  115. MESON_GATE(CLKID_HTX_PCLK, HHI_GCLK_MPEG2, 4),
  116. MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
  117. MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
  118. /* Peripheral Gates */
  119. MESON_GATE(CLKID_FCLK_DIV2, HHI_FIX_PLL_CNTL1, 24),
  120. MESON_GATE(CLKID_FCLK_DIV3, HHI_FIX_PLL_CNTL1, 20),
  121. MESON_GATE(CLKID_FCLK_DIV4, HHI_FIX_PLL_CNTL1, 21),
  122. MESON_GATE(CLKID_FCLK_DIV5, HHI_FIX_PLL_CNTL1, 22),
  123. MESON_GATE(CLKID_FCLK_DIV7, HHI_FIX_PLL_CNTL1, 23),
  124. MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
  125. MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
  126. MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
  127. MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
  128. MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
  129. MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
  130. MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
  131. MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
  132. MESON_GATE(CLKID_HDMI, HHI_HDMI_CLK_CNTL, 8),
  133. };
  134. static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
  135. {
  136. struct meson_clk *priv = dev_get_priv(clk->dev);
  137. struct meson_gate *gate;
  138. debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
  139. /* Propagate through muxes */
  140. switch (id) {
  141. case CLKID_VPU:
  142. return meson_set_gate_by_id(clk,
  143. meson_mux_get_parent(clk, CLKID_VPU), on);
  144. case CLKID_VAPB_SEL:
  145. return meson_set_gate_by_id(clk,
  146. meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
  147. }
  148. if (id >= ARRAY_SIZE(gates))
  149. return -ENOENT;
  150. gate = &gates[id];
  151. if (gate->reg == 0)
  152. return 0;
  153. debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
  154. regmap_update_bits(priv->map, gate->reg,
  155. BIT(gate->bit), on ? BIT(gate->bit) : 0);
  156. /* Propagate to next gate(s) */
  157. switch (id) {
  158. case CLKID_VAPB:
  159. return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
  160. case CLKID_VAPB_0:
  161. return meson_set_gate_by_id(clk,
  162. meson_mux_get_parent(clk, CLKID_VAPB_0_SEL), on);
  163. case CLKID_VAPB_1:
  164. return meson_set_gate_by_id(clk,
  165. meson_mux_get_parent(clk, CLKID_VAPB_0_SEL), on);
  166. case CLKID_VPU_0:
  167. return meson_set_gate_by_id(clk,
  168. meson_mux_get_parent(clk, CLKID_VPU_0_SEL), on);
  169. case CLKID_VPU_1:
  170. return meson_set_gate_by_id(clk,
  171. meson_mux_get_parent(clk, CLKID_VPU_1_SEL), on);
  172. }
  173. return 0;
  174. }
  175. static int meson_clk_enable(struct clk *clk)
  176. {
  177. return meson_set_gate_by_id(clk, clk->id, true);
  178. }
  179. static int meson_clk_disable(struct clk *clk)
  180. {
  181. return meson_set_gate_by_id(clk, clk->id, false);
  182. }
  183. static struct parm meson_vpu_0_div_parm = {
  184. HHI_VPU_CLK_CNTL, 0, 7,
  185. };
  186. int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
  187. static struct parm meson_vpu_1_div_parm = {
  188. HHI_VPU_CLK_CNTL, 16, 7,
  189. };
  190. int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
  191. static struct parm meson_vapb_0_div_parm = {
  192. HHI_VAPBCLK_CNTL, 0, 7,
  193. };
  194. int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
  195. static struct parm meson_vapb_1_div_parm = {
  196. HHI_VAPBCLK_CNTL, 16, 7,
  197. };
  198. int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
  199. static struct parm meson_hdmi_div_parm = {
  200. HHI_HDMI_CLK_CNTL, 0, 7,
  201. };
  202. int meson_hdmi_div_parent = CLKID_HDMI_SEL;
  203. static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
  204. {
  205. struct meson_clk *priv = dev_get_priv(clk->dev);
  206. unsigned int rate, parent_rate;
  207. struct parm *parm;
  208. int parent;
  209. uint reg;
  210. switch (id) {
  211. case CLKID_VPU_0_DIV:
  212. parm = &meson_vpu_0_div_parm;
  213. parent = meson_vpu_0_div_parent;
  214. break;
  215. case CLKID_VPU_1_DIV:
  216. parm = &meson_vpu_1_div_parm;
  217. parent = meson_vpu_1_div_parent;
  218. break;
  219. case CLKID_VAPB_0_DIV:
  220. parm = &meson_vapb_0_div_parm;
  221. parent = meson_vapb_0_div_parent;
  222. break;
  223. case CLKID_VAPB_1_DIV:
  224. parm = &meson_vapb_1_div_parm;
  225. parent = meson_vapb_1_div_parent;
  226. break;
  227. case CLKID_HDMI_DIV:
  228. parm = &meson_hdmi_div_parm;
  229. parent = meson_hdmi_div_parent;
  230. break;
  231. default:
  232. return -ENOENT;
  233. }
  234. regmap_read(priv->map, parm->reg_off, &reg);
  235. reg = PARM_GET(parm->width, parm->shift, reg);
  236. debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
  237. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  238. if (IS_ERR_VALUE(parent_rate))
  239. return parent_rate;
  240. debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
  241. rate = parent_rate / (reg + 1);
  242. debug("%s: rate of %ld is %d\n", __func__, id, rate);
  243. return rate;
  244. }
  245. static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  246. ulong current_rate)
  247. {
  248. struct meson_clk *priv = dev_get_priv(clk->dev);
  249. unsigned int new_div = -EINVAL;
  250. unsigned long parent_rate;
  251. struct parm *parm;
  252. int parent;
  253. int ret;
  254. if (current_rate == rate)
  255. return 0;
  256. debug("%s: setting rate of %ld from %ld to %ld\n",
  257. __func__, id, current_rate, rate);
  258. switch (id) {
  259. case CLKID_VPU_0_DIV:
  260. parm = &meson_vpu_0_div_parm;
  261. parent = meson_vpu_0_div_parent;
  262. break;
  263. case CLKID_VPU_1_DIV:
  264. parm = &meson_vpu_1_div_parm;
  265. parent = meson_vpu_1_div_parent;
  266. break;
  267. case CLKID_VAPB_0_DIV:
  268. parm = &meson_vapb_0_div_parm;
  269. parent = meson_vapb_0_div_parent;
  270. break;
  271. case CLKID_VAPB_1_DIV:
  272. parm = &meson_vapb_1_div_parm;
  273. parent = meson_vapb_1_div_parent;
  274. break;
  275. case CLKID_HDMI_DIV:
  276. parm = &meson_hdmi_div_parm;
  277. parent = meson_hdmi_div_parent;
  278. break;
  279. default:
  280. return -ENOENT;
  281. }
  282. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  283. if (IS_ERR_VALUE(parent_rate))
  284. return parent_rate;
  285. debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
  286. /* If can't divide, set parent instead */
  287. if (!parent_rate || rate > parent_rate)
  288. return meson_clk_set_rate_by_id(clk, parent, rate,
  289. current_rate);
  290. new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
  291. debug("%s: new div of %ld is %d\n", __func__, id, new_div);
  292. /* If overflow, try to set parent rate and retry */
  293. if (!new_div || new_div > (1 << parm->width)) {
  294. ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
  295. if (IS_ERR_VALUE(ret))
  296. return ret;
  297. parent_rate = meson_clk_get_rate_by_id(clk, parent);
  298. if (IS_ERR_VALUE(parent_rate))
  299. return parent_rate;
  300. new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
  301. debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
  302. if (!new_div || new_div > (1 << parm->width))
  303. return -EINVAL;
  304. }
  305. debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
  306. regmap_update_bits(priv->map, parm->reg_off,
  307. SETPMASK(parm->width, parm->shift),
  308. (new_div - 1) << parm->shift);
  309. debug("%s: new rate of %ld is %ld\n",
  310. __func__, id, meson_div_get_rate(clk, id));
  311. return 0;
  312. }
  313. static struct parm meson_vpu_mux_parm = {
  314. HHI_VPU_CLK_CNTL, 31, 1,
  315. };
  316. int meson_vpu_mux_parents[] = {
  317. CLKID_VPU_0,
  318. CLKID_VPU_1,
  319. };
  320. static struct parm meson_vpu_0_mux_parm = {
  321. HHI_VPU_CLK_CNTL, 9, 3,
  322. };
  323. static struct parm meson_vpu_1_mux_parm = {
  324. HHI_VPU_CLK_CNTL, 25, 3,
  325. };
  326. static int meson_vpu_0_1_mux_parents[] = {
  327. CLKID_FCLK_DIV3,
  328. CLKID_FCLK_DIV4,
  329. CLKID_FCLK_DIV5,
  330. CLKID_FCLK_DIV7,
  331. -ENOENT,
  332. -ENOENT,
  333. -ENOENT,
  334. -ENOENT,
  335. };
  336. static struct parm meson_vapb_sel_mux_parm = {
  337. HHI_VAPBCLK_CNTL, 31, 1,
  338. };
  339. int meson_vapb_sel_mux_parents[] = {
  340. CLKID_VAPB_0,
  341. CLKID_VAPB_1,
  342. };
  343. static struct parm meson_vapb_0_mux_parm = {
  344. HHI_VAPBCLK_CNTL, 9, 2,
  345. };
  346. static struct parm meson_vapb_1_mux_parm = {
  347. HHI_VAPBCLK_CNTL, 25, 2,
  348. };
  349. static int meson_vapb_0_1_mux_parents[] = {
  350. CLKID_FCLK_DIV4,
  351. CLKID_FCLK_DIV3,
  352. CLKID_FCLK_DIV5,
  353. CLKID_FCLK_DIV7,
  354. };
  355. static struct parm meson_hdmi_mux_parm = {
  356. HHI_HDMI_CLK_CNTL, 9, 2,
  357. };
  358. static int meson_hdmi_mux_parents[] = {
  359. CLKID_XTAL,
  360. CLKID_FCLK_DIV4,
  361. CLKID_FCLK_DIV3,
  362. CLKID_FCLK_DIV5,
  363. };
  364. static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
  365. {
  366. struct meson_clk *priv = dev_get_priv(clk->dev);
  367. struct parm *parm;
  368. int *parents;
  369. uint reg;
  370. switch (id) {
  371. case CLKID_VPU:
  372. parm = &meson_vpu_mux_parm;
  373. parents = meson_vpu_mux_parents;
  374. break;
  375. case CLKID_VPU_0_SEL:
  376. parm = &meson_vpu_0_mux_parm;
  377. parents = meson_vpu_0_1_mux_parents;
  378. break;
  379. case CLKID_VPU_1_SEL:
  380. parm = &meson_vpu_1_mux_parm;
  381. parents = meson_vpu_0_1_mux_parents;
  382. break;
  383. case CLKID_VAPB_SEL:
  384. parm = &meson_vapb_sel_mux_parm;
  385. parents = meson_vapb_sel_mux_parents;
  386. break;
  387. case CLKID_VAPB_0_SEL:
  388. parm = &meson_vapb_0_mux_parm;
  389. parents = meson_vapb_0_1_mux_parents;
  390. break;
  391. case CLKID_VAPB_1_SEL:
  392. parm = &meson_vapb_1_mux_parm;
  393. parents = meson_vapb_0_1_mux_parents;
  394. break;
  395. case CLKID_HDMI_SEL:
  396. parm = &meson_hdmi_mux_parm;
  397. parents = meson_hdmi_mux_parents;
  398. break;
  399. default:
  400. return -ENOENT;
  401. }
  402. regmap_read(priv->map, parm->reg_off, &reg);
  403. reg = PARM_GET(parm->width, parm->shift, reg);
  404. debug("%s: parent of %ld is %d (%d)\n",
  405. __func__, id, parents[reg], reg);
  406. return parents[reg];
  407. }
  408. static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  409. unsigned long parent_id)
  410. {
  411. unsigned long cur_parent = meson_mux_get_parent(clk, id);
  412. struct meson_clk *priv = dev_get_priv(clk->dev);
  413. unsigned int new_index = -EINVAL;
  414. struct parm *parm;
  415. int *parents;
  416. int i;
  417. if (IS_ERR_VALUE(cur_parent))
  418. return cur_parent;
  419. debug("%s: setting parent of %ld from %ld to %ld\n",
  420. __func__, id, cur_parent, parent_id);
  421. if (cur_parent == parent_id)
  422. return 0;
  423. switch (id) {
  424. case CLKID_VPU:
  425. parm = &meson_vpu_mux_parm;
  426. parents = meson_vpu_mux_parents;
  427. break;
  428. case CLKID_VPU_0_SEL:
  429. parm = &meson_vpu_0_mux_parm;
  430. parents = meson_vpu_0_1_mux_parents;
  431. break;
  432. case CLKID_VPU_1_SEL:
  433. parm = &meson_vpu_1_mux_parm;
  434. parents = meson_vpu_0_1_mux_parents;
  435. break;
  436. case CLKID_VAPB_SEL:
  437. parm = &meson_vapb_sel_mux_parm;
  438. parents = meson_vapb_sel_mux_parents;
  439. break;
  440. case CLKID_VAPB_0_SEL:
  441. parm = &meson_vapb_0_mux_parm;
  442. parents = meson_vapb_0_1_mux_parents;
  443. break;
  444. case CLKID_VAPB_1_SEL:
  445. parm = &meson_vapb_1_mux_parm;
  446. parents = meson_vapb_0_1_mux_parents;
  447. break;
  448. case CLKID_HDMI_SEL:
  449. parm = &meson_hdmi_mux_parm;
  450. parents = meson_hdmi_mux_parents;
  451. break;
  452. default:
  453. /* Not a mux */
  454. return -ENOENT;
  455. }
  456. for (i = 0 ; i < (1 << parm->width) ; ++i) {
  457. if (parents[i] == parent_id)
  458. new_index = i;
  459. }
  460. if (IS_ERR_VALUE(new_index))
  461. return new_index;
  462. debug("%s: new index of %ld is %d\n", __func__, id, new_index);
  463. regmap_update_bits(priv->map, parm->reg_off,
  464. SETPMASK(parm->width, parm->shift),
  465. new_index << parm->shift);
  466. debug("%s: new parent of %ld is %ld\n",
  467. __func__, id, meson_mux_get_parent(clk, id));
  468. return 0;
  469. }
  470. static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
  471. {
  472. int parent = meson_mux_get_parent(clk, id);
  473. if (IS_ERR_VALUE(parent))
  474. return parent;
  475. return meson_clk_get_rate_by_id(clk, parent);
  476. }
  477. static unsigned long meson_clk81_get_rate(struct clk *clk)
  478. {
  479. struct meson_clk *priv = dev_get_priv(clk->dev);
  480. unsigned long parent_rate;
  481. uint reg;
  482. int parents[] = {
  483. CLKID_XTAL,
  484. -1,
  485. CLKID_FCLK_DIV7,
  486. CLKID_MPLL1,
  487. CLKID_MPLL2,
  488. CLKID_FCLK_DIV4,
  489. CLKID_FCLK_DIV3,
  490. CLKID_FCLK_DIV5
  491. };
  492. /* mux */
  493. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  494. reg = (reg >> 12) & 7;
  495. switch (reg) {
  496. case 1:
  497. return -ENOENT;
  498. default:
  499. parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
  500. }
  501. /* divider */
  502. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  503. reg = reg & ((1 << 7) - 1);
  504. return parent_rate / reg;
  505. }
  506. static long mpll_rate_from_params(unsigned long parent_rate,
  507. unsigned long sdm,
  508. unsigned long n2)
  509. {
  510. unsigned long divisor = (SDM_DEN * n2) + sdm;
  511. if (n2 < N2_MIN)
  512. return -EINVAL;
  513. return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
  514. }
  515. static struct parm meson_mpll0_parm[2] = {
  516. {HHI_MPLL_CNTL1, 0, 14}, /* psdm */
  517. {HHI_MPLL_CNTL1, 20, 9}, /* pn2 */
  518. };
  519. static struct parm meson_mpll1_parm[2] = {
  520. {HHI_MPLL_CNTL3, 0, 14}, /* psdm */
  521. {HHI_MPLL_CNTL3, 20, 9}, /* pn2 */
  522. };
  523. static struct parm meson_mpll2_parm[2] = {
  524. {HHI_MPLL_CNTL5, 0, 14}, /* psdm */
  525. {HHI_MPLL_CNTL5, 20, 9}, /* pn2 */
  526. };
  527. /*
  528. * MultiPhase Locked Loops are outputs from a PLL with additional frequency
  529. * scaling capabilities. MPLL rates are calculated as:
  530. *
  531. * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
  532. */
  533. static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
  534. {
  535. struct meson_clk *priv = dev_get_priv(clk->dev);
  536. struct parm *psdm, *pn2;
  537. unsigned long sdm, n2;
  538. unsigned long parent_rate;
  539. uint reg;
  540. switch (id) {
  541. case CLKID_MPLL0:
  542. psdm = &meson_mpll0_parm[0];
  543. pn2 = &meson_mpll0_parm[1];
  544. break;
  545. case CLKID_MPLL1:
  546. psdm = &meson_mpll1_parm[0];
  547. pn2 = &meson_mpll1_parm[1];
  548. break;
  549. case CLKID_MPLL2:
  550. psdm = &meson_mpll2_parm[0];
  551. pn2 = &meson_mpll2_parm[1];
  552. break;
  553. default:
  554. return -ENOENT;
  555. }
  556. parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
  557. if (IS_ERR_VALUE(parent_rate))
  558. return parent_rate;
  559. regmap_read(priv->map, psdm->reg_off, &reg);
  560. sdm = PARM_GET(psdm->width, psdm->shift, reg);
  561. regmap_read(priv->map, pn2->reg_off, &reg);
  562. n2 = PARM_GET(pn2->width, pn2->shift, reg);
  563. return mpll_rate_from_params(parent_rate, sdm, n2);
  564. }
  565. static struct parm meson_fixed_pll_parm[4] = {
  566. {HHI_FIX_PLL_CNTL0, 0, 9}, /* pm */
  567. {HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */
  568. {HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */
  569. {HHI_FIX_PLL_CNTL1, 0, 17}, /* pfrac */
  570. };
  571. static struct parm meson_sys_pll_parm[3] = {
  572. {HHI_SYS_PLL_CNTL0, 0, 9}, /* pm */
  573. {HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */
  574. {HHI_SYS_PLL_CNTL0, 16, 3}, /* pod */
  575. };
  576. static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
  577. {
  578. struct meson_clk *priv = dev_get_priv(clk->dev);
  579. struct parm *pm, *pn, *pod, *pfrac = NULL;
  580. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  581. u16 n, m, od, frac;
  582. ulong rate;
  583. uint reg;
  584. /*
  585. * FIXME: Between the unit conversion and the missing frac, we know
  586. * rate will be slightly off ...
  587. */
  588. switch (id) {
  589. case CLKID_FIXED_PLL:
  590. pm = &meson_fixed_pll_parm[0];
  591. pn = &meson_fixed_pll_parm[1];
  592. pod = &meson_fixed_pll_parm[2];
  593. pfrac = &meson_fixed_pll_parm[3];
  594. break;
  595. case CLKID_SYS_PLL:
  596. pm = &meson_sys_pll_parm[0];
  597. pn = &meson_sys_pll_parm[1];
  598. pod = &meson_sys_pll_parm[2];
  599. break;
  600. default:
  601. return -ENOENT;
  602. }
  603. regmap_read(priv->map, pn->reg_off, &reg);
  604. n = PARM_GET(pn->width, pn->shift, reg);
  605. regmap_read(priv->map, pm->reg_off, &reg);
  606. m = PARM_GET(pm->width, pm->shift, reg);
  607. regmap_read(priv->map, pod->reg_off, &reg);
  608. od = PARM_GET(pod->width, pod->shift, reg);
  609. rate = parent_rate_mhz * m;
  610. if (pfrac) {
  611. ulong frac_rate;
  612. regmap_read(priv->map, pfrac->reg_off, &reg);
  613. frac = PARM_GET(pfrac->width - 1, pfrac->shift, reg);
  614. frac_rate = DIV_ROUND_UP_ULL((u64)parent_rate_mhz * frac,
  615. 1 << (pfrac->width - 2));
  616. if (frac & BIT(pfrac->width - 1))
  617. rate -= frac_rate;
  618. else
  619. rate += frac_rate;
  620. }
  621. return (DIV_ROUND_UP_ULL(rate, n) >> od) * 1000000;
  622. }
  623. static struct parm meson_pcie_pll_parm[3] = {
  624. {HHI_PCIE_PLL_CNTL0, 0, 8}, /* pm */
  625. {HHI_PCIE_PLL_CNTL0, 10, 5}, /* pn */
  626. {HHI_PCIE_PLL_CNTL0, 16, 5}, /* pod */
  627. };
  628. static ulong meson_pcie_pll_get_rate(struct clk *clk)
  629. {
  630. struct meson_clk *priv = dev_get_priv(clk->dev);
  631. struct parm *pm, *pn, *pod;
  632. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  633. u16 n, m, od;
  634. uint reg;
  635. pm = &meson_pcie_pll_parm[0];
  636. pn = &meson_pcie_pll_parm[1];
  637. pod = &meson_pcie_pll_parm[2];
  638. regmap_read(priv->map, pn->reg_off, &reg);
  639. n = PARM_GET(pn->width, pn->shift, reg);
  640. regmap_read(priv->map, pm->reg_off, &reg);
  641. m = PARM_GET(pm->width, pm->shift, reg);
  642. regmap_read(priv->map, pod->reg_off, &reg);
  643. od = PARM_GET(pod->width, pod->shift, reg);
  644. return ((parent_rate_mhz * m / n) / 2 / od / 2) * 1000000;
  645. }
  646. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
  647. {
  648. ulong rate;
  649. switch (id) {
  650. case CLKID_XTAL:
  651. rate = XTAL_RATE;
  652. break;
  653. case CLKID_FIXED_PLL:
  654. case CLKID_SYS_PLL:
  655. rate = meson_pll_get_rate(clk, id);
  656. break;
  657. case CLKID_FCLK_DIV2:
  658. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
  659. break;
  660. case CLKID_FCLK_DIV3:
  661. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
  662. break;
  663. case CLKID_FCLK_DIV4:
  664. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
  665. break;
  666. case CLKID_FCLK_DIV5:
  667. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
  668. break;
  669. case CLKID_FCLK_DIV7:
  670. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
  671. break;
  672. case CLKID_MPLL0:
  673. case CLKID_MPLL1:
  674. case CLKID_MPLL2:
  675. rate = meson_mpll_get_rate(clk, id);
  676. break;
  677. case CLKID_CLK81:
  678. rate = meson_clk81_get_rate(clk);
  679. break;
  680. case CLKID_PCIE_PLL:
  681. rate = meson_pcie_pll_get_rate(clk);
  682. break;
  683. case CLKID_VPU_0:
  684. rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
  685. break;
  686. case CLKID_VPU_1:
  687. rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
  688. break;
  689. case CLKID_VAPB:
  690. rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
  691. break;
  692. case CLKID_VAPB_0:
  693. rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
  694. break;
  695. case CLKID_VAPB_1:
  696. rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
  697. break;
  698. case CLKID_HDMI:
  699. rate = meson_div_get_rate(clk, CLKID_HDMI_DIV);
  700. break;
  701. case CLKID_VPU_0_DIV:
  702. case CLKID_VPU_1_DIV:
  703. case CLKID_VAPB_0_DIV:
  704. case CLKID_VAPB_1_DIV:
  705. case CLKID_HDMI_DIV:
  706. rate = meson_div_get_rate(clk, id);
  707. break;
  708. case CLKID_VPU:
  709. case CLKID_VPU_0_SEL:
  710. case CLKID_VPU_1_SEL:
  711. case CLKID_VAPB_SEL:
  712. case CLKID_VAPB_0_SEL:
  713. case CLKID_VAPB_1_SEL:
  714. case CLKID_HDMI_SEL:
  715. rate = meson_mux_get_rate(clk, id);
  716. break;
  717. default:
  718. if (gates[id].reg != 0) {
  719. /* a clock gate */
  720. rate = meson_clk81_get_rate(clk);
  721. break;
  722. }
  723. return -ENOENT;
  724. }
  725. debug("clock %lu has rate %lu\n", id, rate);
  726. return rate;
  727. }
  728. static ulong meson_clk_get_rate(struct clk *clk)
  729. {
  730. return meson_clk_get_rate_by_id(clk, clk->id);
  731. }
  732. static ulong meson_pcie_pll_set_rate(struct clk *clk, ulong rate)
  733. {
  734. struct meson_clk *priv = dev_get_priv(clk->dev);
  735. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x20090496);
  736. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x30090496);
  737. regmap_write(priv->map, HHI_PCIE_PLL_CNTL1, 0x00000000);
  738. regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001100);
  739. regmap_write(priv->map, HHI_PCIE_PLL_CNTL3, 0x10058e00);
  740. regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x000100c0);
  741. regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000048);
  742. regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000068);
  743. udelay(20);
  744. regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x008100c0);
  745. udelay(10);
  746. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x34090496);
  747. regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x14090496);
  748. udelay(10);
  749. regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001000);
  750. regmap_update_bits(priv->map, HHI_PCIE_PLL_CNTL0,
  751. 0x1f << 16, 9 << 16);
  752. return 100000000;
  753. }
  754. static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
  755. {
  756. return meson_mux_set_parent(clk, clk->id, parent->id);
  757. }
  758. static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  759. ulong rate, ulong current_rate)
  760. {
  761. if (current_rate == rate)
  762. return 0;
  763. switch (id) {
  764. /* Fixed clocks */
  765. case CLKID_FIXED_PLL:
  766. case CLKID_SYS_PLL:
  767. case CLKID_FCLK_DIV2:
  768. case CLKID_FCLK_DIV3:
  769. case CLKID_FCLK_DIV4:
  770. case CLKID_FCLK_DIV5:
  771. case CLKID_FCLK_DIV7:
  772. case CLKID_MPLL0:
  773. case CLKID_MPLL1:
  774. case CLKID_MPLL2:
  775. case CLKID_CLK81:
  776. if (current_rate != rate)
  777. return -EINVAL;
  778. case CLKID_PCIE_PLL:
  779. return meson_pcie_pll_set_rate(clk, rate);
  780. return 0;
  781. case CLKID_VPU:
  782. return meson_clk_set_rate_by_id(clk,
  783. meson_mux_get_parent(clk, CLKID_VPU), rate,
  784. current_rate);
  785. case CLKID_VAPB:
  786. case CLKID_VAPB_SEL:
  787. return meson_clk_set_rate_by_id(clk,
  788. meson_mux_get_parent(clk, CLKID_VAPB_SEL),
  789. rate, current_rate);
  790. case CLKID_VPU_0:
  791. return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
  792. current_rate);
  793. case CLKID_VPU_1:
  794. return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
  795. current_rate);
  796. case CLKID_VAPB_0:
  797. return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
  798. current_rate);
  799. case CLKID_VAPB_1:
  800. return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
  801. current_rate);
  802. case CLKID_VPU_0_DIV:
  803. case CLKID_VPU_1_DIV:
  804. case CLKID_VAPB_0_DIV:
  805. case CLKID_VAPB_1_DIV:
  806. case CLKID_HDMI_DIV:
  807. return meson_div_set_rate(clk, id, rate, current_rate);
  808. case CLKID_HDMI:
  809. return meson_clk_set_rate_by_id(clk, CLKID_HDMI_DIV,
  810. rate, current_rate);
  811. default:
  812. return -ENOENT;
  813. }
  814. return -EINVAL;
  815. }
  816. static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
  817. {
  818. ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
  819. int ret;
  820. if (IS_ERR_VALUE(current_rate))
  821. return current_rate;
  822. debug("%s: setting rate of %ld from %ld to %ld\n",
  823. __func__, clk->id, current_rate, rate);
  824. ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
  825. if (IS_ERR_VALUE(ret))
  826. return ret;
  827. debug("clock %lu has new rate %lu\n", clk->id,
  828. meson_clk_get_rate_by_id(clk, clk->id));
  829. return 0;
  830. }
  831. static int meson_clk_probe(struct udevice *dev)
  832. {
  833. struct meson_clk *priv = dev_get_priv(dev);
  834. priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
  835. if (IS_ERR(priv->map))
  836. return PTR_ERR(priv->map);
  837. /*
  838. * Depending on the boot src, the state of the MMC clock might
  839. * be different. Reset it to make sure we won't get stuck
  840. */
  841. regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
  842. regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
  843. debug("meson-clk-g12a: probed\n");
  844. return 0;
  845. }
  846. static struct clk_ops meson_clk_ops = {
  847. .disable = meson_clk_disable,
  848. .enable = meson_clk_enable,
  849. .get_rate = meson_clk_get_rate,
  850. .set_parent = meson_clk_set_parent,
  851. .set_rate = meson_clk_set_rate,
  852. };
  853. static const struct udevice_id meson_clk_ids[] = {
  854. { .compatible = "amlogic,g12a-clkc" },
  855. { .compatible = "amlogic,g12b-clkc" },
  856. { .compatible = "amlogic,sm1-clkc" },
  857. { }
  858. };
  859. U_BOOT_DRIVER(meson_clk_g12a) = {
  860. .name = "meson_clk_g12a",
  861. .id = UCLASS_CLK,
  862. .of_match = meson_clk_ids,
  863. .priv_auto = sizeof(struct meson_clk),
  864. .ops = &meson_clk_ops,
  865. .probe = meson_clk_probe,
  866. };