axg.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 - BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <asm/arch/clock-axg.h>
  10. #include <asm/io.h>
  11. #include <clk-uclass.h>
  12. #include <dm.h>
  13. #include <regmap.h>
  14. #include <syscon.h>
  15. #include <div64.h>
  16. #include <dt-bindings/clock/axg-clkc.h>
  17. #include <linux/bitops.h>
  18. #include "clk_meson.h"
  19. #include <linux/err.h>
  20. #define XTAL_RATE 24000000
  21. struct meson_clk {
  22. struct regmap *map;
  23. };
  24. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
  25. static struct meson_gate gates[] = {
  26. /* Everything Else (EE) domain gates */
  27. MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
  28. MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
  29. MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
  30. MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 15),
  31. MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
  32. MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
  33. MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
  34. MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
  35. /* Always On (AO) domain gates */
  36. MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
  37. /* PLL Gates */
  38. /* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
  39. MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
  40. /* CLKID_CLK81 is critical for the system */
  41. /* Peripheral Gates */
  42. MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
  43. MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
  44. };
  45. static int meson_set_gate(struct clk *clk, bool on)
  46. {
  47. struct meson_clk *priv = dev_get_priv(clk->dev);
  48. struct meson_gate *gate;
  49. if (clk->id >= ARRAY_SIZE(gates))
  50. return -ENOENT;
  51. gate = &gates[clk->id];
  52. if (gate->reg == 0)
  53. return 0;
  54. regmap_update_bits(priv->map, gate->reg,
  55. BIT(gate->bit), on ? BIT(gate->bit) : 0);
  56. return 0;
  57. }
  58. static int meson_clk_enable(struct clk *clk)
  59. {
  60. return meson_set_gate(clk, true);
  61. }
  62. static int meson_clk_disable(struct clk *clk)
  63. {
  64. return meson_set_gate(clk, false);
  65. }
  66. static unsigned long meson_clk81_get_rate(struct clk *clk)
  67. {
  68. struct meson_clk *priv = dev_get_priv(clk->dev);
  69. unsigned long parent_rate;
  70. uint reg;
  71. int parents[] = {
  72. -1,
  73. -1,
  74. CLKID_FCLK_DIV7,
  75. CLKID_MPLL1,
  76. CLKID_MPLL2,
  77. CLKID_FCLK_DIV4,
  78. CLKID_FCLK_DIV3,
  79. CLKID_FCLK_DIV5
  80. };
  81. /* mux */
  82. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  83. reg = (reg >> 12) & 7;
  84. switch (reg) {
  85. case 0:
  86. parent_rate = XTAL_RATE;
  87. break;
  88. case 1:
  89. return -ENOENT;
  90. default:
  91. parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
  92. }
  93. /* divider */
  94. regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
  95. reg = reg & ((1 << 7) - 1);
  96. return parent_rate / reg;
  97. }
  98. static long mpll_rate_from_params(unsigned long parent_rate,
  99. unsigned long sdm,
  100. unsigned long n2)
  101. {
  102. unsigned long divisor = (SDM_DEN * n2) + sdm;
  103. if (n2 < N2_MIN)
  104. return -EINVAL;
  105. return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
  106. }
  107. static struct parm meson_mpll0_parm[3] = {
  108. {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
  109. {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
  110. };
  111. static struct parm meson_mpll1_parm[3] = {
  112. {HHI_MPLL_CNTL8, 0, 14}, /* psdm */
  113. {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
  114. };
  115. static struct parm meson_mpll2_parm[3] = {
  116. {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
  117. {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
  118. };
  119. /*
  120. * MultiPhase Locked Loops are outputs from a PLL with additional frequency
  121. * scaling capabilities. MPLL rates are calculated as:
  122. *
  123. * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
  124. */
  125. static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
  126. {
  127. struct meson_clk *priv = dev_get_priv(clk->dev);
  128. struct parm *psdm, *pn2;
  129. unsigned long sdm, n2;
  130. unsigned long parent_rate;
  131. uint reg;
  132. switch (id) {
  133. case CLKID_MPLL0:
  134. psdm = &meson_mpll0_parm[0];
  135. pn2 = &meson_mpll0_parm[1];
  136. break;
  137. case CLKID_MPLL1:
  138. psdm = &meson_mpll1_parm[0];
  139. pn2 = &meson_mpll1_parm[1];
  140. break;
  141. case CLKID_MPLL2:
  142. psdm = &meson_mpll2_parm[0];
  143. pn2 = &meson_mpll2_parm[1];
  144. break;
  145. default:
  146. return -ENOENT;
  147. }
  148. parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
  149. if (IS_ERR_VALUE(parent_rate))
  150. return parent_rate;
  151. regmap_read(priv->map, psdm->reg_off, &reg);
  152. sdm = PARM_GET(psdm->width, psdm->shift, reg);
  153. regmap_read(priv->map, pn2->reg_off, &reg);
  154. n2 = PARM_GET(pn2->width, pn2->shift, reg);
  155. return mpll_rate_from_params(parent_rate, sdm, n2);
  156. }
  157. static struct parm meson_fixed_pll_parm[3] = {
  158. {HHI_MPLL_CNTL, 0, 9}, /* pm */
  159. {HHI_MPLL_CNTL, 9, 5}, /* pn */
  160. {HHI_MPLL_CNTL, 16, 2}, /* pod */
  161. };
  162. static struct parm meson_sys_pll_parm[3] = {
  163. {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
  164. {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
  165. {HHI_SYS_PLL_CNTL, 16, 2}, /* pod */
  166. };
  167. static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
  168. {
  169. struct meson_clk *priv = dev_get_priv(clk->dev);
  170. struct parm *pm, *pn, *pod;
  171. unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
  172. u16 n, m, od;
  173. uint reg;
  174. switch (id) {
  175. case CLKID_FIXED_PLL:
  176. pm = &meson_fixed_pll_parm[0];
  177. pn = &meson_fixed_pll_parm[1];
  178. pod = &meson_fixed_pll_parm[2];
  179. break;
  180. case CLKID_SYS_PLL:
  181. pm = &meson_sys_pll_parm[0];
  182. pn = &meson_sys_pll_parm[1];
  183. pod = &meson_sys_pll_parm[2];
  184. break;
  185. default:
  186. return -ENOENT;
  187. }
  188. regmap_read(priv->map, pn->reg_off, &reg);
  189. n = PARM_GET(pn->width, pn->shift, reg);
  190. regmap_read(priv->map, pm->reg_off, &reg);
  191. m = PARM_GET(pm->width, pm->shift, reg);
  192. regmap_read(priv->map, pod->reg_off, &reg);
  193. od = PARM_GET(pod->width, pod->shift, reg);
  194. return ((parent_rate_mhz * m / n) >> od) * 1000000;
  195. }
  196. static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
  197. {
  198. ulong rate;
  199. switch (id) {
  200. case CLKID_FIXED_PLL:
  201. case CLKID_SYS_PLL:
  202. rate = meson_pll_get_rate(clk, id);
  203. break;
  204. case CLKID_FCLK_DIV2:
  205. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
  206. break;
  207. case CLKID_FCLK_DIV3:
  208. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
  209. break;
  210. case CLKID_FCLK_DIV4:
  211. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
  212. break;
  213. case CLKID_FCLK_DIV5:
  214. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
  215. break;
  216. case CLKID_FCLK_DIV7:
  217. rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
  218. break;
  219. case CLKID_MPLL0:
  220. case CLKID_MPLL1:
  221. case CLKID_MPLL2:
  222. rate = meson_mpll_get_rate(clk, id);
  223. break;
  224. case CLKID_CLK81:
  225. rate = meson_clk81_get_rate(clk);
  226. break;
  227. default:
  228. if (gates[id].reg != 0) {
  229. /* a clock gate */
  230. rate = meson_clk81_get_rate(clk);
  231. break;
  232. }
  233. return -ENOENT;
  234. }
  235. debug("clock %lu has rate %lu\n", id, rate);
  236. return rate;
  237. }
  238. static ulong meson_clk_get_rate(struct clk *clk)
  239. {
  240. return meson_clk_get_rate_by_id(clk, clk->id);
  241. }
  242. static int meson_clk_probe(struct udevice *dev)
  243. {
  244. struct meson_clk *priv = dev_get_priv(dev);
  245. priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
  246. if (IS_ERR(priv->map))
  247. return PTR_ERR(priv->map);
  248. /*
  249. * Depending on the boot src, the state of the MMC clock might
  250. * be different. Reset it to make sure we won't get stuck
  251. */
  252. regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
  253. regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
  254. debug("meson-clk-axg: probed\n");
  255. return 0;
  256. }
  257. static struct clk_ops meson_clk_ops = {
  258. .disable = meson_clk_disable,
  259. .enable = meson_clk_enable,
  260. .get_rate = meson_clk_get_rate,
  261. };
  262. static const struct udevice_id meson_clk_ids[] = {
  263. { .compatible = "amlogic,axg-clkc" },
  264. { }
  265. };
  266. U_BOOT_DRIVER(meson_clk_axg) = {
  267. .name = "meson_clk_axg",
  268. .id = UCLASS_CLK,
  269. .of_match = meson_clk_ids,
  270. .priv_auto = sizeof(struct meson_clk),
  271. .ops = &meson_clk_ops,
  272. .probe = meson_clk_probe,
  273. };