pm9263.h 11 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian.pop@leadtechdesign.com>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. * Ilko Iliev <www.ronetix.at>
  6. *
  7. * Configuation settings for the RONETIX PM9263 board.
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #ifndef __CONFIG_H
  28. #define __CONFIG_H
  29. /* ARM asynchronous clock */
  30. #define AT91_CPU_NAME "AT91SAM9263"
  31. #define CONFIG_DISPLAY_BOARDINFO
  32. #define MASTER_PLL_DIV 15
  33. #define MASTER_PLL_MUL 162
  34. #define MAIN_PLL_DIV 2 /* 2 or 4 */
  35. #define AT91_MAIN_CLOCK 18432000
  36. #define CONFIG_SYS_HZ 1000000
  37. #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
  38. #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
  39. #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
  40. #define CONFIG_ARCH_CPU_INIT
  41. #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  42. /* clocks */
  43. #define CONFIG_SYS_MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */
  44. #define CONFIG_SYS_PLLAR_VAL \
  45. (0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  46. #if (MAIN_PLL_DIV == 2)
  47. /* PCK/2 = MCK Master Clock from PLLA */
  48. #define CONFIG_SYS_MCKR1_VAL 0x00000100
  49. /* PCK/2 = MCK Master Clock from PLLA */
  50. #define CONFIG_SYS_MCKR2_VAL 0x00000102
  51. #else
  52. /* PCK/4 = MCK Master Clock from PLLA */
  53. #define CONFIG_SYS_MCKR1_VAL 0x00000200
  54. /* PCK/4 = MCK Master Clock from PLLA */
  55. #define CONFIG_SYS_MCKR2_VAL 0x00000202
  56. #endif
  57. /* define PDC[31:16] as DATA[31:16] */
  58. #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
  59. /* no pull-up for D[31:16] */
  60. #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
  61. /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
  62. #define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A
  63. /* EBI1_CSA, 3.3v, no pull-ups */
  64. #define CONFIG_SYS_MATRIX_EBI1CSA_VAL 0x00010100
  65. /* SDRAM */
  66. /* SDRAMC_MR Mode register */
  67. #define CONFIG_SYS_SDRC_MR_VAL1 0
  68. /* SDRAMC_TR - Refresh Timer register */
  69. #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
  70. #define CONFIG_SYS_SDRC_CR_VAL 0x85227279 /*CL3*/
  71. /* Memory Device Register -> SDRAM */
  72. #define CONFIG_SYS_SDRC_MDR_VAL 0
  73. #define CONFIG_SYS_SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */
  74. #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
  75. #define CONFIG_SYS_SDRC_MR_VAL3 4 /* SDRC_MR */
  76. #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
  77. #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
  78. #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
  79. #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
  80. #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
  81. #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
  82. #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
  83. #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
  84. #define CONFIG_SYS_SDRC_MR_VAL4 3 /* SDRC_MR */
  85. #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
  86. #define CONFIG_SYS_SDRC_MR_VAL5 0 /* SDRC_MR */
  87. #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
  88. #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
  89. #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
  90. /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
  91. #define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */
  92. #define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */
  93. #define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */
  94. #define CONFIG_SYS_SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */
  95. /* setup SMC1, CS0 (PSRAM) - 16-bit */
  96. #define CONFIG_SYS_SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */
  97. #define CONFIG_SYS_SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */
  98. #define CONFIG_SYS_SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */
  99. #define CONFIG_SYS_SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */
  100. #define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */
  101. /* Watchdog */
  102. #define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */
  103. /* */
  104. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  105. #define CONFIG_SETUP_MEMORY_TAGS 1
  106. #define CONFIG_INITRD_TAG 1
  107. #undef CONFIG_SKIP_LOWLEVEL_INIT
  108. #undef CONFIG_SKIP_RELOCATE_UBOOT
  109. #define CONFIG_USER_LOWLEVEL_INIT 1
  110. /*
  111. * Hardware drivers
  112. */
  113. #define CONFIG_ATMEL_USART 1
  114. #undef CONFIG_USART0
  115. #undef CONFIG_USART1
  116. #undef CONFIG_USART2
  117. #define CONFIG_USART3 1 /* USART 3 is DBGU */
  118. /* LCD */
  119. #define CONFIG_LCD 1
  120. #define LCD_BPP LCD_COLOR8
  121. #define CONFIG_LCD_LOGO 1
  122. #undef LCD_TEST_PATTERN
  123. #define CONFIG_LCD_INFO 1
  124. #define CONFIG_LCD_INFO_BELOW_LOGO 1
  125. #define CONFIG_SYS_WHITE_ON_BLACK 1
  126. #define CONFIG_ATMEL_LCD 1
  127. #define CONFIG_ATMEL_LCD_BGR555 1
  128. #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
  129. #define CONFIG_LCD_IN_PSRAM 1
  130. /* LED */
  131. #define CONFIG_AT91_LED
  132. #define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
  133. #define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
  134. #define CONFIG_BOOTDELAY 3
  135. /*
  136. * BOOTP options
  137. */
  138. #define CONFIG_BOOTP_BOOTFILESIZE 1
  139. #define CONFIG_BOOTP_BOOTPATH 1
  140. #define CONFIG_BOOTP_GATEWAY 1
  141. #define CONFIG_BOOTP_HOSTNAME 1
  142. /*
  143. * Command line configuration.
  144. */
  145. #include <config_cmd_default.h>
  146. #undef CONFIG_CMD_BDI
  147. #undef CONFIG_CMD_IMI
  148. #undef CONFIG_CMD_AUTOSCRIPT
  149. #undef CONFIG_CMD_FPGA
  150. #undef CONFIG_CMD_LOADS
  151. #undef CONFIG_CMD_IMLS
  152. #define CONFIG_CMD_PING 1
  153. #define CONFIG_CMD_DHCP 1
  154. #define CONFIG_CMD_NAND 1
  155. #define CONFIG_CMD_USB 1
  156. /* SDRAM */
  157. #define CONFIG_NR_DRAM_BANKS 1
  158. #define PHYS_SDRAM 0x20000000
  159. #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
  160. /* DataFlash */
  161. #define CONFIG_ATMEL_DATAFLASH_SPI
  162. #define CONFIG_HAS_DATAFLASH 1
  163. #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
  164. #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
  165. #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
  166. #define AT91_SPI_CLK 15000000
  167. #define DATAFLASH_TCSS (0x1a << 16)
  168. #define DATAFLASH_TCHS (0x1 << 24)
  169. /* NOR flash, if populated */
  170. #define CONFIG_SYS_FLASH_CFI 1
  171. #define CONFIG_FLASH_CFI_DRIVER 1
  172. #define PHYS_FLASH_1 0x10000000
  173. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  174. #define CONFIG_SYS_MAX_FLASH_SECT 256
  175. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  176. /* NAND flash */
  177. #ifdef CONFIG_CMD_NAND
  178. #define CONFIG_NAND_ATMEL
  179. #define CONFIG_SYS_NAND_MAX_CHIPS 1
  180. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  181. #define CONFIG_SYS_NAND_BASE 0x40000000
  182. #define CONFIG_SYS_NAND_DBW_8 1
  183. /* our ALE is AD21 */
  184. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  185. /* our CLE is AD22 */
  186. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  187. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
  188. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
  189. #endif
  190. #define CONFIG_CMD_JFFS2 1
  191. #define CONFIG_JFFS2_CMDLINE 1
  192. #define CONFIG_JFFS2_NAND 1
  193. #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
  194. #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
  195. #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
  196. /* PSRAM */
  197. #define PHYS_PSRAM 0x70000000
  198. #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
  199. /* Ethernet */
  200. #define CONFIG_MACB 1
  201. #define CONFIG_RMII 1
  202. #define CONFIG_NET_MULTI 1
  203. #define CONFIG_NET_RETRY_COUNT 20
  204. #define CONFIG_RESET_PHY_R 1
  205. /* USB */
  206. #define CONFIG_USB_ATMEL
  207. #define CONFIG_USB_OHCI_NEW 1
  208. #define CONFIG_DOS_PARTITION 1
  209. #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
  210. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
  211. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
  212. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  213. #define CONFIG_USB_STORAGE 1
  214. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  215. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  216. #define CONFIG_SYS_MEMTEST_END 0x23e00000
  217. #define CONFIG_SYS_USE_FLASH 1
  218. #undef CONFIG_SYS_USE_DATAFLASH
  219. #undef CONFIG_SYS_USE_NANDFLASH
  220. #ifdef CONFIG_SYS_USE_DATAFLASH
  221. /* bootstrap + u-boot + env + linux in dataflash on CS0 */
  222. #define CONFIG_ENV_IS_IN_DATAFLASH
  223. #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
  224. #define CONFIG_ENV_OFFSET 0x4200
  225. #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
  226. #define CONFIG_ENV_SIZE 0x4200
  227. #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
  228. #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  229. "root=/dev/mtdblock0 " \
  230. "mtdparts=at91_nand:-(root) "\
  231. "rw rootfstype=jffs2"
  232. #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
  233. /* bootstrap + u-boot + env + linux in nandflash */
  234. #define CONFIG_ENV_IS_IN_NAND
  235. #define CONFIG_ENV_OFFSET 0x60000
  236. #define CONFIG_ENV_OFFSET_REDUND 0x80000
  237. #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
  238. #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
  239. #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
  240. "root=/dev/mtdblock5 " \
  241. "mtdparts=at91_nand:" \
  242. "128k(bootstrap)ro," \
  243. "256k(uboot)ro," \
  244. "128k(env1)ro," \
  245. "128k(env2)ro," \
  246. "2M(linux)," \
  247. "-(root) " \
  248. "rw rootfstype=jffs2"
  249. #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
  250. #define CONFIG_ENV_IS_IN_FLASH 1
  251. #define CONFIG_ENV_OFFSET 0x40000
  252. #define CONFIG_ENV_SECT_SIZE 0x10000
  253. #define CONFIG_ENV_SIZE 0x10000
  254. #define CONFIG_ENV_OVERWRITE 1
  255. /* JFFS Partition offset set */
  256. #define CONFIG_SYS_JFFS2_FIRST_BANK 0
  257. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  258. /* 512k reserved for u-boot */
  259. #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
  260. #define CONFIG_BOOTCOMMAND "run flashboot"
  261. #define CONFIG_ROOTPATH /ronetix/rootfs
  262. #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
  263. #define CONFIG_CON_ROT "fbcon=rotate:3 "
  264. #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
  265. CONFIG_CON_ROT
  266. #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
  267. #define MTDPARTS_DEFAULT \
  268. "mtdparts=physmap-flash.0:" \
  269. "256k(u-boot)ro," \
  270. "64k(u-boot-env)ro," \
  271. "1408k(kernel)," \
  272. "-(rootfs);" \
  273. "nand:-(nand)"
  274. #define CONFIG_EXTRA_ENV_SETTINGS \
  275. "mtdids=" MTDIDS_DEFAULT "\0" \
  276. "mtdparts=" MTDPARTS_DEFAULT "\0" \
  277. "partition=nand0,0\0" \
  278. "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
  279. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  280. CONFIG_CON_ROT \
  281. "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
  282. "addip=setenv bootargs $(bootargs) " \
  283. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
  284. ":$(hostname):eth0:off\0" \
  285. "ramboot=tftpboot 0x22000000 vmImage;" \
  286. "run ramargs;run addip;bootm 22000000\0" \
  287. "nfsboot=tftpboot 0x22000000 vmImage;" \
  288. "run nfsargs;run addip;bootm 22000000\0" \
  289. "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
  290. ""
  291. #else
  292. #error "Undefined memory device"
  293. #endif
  294. #define CONFIG_BAUDRATE 115200
  295. #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
  296. #define CONFIG_SYS_PROMPT "u-boot-pm9263> "
  297. #define CONFIG_SYS_CBSIZE 256
  298. #define CONFIG_SYS_MAXARGS 16
  299. #define CONFIG_SYS_PBSIZE \
  300. (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  301. #define CONFIG_SYS_LONGHELP 1
  302. #define CONFIG_CMDLINE_EDITING 1
  303. #define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
  304. /*
  305. * Size of malloc() pool
  306. */
  307. #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
  308. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
  309. #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
  310. #ifdef CONFIG_USE_IRQ
  311. #error CONFIG_USE_IRQ not supported
  312. #endif
  313. #endif