lowlevel_init.S 7.5 KB

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  1. /*
  2. * Memory Setup stuff - taken from blob memsetup.S
  3. *
  4. * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
  5. * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  6. *
  7. * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
  8. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #include <config.h>
  29. #include <version.h>
  30. #include <asm/arch/hardware.h>
  31. #include <asm/arch/at91_pmc.h>
  32. #include <asm/arch/at91_pio.h>
  33. #include <asm/arch/at91_rstc.h>
  34. #include <asm/arch/at91_wdt.h>
  35. #include <asm/arch/at91sam9_sdramc.h>
  36. #include <asm/arch/at91sam9_smc.h>
  37. #include <asm/arch/at91sam9263_matrix.h>
  38. _TEXT_BASE:
  39. .word TEXT_BASE
  40. .globl lowlevel_init
  41. .type lowlevel_init,function
  42. lowlevel_init:
  43. mov r5, pc /* r5 = POS1 + 4 current */
  44. POS1:
  45. ldr r0, =POS1 /* r0 = POS1 compile */
  46. ldr r2, _TEXT_BASE
  47. sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
  48. sub r5, r5, r0 /* r0 = TEXT_BASE-1 */
  49. sub r5, r5, #4 /* r1 = text base - current */
  50. /* memory control configuration 1 */
  51. ldr r0, =SMRDATA
  52. ldr r2, =SMRDATA1
  53. ldr r1, _TEXT_BASE
  54. sub r0, r0, r1
  55. sub r2, r2, r1
  56. add r0, r0, r5
  57. add r2, r2, r5
  58. 0:
  59. /* the address */
  60. ldr r1, [r0], #4
  61. /* the value */
  62. ldr r3, [r0], #4
  63. str r3, [r1]
  64. cmp r2, r0
  65. bne 0b
  66. /* ----------------------------------------------------------------------------
  67. * PMC Init Step 1.
  68. * ----------------------------------------------------------------------------
  69. * - Check if the PLL is already initialized
  70. * ----------------------------------------------------------------------------
  71. */
  72. ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
  73. ldr r0, [r1]
  74. and r0, r0, #3
  75. cmp r0, #0
  76. bne PLL_setup_end
  77. /* ---------------------------------------------------------------------------
  78. * - Enable the Main Oscillator
  79. * ---------------------------------------------------------------------------
  80. */
  81. ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
  82. ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
  83. ldr r0, =0x0000FF01
  84. str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */
  85. /* Reading the PMC Status to detect when the Main Oscillator is enabled */
  86. mov r4, #AT91_PMC_MOSCS
  87. MOSCS_Loop:
  88. ldr r3, [r2]
  89. and r3, r4, r3
  90. cmp r3, #AT91_PMC_MOSCS
  91. bne MOSCS_Loop
  92. /* ----------------------------------------------------------------------------
  93. * PMC Init Step 2.
  94. * ----------------------------------------------------------------------------
  95. * Setup PLLA
  96. * ----------------------------------------------------------------------------
  97. */
  98. ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
  99. ldr r0, =CONFIG_SYS_PLLAR_VAL
  100. str r0, [r1]
  101. /* Reading the PMC Status register to detect when the PLLA is locked */
  102. mov r4, #AT91_PMC_LOCKA
  103. MOSCS_Loop1:
  104. ldr r3, [r2]
  105. and r3, r4, r3
  106. cmp r3, #AT91_PMC_LOCKA
  107. bne MOSCS_Loop1
  108. /* ----------------------------------------------------------------------------
  109. * PMC Init Step 3.
  110. * ----------------------------------------------------------------------------
  111. * - Switch on the Main Oscillator 18.432 MHz
  112. * ----------------------------------------------------------------------------
  113. */
  114. ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
  115. /* -Master Clock Controller register PMC_MCKR */
  116. ldr r0, =CONFIG_SYS_MCKR1_VAL
  117. str r0, [r1]
  118. /* Reading the PMC Status to detect when the Master clock is ready */
  119. mov r4, #AT91_PMC_MCKRDY
  120. MCKRDY_Loop:
  121. ldr r3, [r2]
  122. and r3, r4, r3
  123. cmp r3, #AT91_PMC_MCKRDY
  124. bne MCKRDY_Loop
  125. ldr r0, =CONFIG_SYS_MCKR2_VAL
  126. str r0, [r1]
  127. /* Reading the PMC Status to detect when the Master clock is ready */
  128. mov r4, #AT91_PMC_MCKRDY
  129. MCKRDY_Loop1:
  130. ldr r3, [r2]
  131. and r3, r4, r3
  132. cmp r3, #AT91_PMC_MCKRDY
  133. bne MCKRDY_Loop1
  134. PLL_setup_end:
  135. /* ----------------------------------------------------------------------------
  136. * - memory control configuration 2
  137. * ----------------------------------------------------------------------------
  138. */
  139. ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
  140. ldr r1, [r0]
  141. cmp r1, #0
  142. bne SDRAM_setup_end
  143. ldr r0, =SMRDATA1
  144. ldr r2, =SMRDATA2
  145. ldr r1, _TEXT_BASE
  146. sub r0, r0, r1
  147. sub r2, r2, r1
  148. add r0, r0, r5
  149. add r2, r2, r5
  150. 2:
  151. /* the address */
  152. ldr r1, [r0], #4
  153. /* the value */
  154. ldr r3, [r0], #4
  155. str r3, [r1]
  156. cmp r2, r0
  157. bne 2b
  158. SDRAM_setup_end:
  159. /* everything is fine now */
  160. mov pc, lr
  161. .ltorg
  162. SMRDATA:
  163. .word (AT91_BASE_SYS + AT91_WDT_MR)
  164. .word CONFIG_SYS_WDTC_WDMR_VAL
  165. .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
  166. .word CONFIG_SYS_PIOD_PDR_VAL1
  167. .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
  168. .word CONFIG_SYS_PIOD_PPUDR_VAL
  169. .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
  170. .word CONFIG_SYS_PIOD_PPUDR_VAL
  171. .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
  172. .word CONFIG_SYS_MATRIX_EBI0CSA_VAL
  173. .word (AT91_BASE_SYS + AT91_MATRIX_EBI1CSA)
  174. .word CONFIG_SYS_MATRIX_EBI1CSA_VAL
  175. /* flash */
  176. .word (AT91_BASE_SYS + AT91_SMC_MODE(0))
  177. .word CONFIG_SYS_SMC0_CTRL0_VAL
  178. .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
  179. .word CONFIG_SYS_SMC0_CYCLE0_VAL
  180. .word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
  181. .word CONFIG_SYS_SMC0_PULSE0_VAL
  182. .word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
  183. .word CONFIG_SYS_SMC0_SETUP0_VAL
  184. /* PSRAM */
  185. .word (AT91_BASE_SYS + AT91_SMC1_MODE(0))
  186. .word CONFIG_SYS_SMC1_CTRL0_VAL
  187. .word (AT91_BASE_SYS + AT91_SMC1_CYCLE(0))
  188. .word CONFIG_SYS_SMC1_CYCLE0_VAL
  189. .word (AT91_BASE_SYS + AT91_SMC1_PULSE(0))
  190. .word CONFIG_SYS_SMC1_PULSE0_VAL
  191. .word (AT91_BASE_SYS + AT91_SMC1_SETUP(0))
  192. .word CONFIG_SYS_SMC1_SETUP0_VAL
  193. SMRDATA1:
  194. .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
  195. .word CONFIG_SYS_SDRC_MR_VAL1
  196. .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
  197. .word CONFIG_SYS_SDRC_TR_VAL1
  198. .word (AT91_BASE_SYS + AT91_SDRAMC_CR)
  199. .word CONFIG_SYS_SDRC_CR_VAL
  200. .word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
  201. .word CONFIG_SYS_SDRC_MDR_VAL
  202. .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
  203. .word CONFIG_SYS_SDRC_MR_VAL2
  204. .word AT91_SDRAM_BASE
  205. .word CONFIG_SYS_SDRAM_VAL1
  206. .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
  207. .word CONFIG_SYS_SDRC_MR_VAL3
  208. .word AT91_SDRAM_BASE
  209. .word CONFIG_SYS_SDRAM_VAL2
  210. .word AT91_SDRAM_BASE
  211. .word CONFIG_SYS_SDRAM_VAL3
  212. .word AT91_SDRAM_BASE
  213. .word CONFIG_SYS_SDRAM_VAL4
  214. .word AT91_SDRAM_BASE
  215. .word CONFIG_SYS_SDRAM_VAL5
  216. .word AT91_SDRAM_BASE
  217. .word CONFIG_SYS_SDRAM_VAL6
  218. .word AT91_SDRAM_BASE
  219. .word CONFIG_SYS_SDRAM_VAL7
  220. .word AT91_SDRAM_BASE
  221. .word CONFIG_SYS_SDRAM_VAL8
  222. .word AT91_SDRAM_BASE
  223. .word CONFIG_SYS_SDRAM_VAL9
  224. .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
  225. .word CONFIG_SYS_SDRC_MR_VAL4
  226. .word AT91_SDRAM_BASE
  227. .word CONFIG_SYS_SDRAM_VAL10
  228. .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
  229. .word CONFIG_SYS_SDRC_MR_VAL5
  230. .word AT91_SDRAM_BASE
  231. .word CONFIG_SYS_SDRAM_VAL11
  232. .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
  233. .word CONFIG_SYS_SDRC_TR_VAL2
  234. .word AT91_SDRAM_BASE
  235. .word CONFIG_SYS_SDRAM_VAL12
  236. /* User reset enable*/
  237. .word (AT91_BASE_SYS + AT91_RSTC_MR)
  238. .word CONFIG_SYS_RSTC_RMR_VAL
  239. #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
  240. /* MATRIX_MCFG - REMAP all masters */
  241. .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)
  242. .word 0x1FF
  243. #endif
  244. SMRDATA2:
  245. .word 0