tqm834x.c 11 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. */
  24. #include <common.h>
  25. #include <ioports.h>
  26. #include <mpc83xx.h>
  27. #include <asm/mpc8349_pci.h>
  28. #include <i2c.h>
  29. #include <spd.h>
  30. #include <miiphy.h>
  31. #include <asm-ppc/mmu.h>
  32. #include <pci.h>
  33. #define IOSYNC asm("eieio")
  34. #define ISYNC asm("isync")
  35. #define SYNC asm("sync")
  36. #define FPW FLASH_PORT_WIDTH
  37. #define FPWV FLASH_PORT_WIDTHV
  38. #define DDR_MAX_SIZE_PER_CS 0x20000000
  39. #if defined(DDR_CASLAT_20)
  40. #define TIMING_CASLAT TIMING_CFG1_CASLAT_20
  41. #define MODE_CASLAT DDR_MODE_CASLAT_20
  42. #else
  43. #define TIMING_CASLAT TIMING_CFG1_CASLAT_25
  44. #define MODE_CASLAT DDR_MODE_CASLAT_25
  45. #endif
  46. #define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
  47. CSCONFIG_COL_BIT_9)
  48. /* Global variable used to store detected number of banks */
  49. int tqm834x_num_flash_banks;
  50. /* External definitions */
  51. ulong flash_get_size (ulong base, int banknum);
  52. extern flash_info_t flash_info[];
  53. extern long spd_sdram (void);
  54. /* Local functions */
  55. static int detect_num_flash_banks(void);
  56. static long int get_ddr_bank_size(short cs, volatile long *base);
  57. static void set_cs_bounds(short cs, long base, long size);
  58. static void set_cs_config(short cs, long config);
  59. static void set_ddr_config(void);
  60. /* Local variable */
  61. static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  62. /**************************************************************************
  63. * Board initialzation after relocation to RAM. Used to detect the number
  64. * of Flash banks on TQM834x.
  65. */
  66. int board_early_init_r (void) {
  67. /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
  68. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  69. return 0;
  70. /* detect the number of Flash banks */
  71. return detect_num_flash_banks();
  72. }
  73. /**************************************************************************
  74. * DRAM initalization and size detection
  75. */
  76. long int initdram (int board_type)
  77. {
  78. long bank_size;
  79. long size;
  80. int cs;
  81. /* during size detection, set up the max DDRLAW size */
  82. im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
  83. im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
  84. /* set CS bounds to maximum size */
  85. for(cs = 0; cs < 4; ++cs) {
  86. set_cs_bounds(cs,
  87. CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
  88. DDR_MAX_SIZE_PER_CS);
  89. set_cs_config(cs, INITIAL_CS_CONFIG);
  90. }
  91. /* configure ddr controller */
  92. set_ddr_config();
  93. udelay(200);
  94. /* enable DDR controller */
  95. im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
  96. SDRAM_CFG_SREN |
  97. SDRAM_CFG_SDRAM_TYPE_DDR);
  98. SYNC;
  99. /* size detection */
  100. debug("\n");
  101. size = 0;
  102. for(cs = 0; cs < 4; ++cs) {
  103. debug("\nDetecting Bank%d\n", cs);
  104. bank_size = get_ddr_bank_size(cs,
  105. (volatile long*)(CFG_DDR_BASE + size));
  106. size += bank_size;
  107. debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
  108. /* exit if less than one bank */
  109. if(size < DDR_MAX_SIZE_PER_CS) break;
  110. }
  111. return size;
  112. }
  113. /**************************************************************************
  114. * checkboard()
  115. */
  116. int checkboard (void)
  117. {
  118. puts("Board: TQM834x\n");
  119. #ifdef CONFIG_PCI
  120. DECLARE_GLOBAL_DATA_PTR;
  121. volatile immap_t * immr;
  122. u32 w, f;
  123. immr = (immap_t *)CFG_IMMRBAR;
  124. if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
  125. printf("PCI: NOT in host mode..?!\n");
  126. return 0;
  127. }
  128. /* get bus width */
  129. w = 32;
  130. if (immr->reset.rcwh & RCWH_PCI64)
  131. w = 64;
  132. /* get clock */
  133. f = gd->pci_clk;
  134. printf("PCI1: %d bit, %d MHz\n", w, f / 1000000);
  135. #else
  136. printf("PCI: disabled\n");
  137. #endif
  138. return 0;
  139. }
  140. /**************************************************************************
  141. *
  142. * Local functions
  143. *
  144. *************************************************************************/
  145. /**************************************************************************
  146. * Detect the number of flash banks (1 or 2). Store it in
  147. * a global variable tqm834x_num_flash_banks.
  148. * Bank detection code based on the Monitor code.
  149. */
  150. static int detect_num_flash_banks(void)
  151. {
  152. typedef unsigned long FLASH_PORT_WIDTH;
  153. typedef volatile unsigned long FLASH_PORT_WIDTHV;
  154. FPWV *bank1_base;
  155. FPWV *bank2_base;
  156. FPW bank1_read;
  157. FPW bank2_read;
  158. ulong bank1_size;
  159. ulong bank2_size;
  160. ulong total_size;
  161. tqm834x_num_flash_banks = 2; /* assume two banks */
  162. /* Get bank 1 and 2 information */
  163. bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
  164. debug("Bank1 size: %lu\n", bank1_size);
  165. bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
  166. debug("Bank2 size: %lu\n", bank2_size);
  167. total_size = bank1_size + bank2_size;
  168. if (bank2_size > 0) {
  169. /* Seems like we've got bank 2, but maybe it's mirrored 1 */
  170. /* Set the base addresses */
  171. bank1_base = (FPWV *) (CFG_FLASH_BASE);
  172. bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
  173. /* Put bank 2 into CFI command mode and read */
  174. bank2_base[0x55] = 0x00980098;
  175. IOSYNC;
  176. ISYNC;
  177. bank2_read = bank2_base[0x10];
  178. /* Read from bank 1 (it's in read mode) */
  179. bank1_read = bank1_base[0x10];
  180. /* Reset Flash */
  181. bank1_base[0] = 0x00F000F0;
  182. bank2_base[0] = 0x00F000F0;
  183. if (bank2_read == bank1_read) {
  184. /*
  185. * Looks like just one bank, but not sure yet. Let's
  186. * read from bank 2 in autosoelect mode.
  187. */
  188. bank2_base[0x0555] = 0x00AA00AA;
  189. bank2_base[0x02AA] = 0x00550055;
  190. bank2_base[0x0555] = 0x00900090;
  191. IOSYNC;
  192. ISYNC;
  193. bank2_read = bank2_base[0x10];
  194. /* Read from bank 1 (it's in read mode) */
  195. bank1_read = bank1_base[0x10];
  196. /* Reset Flash */
  197. bank1_base[0] = 0x00F000F0;
  198. bank2_base[0] = 0x00F000F0;
  199. if (bank2_read == bank1_read) {
  200. /*
  201. * In both CFI command and autoselect modes,
  202. * we got the some data reading from Flash.
  203. * There is only one mirrored bank.
  204. */
  205. tqm834x_num_flash_banks = 1;
  206. total_size = bank1_size;
  207. }
  208. }
  209. }
  210. debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
  211. /* set OR0 and BR0 */
  212. im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
  213. (-(total_size) & OR_GPCM_AM);
  214. im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
  215. (BR_MS_GPCM | BR_PS_32 | BR_V);
  216. return (0);
  217. }
  218. /*************************************************************************
  219. * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
  220. */
  221. static long int get_ddr_bank_size(short cs, volatile long *base)
  222. {
  223. /* This array lists all valid DDR SDRAM configurations, with
  224. * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
  225. * The last entry has to to have size equal 0 and is igonred during
  226. * autodection. Bank sizes must be in increasing order of size
  227. */
  228. struct {
  229. long row;
  230. long col;
  231. long size;
  232. } conf[] = {
  233. {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
  234. {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
  235. {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
  236. {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
  237. {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
  238. {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
  239. {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
  240. {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
  241. {0, 0, 0}
  242. };
  243. int i;
  244. int detected;
  245. long size;
  246. detected = -1;
  247. for(i = 0; conf[i].size != 0; ++i) {
  248. /* set sdram bank configuration */
  249. set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
  250. debug("Getting RAM size...\n");
  251. size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
  252. if((size == conf[i].size) && (i == detected + 1))
  253. detected = i;
  254. debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
  255. conf[i].row,
  256. conf[i].col,
  257. conf[i].size >> 20,
  258. base,
  259. size >> 20);
  260. }
  261. if(detected == -1){
  262. /* disable empty cs */
  263. debug("\nNo valid configurations for CS%d, disabling...\n", cs);
  264. set_cs_config(cs, 0);
  265. return 0;
  266. }
  267. debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
  268. conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
  269. /* configure cs ro detected params */
  270. set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
  271. conf[detected].col);
  272. set_cs_bounds(cs, (long)base, conf[detected].size);
  273. return(conf[detected].size);
  274. }
  275. /**************************************************************************
  276. * Sets DDR bank CS bounds.
  277. */
  278. static void set_cs_bounds(short cs, long base, long size)
  279. {
  280. debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
  281. if(size == 0){
  282. im->ddr.csbnds[cs].csbnds = 0x00000000;
  283. } else {
  284. im->ddr.csbnds[cs].csbnds =
  285. ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  286. (((base + size - 1) >> CSBNDS_EA_SHIFT) &
  287. CSBNDS_EA);
  288. }
  289. SYNC;
  290. }
  291. /**************************************************************************
  292. * Sets DDR banks CS configuration.
  293. * config == 0x00000000 disables the CS.
  294. */
  295. static void set_cs_config(short cs, long config)
  296. {
  297. debug("Setting config %08x for cs %d\n", config, cs);
  298. im->ddr.cs_config[cs] = config;
  299. SYNC;
  300. }
  301. /**************************************************************************
  302. * Sets DDR clocks, timings and configuration.
  303. */
  304. static void set_ddr_config(void) {
  305. /* clock control */
  306. im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
  307. DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
  308. SYNC;
  309. /* timing configuration */
  310. im->ddr.timing_cfg_1 =
  311. (4 << TIMING_CFG1_PRETOACT_SHIFT) |
  312. (7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
  313. (4 << TIMING_CFG1_ACTTORW_SHIFT) |
  314. (5 << TIMING_CFG1_REFREC_SHIFT) |
  315. (3 << TIMING_CFG1_WRREC_SHIFT) |
  316. (3 << TIMING_CFG1_ACTTOACT_SHIFT) |
  317. (1 << TIMING_CFG1_WRTORD_SHIFT) |
  318. (TIMING_CFG1_CASLAT & TIMING_CASLAT);
  319. im->ddr.timing_cfg_2 =
  320. TIMING_CFG2_CPO_DEF |
  321. (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
  322. SYNC;
  323. /* don't enable DDR controller yet */
  324. im->ddr.sdram_cfg =
  325. SDRAM_CFG_SREN |
  326. SDRAM_CFG_SDRAM_TYPE_DDR;
  327. SYNC;
  328. /* Set SDRAM mode */
  329. im->ddr.sdram_mode =
  330. ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
  331. SDRAM_MODE_ESD_SHIFT) |
  332. ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
  333. SDRAM_MODE_SD_SHIFT) |
  334. ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
  335. MODE_CASLAT);
  336. SYNC;
  337. /* Set fast SDRAM refresh rate */
  338. im->ddr.sdram_interval =
  339. (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
  340. (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
  341. SYNC;
  342. }