mv_eth.c 104 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Ingo Assmus <ingo.assmus@keymile.com>
  4. *
  5. * based on - Driver for MV64460X ethernet ports
  6. * Copyright (C) 2002 rabeeh@galileo.co.il
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * mv_eth.c - header file for the polled mode GT ethernet driver
  28. */
  29. #include <common.h>
  30. #include <net.h>
  31. #include <malloc.h>
  32. #include "mv_eth.h"
  33. /* enable Debug outputs */
  34. #undef DEBUG_MV_ETH
  35. #ifdef DEBUG_MV_ETH
  36. #define DEBUG
  37. #define DP(x) x
  38. #else
  39. #define DP(x)
  40. #endif
  41. #undef MV64460_CHECKSUM_OFFLOAD
  42. /*************************************************************************
  43. **************************************************************************
  44. **************************************************************************
  45. * The first part is the high level driver of the gigE ethernet ports. *
  46. **************************************************************************
  47. **************************************************************************
  48. *************************************************************************/
  49. /* Definition for configuring driver */
  50. /* #define UPDATE_STATS_BY_SOFTWARE */
  51. #undef MV64460_RX_QUEUE_FILL_ON_TASK
  52. /* Constants */
  53. #define MAGIC_ETH_RUNNING 8031971
  54. #define MV64460_INTERNAL_SRAM_SIZE _256K
  55. #define EXTRA_BYTES 32
  56. #define WRAP ETH_HLEN + 2 + 4 + 16
  57. #define BUFFER_MTU dev->mtu + WRAP
  58. #define INT_CAUSE_UNMASK_ALL 0x0007ffff
  59. #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
  60. #ifdef MV64460_RX_FILL_ON_TASK
  61. #define INT_CAUSE_MASK_ALL 0x00000000
  62. #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
  63. #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
  64. #endif
  65. /* Read/Write to/from MV64460 internal registers */
  66. #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
  67. #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
  68. #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
  69. #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
  70. /* Static function declarations */
  71. static int mv64460_eth_real_open (struct eth_device *eth);
  72. static int mv64460_eth_real_stop (struct eth_device *eth);
  73. static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
  74. *dev);
  75. static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
  76. static void mv64460_eth_update_stat (struct eth_device *dev);
  77. bool db64460_eth_start (struct eth_device *eth);
  78. unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
  79. unsigned int mib_offset);
  80. int mv64460_eth_receive (struct eth_device *dev);
  81. int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
  82. #ifndef UPDATE_STATS_BY_SOFTWARE
  83. static void mv64460_eth_print_stat (struct eth_device *dev);
  84. #endif
  85. /* Processes a received packet */
  86. extern void NetReceive (volatile uchar *, int);
  87. extern unsigned int INTERNAL_REG_BASE_ADDR;
  88. /*************************************************
  89. *Helper functions - used inside the driver only *
  90. *************************************************/
  91. #ifdef DEBUG_MV_ETH
  92. void print_globals (struct eth_device *dev)
  93. {
  94. printf ("Ethernet PRINT_Globals-Debug function\n");
  95. printf ("Base Address for ETH_PORT_INFO: %08x\n",
  96. (unsigned int) dev->priv);
  97. printf ("Base Address for mv64460_eth_priv: %08x\n",
  98. (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
  99. port_private));
  100. printf ("GT Internal Base Address: %08x\n",
  101. INTERNAL_REG_BASE_ADDR);
  102. printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
  103. printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
  104. printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
  105. (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
  106. p_rx_buffer_base[0],
  107. (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
  108. printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
  109. (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
  110. p_tx_buffer_base[0],
  111. (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
  112. }
  113. #endif
  114. #define my_cpu_to_le32(x) my_le32_to_cpu((x))
  115. unsigned long my_le32_to_cpu (unsigned long x)
  116. {
  117. return (((x & 0x000000ffU) << 24) |
  118. ((x & 0x0000ff00U) << 8) |
  119. ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
  120. }
  121. /**********************************************************************
  122. * mv64460_eth_print_phy_status
  123. *
  124. * Prints gigabit ethenret phy status
  125. *
  126. * Input : pointer to ethernet interface network device structure
  127. * Output : N/A
  128. **********************************************************************/
  129. static void mv64460_eth_print_phy_status (struct eth_device *dev)
  130. {
  131. struct mv64460_eth_priv *port_private;
  132. unsigned int port_num;
  133. ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
  134. unsigned int port_status, phy_reg_data;
  135. port_private =
  136. (struct mv64460_eth_priv *) ethernet_private->port_private;
  137. port_num = port_private->port_num;
  138. /* Check Link status on phy */
  139. eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
  140. if (!(phy_reg_data & 0x20)) {
  141. printf ("Ethernet port changed link status to DOWN\n");
  142. } else {
  143. port_status =
  144. MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
  145. printf ("Ethernet status port %d: Link up", port_num);
  146. printf (", %s",
  147. (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
  148. if (port_status & BIT4)
  149. printf (", Speed 1 Gbps");
  150. else
  151. printf (", %s",
  152. (port_status & BIT5) ? "Speed 100 Mbps" :
  153. "Speed 10 Mbps");
  154. printf ("\n");
  155. }
  156. }
  157. /**********************************************************************
  158. * u-boot entry functions for mv64460_eth
  159. *
  160. **********************************************************************/
  161. int db64460_eth_probe (struct eth_device *dev)
  162. {
  163. return ((int) db64460_eth_start (dev));
  164. }
  165. int db64460_eth_poll (struct eth_device *dev)
  166. {
  167. return mv64460_eth_receive (dev);
  168. }
  169. int db64460_eth_transmit (struct eth_device *dev, volatile void *packet,
  170. int length)
  171. {
  172. mv64460_eth_xmit (dev, packet, length);
  173. return 0;
  174. }
  175. void db64460_eth_disable (struct eth_device *dev)
  176. {
  177. mv64460_eth_stop (dev);
  178. }
  179. void mv6446x_eth_initialize (bd_t * bis)
  180. {
  181. struct eth_device *dev;
  182. ETH_PORT_INFO *ethernet_private;
  183. struct mv64460_eth_priv *port_private;
  184. int devnum, x, temp;
  185. char *s, *e, buf[64];
  186. for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
  187. dev = calloc (sizeof (*dev), 1);
  188. if (!dev) {
  189. printf ("%s: mv_enet%d allocation failure, %s\n",
  190. __FUNCTION__, devnum, "eth_device structure");
  191. return;
  192. }
  193. /* must be less than NAMESIZE (16) */
  194. sprintf (dev->name, "mv_enet%d", devnum);
  195. #ifdef DEBUG
  196. printf ("Initializing %s\n", dev->name);
  197. #endif
  198. /* Extract the MAC address from the environment */
  199. switch (devnum) {
  200. case 0:
  201. s = "ethaddr";
  202. break;
  203. case 1:
  204. s = "eth1addr";
  205. break;
  206. case 2:
  207. s = "eth2addr";
  208. break;
  209. default: /* this should never happen */
  210. printf ("%s: Invalid device number %d\n",
  211. __FUNCTION__, devnum);
  212. return;
  213. }
  214. temp = getenv_r (s, buf, sizeof (buf));
  215. s = (temp > 0) ? buf : NULL;
  216. #ifdef DEBUG
  217. printf ("Setting MAC %d to %s\n", devnum, s);
  218. #endif
  219. for (x = 0; x < 6; ++x) {
  220. dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
  221. if (s)
  222. s = (*e) ? e + 1 : e;
  223. }
  224. /* ronen - set the MAC addr in the HW */
  225. eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
  226. dev->init = (void *) db64460_eth_probe;
  227. dev->halt = (void *) ethernet_phy_reset;
  228. dev->send = (void *) db64460_eth_transmit;
  229. dev->recv = (void *) db64460_eth_poll;
  230. ethernet_private = calloc (sizeof (*ethernet_private), 1);
  231. dev->priv = (void *)ethernet_private;
  232. if (!ethernet_private) {
  233. printf ("%s: %s allocation failure, %s\n",
  234. __FUNCTION__, dev->name,
  235. "Private Device Structure");
  236. free (dev);
  237. return;
  238. }
  239. /* start with an zeroed ETH_PORT_INFO */
  240. memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
  241. memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
  242. /* set pointer to memory for stats data structure etc... */
  243. port_private = calloc (sizeof (*ethernet_private), 1);
  244. ethernet_private->port_private = (void *)port_private;
  245. if (!port_private) {
  246. printf ("%s: %s allocation failure, %s\n",
  247. __FUNCTION__, dev->name,
  248. "Port Private Device Structure");
  249. free (ethernet_private);
  250. free (dev);
  251. return;
  252. }
  253. port_private->stats =
  254. calloc (sizeof (struct net_device_stats), 1);
  255. if (!port_private->stats) {
  256. printf ("%s: %s allocation failure, %s\n",
  257. __FUNCTION__, dev->name,
  258. "Net stat Structure");
  259. free (port_private);
  260. free (ethernet_private);
  261. free (dev);
  262. return;
  263. }
  264. memset (ethernet_private->port_private, 0,
  265. sizeof (struct mv64460_eth_priv));
  266. switch (devnum) {
  267. case 0:
  268. ethernet_private->port_num = ETH_0;
  269. break;
  270. case 1:
  271. ethernet_private->port_num = ETH_1;
  272. break;
  273. case 2:
  274. ethernet_private->port_num = ETH_2;
  275. break;
  276. default:
  277. printf ("Invalid device number %d\n", devnum);
  278. break;
  279. };
  280. port_private->port_num = devnum;
  281. /*
  282. * Read MIB counter on the GT in order to reset them,
  283. * then zero all the stats fields in memory
  284. */
  285. mv64460_eth_update_stat (dev);
  286. memset (port_private->stats, 0,
  287. sizeof (struct net_device_stats));
  288. /* Extract the MAC address from the environment */
  289. switch (devnum) {
  290. case 0:
  291. s = "ethaddr";
  292. break;
  293. case 1:
  294. s = "eth1addr";
  295. break;
  296. case 2:
  297. s = "eth2addr";
  298. break;
  299. default: /* this should never happen */
  300. printf ("%s: Invalid device number %d\n",
  301. __FUNCTION__, devnum);
  302. return;
  303. }
  304. temp = getenv_r (s, buf, sizeof (buf));
  305. s = (temp > 0) ? buf : NULL;
  306. #ifdef DEBUG
  307. printf ("Setting MAC %d to %s\n", devnum, s);
  308. #endif
  309. for (x = 0; x < 6; ++x) {
  310. dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
  311. if (s)
  312. s = (*e) ? e + 1 : e;
  313. }
  314. DP (printf ("Allocating descriptor and buffer rings\n"));
  315. ethernet_private->p_rx_desc_area_base[0] =
  316. (ETH_RX_DESC *) memalign (16,
  317. RX_DESC_ALIGNED_SIZE *
  318. MV64460_RX_QUEUE_SIZE + 1);
  319. ethernet_private->p_tx_desc_area_base[0] =
  320. (ETH_TX_DESC *) memalign (16,
  321. TX_DESC_ALIGNED_SIZE *
  322. MV64460_TX_QUEUE_SIZE + 1);
  323. ethernet_private->p_rx_buffer_base[0] =
  324. (char *) memalign (16,
  325. MV64460_RX_QUEUE_SIZE *
  326. MV64460_TX_BUFFER_SIZE + 1);
  327. ethernet_private->p_tx_buffer_base[0] =
  328. (char *) memalign (16,
  329. MV64460_RX_QUEUE_SIZE *
  330. MV64460_TX_BUFFER_SIZE + 1);
  331. #ifdef DEBUG_MV_ETH
  332. /* DEBUG OUTPUT prints adresses of globals */
  333. print_globals (dev);
  334. #endif
  335. eth_register (dev);
  336. }
  337. DP (printf ("%s: exit\n", __FUNCTION__));
  338. }
  339. /**********************************************************************
  340. * mv64460_eth_open
  341. *
  342. * This function is called when openning the network device. The function
  343. * should initialize all the hardware, initialize cyclic Rx/Tx
  344. * descriptors chain and buffers and allocate an IRQ to the network
  345. * device.
  346. *
  347. * Input : a pointer to the network device structure
  348. * / / ronen - changed the output to match net/eth.c needs
  349. * Output : nonzero of success , zero if fails.
  350. * under construction
  351. **********************************************************************/
  352. int mv64460_eth_open (struct eth_device *dev)
  353. {
  354. return (mv64460_eth_real_open (dev));
  355. }
  356. /* Helper function for mv64460_eth_open */
  357. static int mv64460_eth_real_open (struct eth_device *dev)
  358. {
  359. unsigned int queue;
  360. ETH_PORT_INFO *ethernet_private;
  361. struct mv64460_eth_priv *port_private;
  362. unsigned int port_num;
  363. u32 port_status, phy_reg_data;
  364. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  365. /* ronen - when we update the MAC env params we only update dev->enetaddr
  366. see ./net/eth.c eth_set_enetaddr() */
  367. memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
  368. port_private =
  369. (struct mv64460_eth_priv *) ethernet_private->port_private;
  370. port_num = port_private->port_num;
  371. /* Stop RX Queues */
  372. MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
  373. 0x0000ff00);
  374. /* Clear the ethernet port interrupts */
  375. MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
  376. MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
  377. /* Unmask RX buffer and TX end interrupt */
  378. MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
  379. INT_CAUSE_UNMASK_ALL);
  380. /* Unmask phy and link status changes interrupts */
  381. MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
  382. INT_CAUSE_UNMASK_ALL_EXT);
  383. /* Set phy address of the port */
  384. ethernet_private->port_phy_addr = 0x8 + port_num;
  385. /* Activate the DMA channels etc */
  386. eth_port_init (ethernet_private);
  387. /* "Allocate" setup TX rings */
  388. for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
  389. unsigned int size;
  390. port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
  391. size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
  392. ethernet_private->tx_desc_area_size[queue] = size;
  393. /* first clear desc area completely */
  394. memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
  395. 0, ethernet_private->tx_desc_area_size[queue]);
  396. /* initialize tx desc ring with low level driver */
  397. if (ether_init_tx_desc_ring
  398. (ethernet_private, ETH_Q0,
  399. port_private->tx_ring_size[queue],
  400. MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
  401. (unsigned int) ethernet_private->
  402. p_tx_desc_area_base[queue],
  403. (unsigned int) ethernet_private->
  404. p_tx_buffer_base[queue]) == false)
  405. printf ("### Error initializing TX Ring\n");
  406. }
  407. /* "Allocate" setup RX rings */
  408. for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
  409. unsigned int size;
  410. /* Meantime RX Ring are fixed - but must be configurable by user */
  411. port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
  412. size = (port_private->rx_ring_size[queue] *
  413. RX_DESC_ALIGNED_SIZE);
  414. ethernet_private->rx_desc_area_size[queue] = size;
  415. /* first clear desc area completely */
  416. memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
  417. 0, ethernet_private->rx_desc_area_size[queue]);
  418. if ((ether_init_rx_desc_ring
  419. (ethernet_private, ETH_Q0,
  420. port_private->rx_ring_size[queue],
  421. MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
  422. (unsigned int) ethernet_private->
  423. p_rx_desc_area_base[queue],
  424. (unsigned int) ethernet_private->
  425. p_rx_buffer_base[queue])) == false)
  426. printf ("### Error initializing RX Ring\n");
  427. }
  428. eth_port_start (ethernet_private);
  429. /* Set maximum receive buffer to 9700 bytes */
  430. MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
  431. (0x5 << 17) |
  432. (MV_REG_READ
  433. (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
  434. & 0xfff1ffff));
  435. /*
  436. * Set ethernet MTU for leaky bucket mechanism to 0 - this will
  437. * disable the leaky bucket mechanism .
  438. */
  439. MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
  440. port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
  441. /* Check Link status on phy */
  442. eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
  443. if (!(phy_reg_data & 0x20)) {
  444. /* Reset PHY */
  445. if ((ethernet_phy_reset (port_num)) != true) {
  446. printf ("$$ Warnning: No link on port %d \n",
  447. port_num);
  448. return 0;
  449. } else {
  450. eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
  451. if (!(phy_reg_data & 0x20)) {
  452. printf ("### Error: Phy is not active\n");
  453. return 0;
  454. }
  455. }
  456. } else {
  457. mv64460_eth_print_phy_status (dev);
  458. }
  459. port_private->eth_running = MAGIC_ETH_RUNNING;
  460. return 1;
  461. }
  462. static int mv64460_eth_free_tx_rings (struct eth_device *dev)
  463. {
  464. unsigned int queue;
  465. ETH_PORT_INFO *ethernet_private;
  466. struct mv64460_eth_priv *port_private;
  467. unsigned int port_num;
  468. volatile ETH_TX_DESC *p_tx_curr_desc;
  469. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  470. port_private =
  471. (struct mv64460_eth_priv *) ethernet_private->port_private;
  472. port_num = port_private->port_num;
  473. /* Stop Tx Queues */
  474. MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
  475. 0x0000ff00);
  476. /* Free TX rings */
  477. DP (printf ("Clearing previously allocated TX queues... "));
  478. for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
  479. /* Free on TX rings */
  480. for (p_tx_curr_desc =
  481. ethernet_private->p_tx_desc_area_base[queue];
  482. ((unsigned int) p_tx_curr_desc <= (unsigned int)
  483. ethernet_private->p_tx_desc_area_base[queue] +
  484. ethernet_private->tx_desc_area_size[queue]);
  485. p_tx_curr_desc =
  486. (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
  487. TX_DESC_ALIGNED_SIZE)) {
  488. /* this is inside for loop */
  489. if (p_tx_curr_desc->return_info != 0) {
  490. p_tx_curr_desc->return_info = 0;
  491. DP (printf ("freed\n"));
  492. }
  493. }
  494. DP (printf ("Done\n"));
  495. }
  496. return 0;
  497. }
  498. static int mv64460_eth_free_rx_rings (struct eth_device *dev)
  499. {
  500. unsigned int queue;
  501. ETH_PORT_INFO *ethernet_private;
  502. struct mv64460_eth_priv *port_private;
  503. unsigned int port_num;
  504. volatile ETH_RX_DESC *p_rx_curr_desc;
  505. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  506. port_private =
  507. (struct mv64460_eth_priv *) ethernet_private->port_private;
  508. port_num = port_private->port_num;
  509. /* Stop RX Queues */
  510. MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
  511. 0x0000ff00);
  512. /* Free RX rings */
  513. DP (printf ("Clearing previously allocated RX queues... "));
  514. for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
  515. /* Free preallocated skb's on RX rings */
  516. for (p_rx_curr_desc =
  517. ethernet_private->p_rx_desc_area_base[queue];
  518. (((unsigned int) p_rx_curr_desc <
  519. ((unsigned int) ethernet_private->
  520. p_rx_desc_area_base[queue] +
  521. ethernet_private->rx_desc_area_size[queue])));
  522. p_rx_curr_desc =
  523. (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
  524. RX_DESC_ALIGNED_SIZE)) {
  525. if (p_rx_curr_desc->return_info != 0) {
  526. p_rx_curr_desc->return_info = 0;
  527. DP (printf ("freed\n"));
  528. }
  529. }
  530. DP (printf ("Done\n"));
  531. }
  532. return 0;
  533. }
  534. /**********************************************************************
  535. * mv64460_eth_stop
  536. *
  537. * This function is used when closing the network device.
  538. * It updates the hardware,
  539. * release all memory that holds buffers and descriptors and release the IRQ.
  540. * Input : a pointer to the device structure
  541. * Output : zero if success , nonzero if fails
  542. *********************************************************************/
  543. int mv64460_eth_stop (struct eth_device *dev)
  544. {
  545. ETH_PORT_INFO *ethernet_private;
  546. struct mv64460_eth_priv *port_private;
  547. unsigned int port_num;
  548. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  549. port_private =
  550. (struct mv64460_eth_priv *) ethernet_private->port_private;
  551. port_num = port_private->port_num;
  552. /* Disable all gigE address decoder */
  553. MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
  554. DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
  555. mv64460_eth_real_stop (dev);
  556. return 0;
  557. };
  558. /* Helper function for mv64460_eth_stop */
  559. static int mv64460_eth_real_stop (struct eth_device *dev)
  560. {
  561. ETH_PORT_INFO *ethernet_private;
  562. struct mv64460_eth_priv *port_private;
  563. unsigned int port_num;
  564. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  565. port_private =
  566. (struct mv64460_eth_priv *) ethernet_private->port_private;
  567. port_num = port_private->port_num;
  568. mv64460_eth_free_tx_rings (dev);
  569. mv64460_eth_free_rx_rings (dev);
  570. eth_port_reset (ethernet_private->port_num);
  571. /* Disable ethernet port interrupts */
  572. MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
  573. MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
  574. /* Mask RX buffer and TX end interrupt */
  575. MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
  576. /* Mask phy and link status changes interrupts */
  577. MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
  578. MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
  579. BIT0 << port_num);
  580. /* Print Network statistics */
  581. #ifndef UPDATE_STATS_BY_SOFTWARE
  582. /*
  583. * Print statistics (only if ethernet is running),
  584. * then zero all the stats fields in memory
  585. */
  586. if (port_private->eth_running == MAGIC_ETH_RUNNING) {
  587. port_private->eth_running = 0;
  588. mv64460_eth_print_stat (dev);
  589. }
  590. memset (port_private->stats, 0, sizeof (struct net_device_stats));
  591. #endif
  592. DP (printf ("\nEthernet stopped ... \n"));
  593. return 0;
  594. }
  595. /**********************************************************************
  596. * mv64460_eth_start_xmit
  597. *
  598. * This function is queues a packet in the Tx descriptor for
  599. * required port.
  600. *
  601. * Input : skb - a pointer to socket buffer
  602. * dev - a pointer to the required port
  603. *
  604. * Output : zero upon success
  605. **********************************************************************/
  606. int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
  607. int dataSize)
  608. {
  609. ETH_PORT_INFO *ethernet_private;
  610. struct mv64460_eth_priv *port_private;
  611. unsigned int port_num;
  612. PKT_INFO pkt_info;
  613. ETH_FUNC_RET_STATUS status;
  614. struct net_device_stats *stats;
  615. ETH_FUNC_RET_STATUS release_result;
  616. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  617. port_private =
  618. (struct mv64460_eth_priv *) ethernet_private->port_private;
  619. port_num = port_private->port_num;
  620. stats = port_private->stats;
  621. /* Update packet info data structure */
  622. pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
  623. pkt_info.byte_cnt = dataSize;
  624. pkt_info.buf_ptr = (unsigned int) dataPtr;
  625. status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
  626. if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
  627. printf ("Error on transmitting packet ..");
  628. if (status == ETH_QUEUE_FULL)
  629. printf ("ETH Queue is full. \n");
  630. if (status == ETH_QUEUE_LAST_RESOURCE)
  631. printf ("ETH Queue: using last available resource. \n");
  632. goto error;
  633. }
  634. /* Update statistics and start of transmittion time */
  635. stats->tx_bytes += dataSize;
  636. stats->tx_packets++;
  637. /* Check if packet(s) is(are) transmitted correctly (release everything) */
  638. do {
  639. release_result =
  640. eth_tx_return_desc (ethernet_private, ETH_Q0,
  641. &pkt_info);
  642. switch (release_result) {
  643. case ETH_OK:
  644. DP (printf ("descriptor released\n"));
  645. if (pkt_info.cmd_sts & BIT0) {
  646. printf ("Error in TX\n");
  647. stats->tx_errors++;
  648. }
  649. break;
  650. case ETH_RETRY:
  651. DP (printf ("transmission still in process\n"));
  652. break;
  653. case ETH_ERROR:
  654. printf ("routine can not access Tx desc ring\n");
  655. break;
  656. case ETH_END_OF_JOB:
  657. DP (printf ("the routine has nothing to release\n"));
  658. break;
  659. default: /* should not happen */
  660. break;
  661. }
  662. } while (release_result == ETH_OK);
  663. return 0; /* success */
  664. error:
  665. return 1; /* Failed - higher layers will free the skb */
  666. }
  667. /**********************************************************************
  668. * mv64460_eth_receive
  669. *
  670. * This function is forward packets that are received from the port's
  671. * queues toward kernel core or FastRoute them to another interface.
  672. *
  673. * Input : dev - a pointer to the required interface
  674. * max - maximum number to receive (0 means unlimted)
  675. *
  676. * Output : number of served packets
  677. **********************************************************************/
  678. int mv64460_eth_receive (struct eth_device *dev)
  679. {
  680. ETH_PORT_INFO *ethernet_private;
  681. struct mv64460_eth_priv *port_private;
  682. unsigned int port_num;
  683. PKT_INFO pkt_info;
  684. struct net_device_stats *stats;
  685. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  686. port_private =
  687. (struct mv64460_eth_priv *) ethernet_private->port_private;
  688. port_num = port_private->port_num;
  689. stats = port_private->stats;
  690. while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
  691. ETH_OK)) {
  692. #ifdef DEBUG_MV_ETH
  693. if (pkt_info.byte_cnt != 0) {
  694. printf ("%s: Received %d byte Packet @ 0x%x\n",
  695. __FUNCTION__, pkt_info.byte_cnt,
  696. pkt_info.buf_ptr);
  697. }
  698. #endif
  699. /* Update statistics. Note byte count includes 4 byte CRC count */
  700. stats->rx_packets++;
  701. stats->rx_bytes += pkt_info.byte_cnt;
  702. /*
  703. * In case received a packet without first / last bits on OR the error
  704. * summary bit is on, the packets needs to be dropeed.
  705. */
  706. if (((pkt_info.
  707. cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
  708. (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
  709. || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
  710. stats->rx_dropped++;
  711. printf ("Received packet spread on multiple descriptors\n");
  712. /* Is this caused by an error ? */
  713. if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
  714. stats->rx_errors++;
  715. }
  716. /* free these descriptors again without forwarding them to the higher layers */
  717. pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
  718. pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
  719. if (eth_rx_return_buff
  720. (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
  721. printf ("Error while returning the RX Desc to Ring\n");
  722. } else {
  723. DP (printf ("RX Desc returned to Ring\n"));
  724. }
  725. /* /free these descriptors again */
  726. } else {
  727. /* !!! call higher layer processing */
  728. #ifdef DEBUG_MV_ETH
  729. printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
  730. #endif
  731. /* let the upper layer handle the packet */
  732. NetReceive ((uchar *) pkt_info.buf_ptr,
  733. (int) pkt_info.byte_cnt);
  734. /* **************************************************************** */
  735. /* free descriptor */
  736. pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
  737. pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
  738. DP (printf
  739. ("RX: pkt_info.buf_ptr = %x\n",
  740. pkt_info.buf_ptr));
  741. if (eth_rx_return_buff
  742. (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
  743. printf ("Error while returning the RX Desc to Ring\n");
  744. } else {
  745. DP (printf ("RX Desc returned to Ring\n"));
  746. }
  747. /* **************************************************************** */
  748. }
  749. }
  750. mv64460_eth_get_stats (dev); /* update statistics */
  751. return 1;
  752. }
  753. /**********************************************************************
  754. * mv64460_eth_get_stats
  755. *
  756. * Returns a pointer to the interface statistics.
  757. *
  758. * Input : dev - a pointer to the required interface
  759. *
  760. * Output : a pointer to the interface's statistics
  761. **********************************************************************/
  762. static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
  763. {
  764. ETH_PORT_INFO *ethernet_private;
  765. struct mv64460_eth_priv *port_private;
  766. unsigned int port_num;
  767. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  768. port_private =
  769. (struct mv64460_eth_priv *) ethernet_private->port_private;
  770. port_num = port_private->port_num;
  771. mv64460_eth_update_stat (dev);
  772. return port_private->stats;
  773. }
  774. /**********************************************************************
  775. * mv64460_eth_update_stat
  776. *
  777. * Update the statistics structure in the private data structure
  778. *
  779. * Input : pointer to ethernet interface network device structure
  780. * Output : N/A
  781. **********************************************************************/
  782. static void mv64460_eth_update_stat (struct eth_device *dev)
  783. {
  784. ETH_PORT_INFO *ethernet_private;
  785. struct mv64460_eth_priv *port_private;
  786. struct net_device_stats *stats;
  787. unsigned int port_num;
  788. volatile unsigned int dummy;
  789. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  790. port_private =
  791. (struct mv64460_eth_priv *) ethernet_private->port_private;
  792. port_num = port_private->port_num;
  793. stats = port_private->stats;
  794. /* These are false updates */
  795. stats->rx_packets += (unsigned long)
  796. eth_read_mib_counter (ethernet_private->port_num,
  797. ETH_MIB_GOOD_FRAMES_RECEIVED);
  798. stats->tx_packets += (unsigned long)
  799. eth_read_mib_counter (ethernet_private->port_num,
  800. ETH_MIB_GOOD_FRAMES_SENT);
  801. stats->rx_bytes += (unsigned long)
  802. eth_read_mib_counter (ethernet_private->port_num,
  803. ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
  804. /*
  805. * Ideally this should be as follows -
  806. *
  807. * stats->rx_bytes += stats->rx_bytes +
  808. * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
  809. * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
  810. *
  811. * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
  812. * is just a dummy read for proper work of the GigE port
  813. */
  814. dummy = eth_read_mib_counter (ethernet_private->port_num,
  815. ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
  816. stats->tx_bytes += (unsigned long)
  817. eth_read_mib_counter (ethernet_private->port_num,
  818. ETH_MIB_GOOD_OCTETS_SENT_LOW);
  819. dummy = eth_read_mib_counter (ethernet_private->port_num,
  820. ETH_MIB_GOOD_OCTETS_SENT_HIGH);
  821. stats->rx_errors += (unsigned long)
  822. eth_read_mib_counter (ethernet_private->port_num,
  823. ETH_MIB_MAC_RECEIVE_ERROR);
  824. /* Rx dropped is for received packet with CRC error */
  825. stats->rx_dropped +=
  826. (unsigned long) eth_read_mib_counter (ethernet_private->
  827. port_num,
  828. ETH_MIB_BAD_CRC_EVENT);
  829. stats->multicast += (unsigned long)
  830. eth_read_mib_counter (ethernet_private->port_num,
  831. ETH_MIB_MULTICAST_FRAMES_RECEIVED);
  832. stats->collisions +=
  833. (unsigned long) eth_read_mib_counter (ethernet_private->
  834. port_num,
  835. ETH_MIB_COLLISION) +
  836. (unsigned long) eth_read_mib_counter (ethernet_private->
  837. port_num,
  838. ETH_MIB_LATE_COLLISION);
  839. /* detailed rx errors */
  840. stats->rx_length_errors +=
  841. (unsigned long) eth_read_mib_counter (ethernet_private->
  842. port_num,
  843. ETH_MIB_UNDERSIZE_RECEIVED)
  844. +
  845. (unsigned long) eth_read_mib_counter (ethernet_private->
  846. port_num,
  847. ETH_MIB_OVERSIZE_RECEIVED);
  848. /* detailed tx errors */
  849. }
  850. #ifndef UPDATE_STATS_BY_SOFTWARE
  851. /**********************************************************************
  852. * mv64460_eth_print_stat
  853. *
  854. * Update the statistics structure in the private data structure
  855. *
  856. * Input : pointer to ethernet interface network device structure
  857. * Output : N/A
  858. **********************************************************************/
  859. static void mv64460_eth_print_stat (struct eth_device *dev)
  860. {
  861. ETH_PORT_INFO *ethernet_private;
  862. struct mv64460_eth_priv *port_private;
  863. struct net_device_stats *stats;
  864. unsigned int port_num;
  865. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  866. port_private =
  867. (struct mv64460_eth_priv *) ethernet_private->port_private;
  868. port_num = port_private->port_num;
  869. stats = port_private->stats;
  870. /* These are false updates */
  871. printf ("\n### Network statistics: ###\n");
  872. printf ("--------------------------\n");
  873. printf (" Packets received: %ld\n", stats->rx_packets);
  874. printf (" Packets send: %ld\n", stats->tx_packets);
  875. printf (" Received bytes: %ld\n", stats->rx_bytes);
  876. printf (" Send bytes: %ld\n", stats->tx_bytes);
  877. if (stats->rx_errors != 0)
  878. printf (" Rx Errors: %ld\n",
  879. stats->rx_errors);
  880. if (stats->rx_dropped != 0)
  881. printf (" Rx dropped (CRC Errors): %ld\n",
  882. stats->rx_dropped);
  883. if (stats->multicast != 0)
  884. printf (" Rx mulicast frames: %ld\n",
  885. stats->multicast);
  886. if (stats->collisions != 0)
  887. printf (" No. of collisions: %ld\n",
  888. stats->collisions);
  889. if (stats->rx_length_errors != 0)
  890. printf (" Rx length errors: %ld\n",
  891. stats->rx_length_errors);
  892. }
  893. #endif
  894. /**************************************************************************
  895. *network_start - Network Kick Off Routine UBoot
  896. *Inputs :
  897. *Outputs :
  898. **************************************************************************/
  899. bool db64460_eth_start (struct eth_device *dev)
  900. {
  901. return (mv64460_eth_open (dev)); /* calls real open */
  902. }
  903. /*************************************************************************
  904. **************************************************************************
  905. **************************************************************************
  906. * The second part is the low level driver of the gigE ethernet ports. *
  907. **************************************************************************
  908. **************************************************************************
  909. *************************************************************************/
  910. /*
  911. * based on Linux code
  912. * arch/ppc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
  913. * Copyright (C) 2002 rabeeh@galileo.co.il
  914. * This program is free software; you can redistribute it and/or
  915. * modify it under the terms of the GNU General Public License
  916. * as published by the Free Software Foundation; either version 2
  917. * of the License, or (at your option) any later version.
  918. * This program is distributed in the hope that it will be useful,
  919. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  920. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  921. * GNU General Public License for more details.
  922. * You should have received a copy of the GNU General Public License
  923. * along with this program; if not, write to the Free Software
  924. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  925. *
  926. */
  927. /********************************************************************************
  928. * Marvell's Gigabit Ethernet controller low level driver
  929. *
  930. * DESCRIPTION:
  931. * This file introduce low level API to Marvell's Gigabit Ethernet
  932. * controller. This Gigabit Ethernet Controller driver API controls
  933. * 1) Operations (i.e. port init, start, reset etc').
  934. * 2) Data flow (i.e. port send, receive etc').
  935. * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
  936. * struct.
  937. * This struct includes user configuration information as well as
  938. * driver internal data needed for its operations.
  939. *
  940. * Supported Features:
  941. * - This low level driver is OS independent. Allocating memory for
  942. * the descriptor rings and buffers are not within the scope of
  943. * this driver.
  944. * - The user is free from Rx/Tx queue managing.
  945. * - This low level driver introduce functionality API that enable
  946. * the to operate Marvell's Gigabit Ethernet Controller in a
  947. * convenient way.
  948. * - Simple Gigabit Ethernet port operation API.
  949. * - Simple Gigabit Ethernet port data flow API.
  950. * - Data flow and operation API support per queue functionality.
  951. * - Support cached descriptors for better performance.
  952. * - Enable access to all four DRAM banks and internal SRAM memory
  953. * spaces.
  954. * - PHY access and control API.
  955. * - Port control register configuration API.
  956. * - Full control over Unicast and Multicast MAC configurations.
  957. *
  958. * Operation flow:
  959. *
  960. * Initialization phase
  961. * This phase complete the initialization of the ETH_PORT_INFO
  962. * struct.
  963. * User information regarding port configuration has to be set
  964. * prior to calling the port initialization routine. For example,
  965. * the user has to assign the port_phy_addr field which is board
  966. * depended parameter.
  967. * In this phase any port Tx/Rx activity is halted, MIB counters
  968. * are cleared, PHY address is set according to user parameter and
  969. * access to DRAM and internal SRAM memory spaces.
  970. *
  971. * Driver ring initialization
  972. * Allocating memory for the descriptor rings and buffers is not
  973. * within the scope of this driver. Thus, the user is required to
  974. * allocate memory for the descriptors ring and buffers. Those
  975. * memory parameters are used by the Rx and Tx ring initialization
  976. * routines in order to curve the descriptor linked list in a form
  977. * of a ring.
  978. * Note: Pay special attention to alignment issues when using
  979. * cached descriptors/buffers. In this phase the driver store
  980. * information in the ETH_PORT_INFO struct regarding each queue
  981. * ring.
  982. *
  983. * Driver start
  984. * This phase prepares the Ethernet port for Rx and Tx activity.
  985. * It uses the information stored in the ETH_PORT_INFO struct to
  986. * initialize the various port registers.
  987. *
  988. * Data flow:
  989. * All packet references to/from the driver are done using PKT_INFO
  990. * struct.
  991. * This struct is a unified struct used with Rx and Tx operations.
  992. * This way the user is not required to be familiar with neither
  993. * Tx nor Rx descriptors structures.
  994. * The driver's descriptors rings are management by indexes.
  995. * Those indexes controls the ring resources and used to indicate
  996. * a SW resource error:
  997. * 'current'
  998. * This index points to the current available resource for use. For
  999. * example in Rx process this index will point to the descriptor
  1000. * that will be passed to the user upon calling the receive routine.
  1001. * In Tx process, this index will point to the descriptor
  1002. * that will be assigned with the user packet info and transmitted.
  1003. * 'used'
  1004. * This index points to the descriptor that need to restore its
  1005. * resources. For example in Rx process, using the Rx buffer return
  1006. * API will attach the buffer returned in packet info to the
  1007. * descriptor pointed by 'used'. In Tx process, using the Tx
  1008. * descriptor return will merely return the user packet info with
  1009. * the command status of the transmitted buffer pointed by the
  1010. * 'used' index. Nevertheless, it is essential to use this routine
  1011. * to update the 'used' index.
  1012. * 'first'
  1013. * This index supports Tx Scatter-Gather. It points to the first
  1014. * descriptor of a packet assembled of multiple buffers. For example
  1015. * when in middle of Such packet we have a Tx resource error the
  1016. * 'curr' index get the value of 'first' to indicate that the ring
  1017. * returned to its state before trying to transmit this packet.
  1018. *
  1019. * Receive operation:
  1020. * The eth_port_receive API set the packet information struct,
  1021. * passed by the caller, with received information from the
  1022. * 'current' SDMA descriptor.
  1023. * It is the user responsibility to return this resource back
  1024. * to the Rx descriptor ring to enable the reuse of this source.
  1025. * Return Rx resource is done using the eth_rx_return_buff API.
  1026. *
  1027. * Transmit operation:
  1028. * The eth_port_send API supports Scatter-Gather which enables to
  1029. * send a packet spanned over multiple buffers. This means that
  1030. * for each packet info structure given by the user and put into
  1031. * the Tx descriptors ring, will be transmitted only if the 'LAST'
  1032. * bit will be set in the packet info command status field. This
  1033. * API also consider restriction regarding buffer alignments and
  1034. * sizes.
  1035. * The user must return a Tx resource after ensuring the buffer
  1036. * has been transmitted to enable the Tx ring indexes to update.
  1037. *
  1038. * BOARD LAYOUT
  1039. * This device is on-board. No jumper diagram is necessary.
  1040. *
  1041. * EXTERNAL INTERFACE
  1042. *
  1043. * Prior to calling the initialization routine eth_port_init() the user
  1044. * must set the following fields under ETH_PORT_INFO struct:
  1045. * port_num User Ethernet port number.
  1046. * port_phy_addr User PHY address of Ethernet port.
  1047. * port_mac_addr[6] User defined port MAC address.
  1048. * port_config User port configuration value.
  1049. * port_config_extend User port config extend value.
  1050. * port_sdma_config User port SDMA config value.
  1051. * port_serial_control User port serial control value.
  1052. * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
  1053. * *port_private User scratch pad for user specific data structures.
  1054. *
  1055. * This driver introduce a set of default values:
  1056. * PORT_CONFIG_VALUE Default port configuration value
  1057. * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
  1058. * PORT_SDMA_CONFIG_VALUE Default sdma control value
  1059. * PORT_SERIAL_CONTROL_VALUE Default port serial control value
  1060. *
  1061. * This driver data flow is done using the PKT_INFO struct which is
  1062. * a unified struct for Rx and Tx operations:
  1063. * byte_cnt Tx/Rx descriptor buffer byte count.
  1064. * l4i_chk CPU provided TCP Checksum. For Tx operation only.
  1065. * cmd_sts Tx/Rx descriptor command status.
  1066. * buf_ptr Tx/Rx descriptor buffer pointer.
  1067. * return_info Tx/Rx user resource return information.
  1068. *
  1069. *
  1070. * EXTERNAL SUPPORT REQUIREMENTS
  1071. *
  1072. * This driver requires the following external support:
  1073. *
  1074. * D_CACHE_FLUSH_LINE (address, address offset)
  1075. *
  1076. * This macro applies assembly code to flush and invalidate cache
  1077. * line.
  1078. * address - address base.
  1079. * address offset - address offset
  1080. *
  1081. *
  1082. * CPU_PIPE_FLUSH
  1083. *
  1084. * This macro applies assembly code to flush the CPU pipeline.
  1085. *
  1086. *******************************************************************************/
  1087. /* includes */
  1088. /* defines */
  1089. /* SDMA command macros */
  1090. #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
  1091. MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
  1092. #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
  1093. MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
  1094. (1 << (8 + tx_queue)))
  1095. #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
  1096. MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
  1097. #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
  1098. MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
  1099. #define CURR_RFD_GET(p_curr_desc, queue) \
  1100. ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
  1101. #define CURR_RFD_SET(p_curr_desc, queue) \
  1102. (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
  1103. #define USED_RFD_GET(p_used_desc, queue) \
  1104. ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
  1105. #define USED_RFD_SET(p_used_desc, queue)\
  1106. (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
  1107. #define CURR_TFD_GET(p_curr_desc, queue) \
  1108. ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
  1109. #define CURR_TFD_SET(p_curr_desc, queue) \
  1110. (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
  1111. #define USED_TFD_GET(p_used_desc, queue) \
  1112. ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
  1113. #define USED_TFD_SET(p_used_desc, queue) \
  1114. (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
  1115. #define FIRST_TFD_GET(p_first_desc, queue) \
  1116. ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
  1117. #define FIRST_TFD_SET(p_first_desc, queue) \
  1118. (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
  1119. /* Macros that save access to desc in order to find next desc pointer */
  1120. #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
  1121. #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
  1122. #define LINK_UP_TIMEOUT 100000
  1123. #define PHY_BUSY_TIMEOUT 10000000
  1124. /* locals */
  1125. /* PHY routines */
  1126. static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
  1127. static int ethernet_phy_get (ETH_PORT eth_port_num);
  1128. /* Ethernet Port routines */
  1129. static void eth_set_access_control (ETH_PORT eth_port_num,
  1130. ETH_WIN_PARAM * param);
  1131. static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
  1132. ETH_QUEUE queue, int option);
  1133. #if 0 /* FIXME */
  1134. static bool eth_port_smc_addr (ETH_PORT eth_port_num,
  1135. unsigned char mc_byte,
  1136. ETH_QUEUE queue, int option);
  1137. static bool eth_port_omc_addr (ETH_PORT eth_port_num,
  1138. unsigned char crc8,
  1139. ETH_QUEUE queue, int option);
  1140. #endif
  1141. static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
  1142. int byte_count);
  1143. void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
  1144. typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
  1145. u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
  1146. {
  1147. u32 result = 0;
  1148. u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
  1149. if (enable & (1 << bank))
  1150. return 0;
  1151. if (bank == BANK0)
  1152. result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
  1153. if (bank == BANK1)
  1154. result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
  1155. if (bank == BANK2)
  1156. result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
  1157. if (bank == BANK3)
  1158. result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
  1159. result &= 0x0000ffff;
  1160. result = result << 16;
  1161. return result;
  1162. }
  1163. u32 mv_get_dram_bank_size (MEMORY_BANK bank)
  1164. {
  1165. u32 result = 0;
  1166. u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
  1167. if (enable & (1 << bank))
  1168. return 0;
  1169. if (bank == BANK0)
  1170. result = MV_REG_READ (MV64460_CS_0_SIZE);
  1171. if (bank == BANK1)
  1172. result = MV_REG_READ (MV64460_CS_1_SIZE);
  1173. if (bank == BANK2)
  1174. result = MV_REG_READ (MV64460_CS_2_SIZE);
  1175. if (bank == BANK3)
  1176. result = MV_REG_READ (MV64460_CS_3_SIZE);
  1177. result += 1;
  1178. result &= 0x0000ffff;
  1179. result = result << 16;
  1180. return result;
  1181. }
  1182. u32 mv_get_internal_sram_base (void)
  1183. {
  1184. u32 result;
  1185. result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
  1186. result &= 0x0000ffff;
  1187. result = result << 16;
  1188. return result;
  1189. }
  1190. /*******************************************************************************
  1191. * eth_port_init - Initialize the Ethernet port driver
  1192. *
  1193. * DESCRIPTION:
  1194. * This function prepares the ethernet port to start its activity:
  1195. * 1) Completes the ethernet port driver struct initialization toward port
  1196. * start routine.
  1197. * 2) Resets the device to a quiescent state in case of warm reboot.
  1198. * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
  1199. * 4) Clean MAC tables. The reset status of those tables is unknown.
  1200. * 5) Set PHY address.
  1201. * Note: Call this routine prior to eth_port_start routine and after setting
  1202. * user values in the user fields of Ethernet port control struct (i.e.
  1203. * port_phy_addr).
  1204. *
  1205. * INPUT:
  1206. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
  1207. *
  1208. * OUTPUT:
  1209. * See description.
  1210. *
  1211. * RETURN:
  1212. * None.
  1213. *
  1214. *******************************************************************************/
  1215. static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
  1216. {
  1217. int queue;
  1218. ETH_WIN_PARAM win_param;
  1219. p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
  1220. p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
  1221. p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
  1222. p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
  1223. p_eth_port_ctrl->port_rx_queue_command = 0;
  1224. p_eth_port_ctrl->port_tx_queue_command = 0;
  1225. /* Zero out SW structs */
  1226. for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
  1227. CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
  1228. USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
  1229. p_eth_port_ctrl->rx_resource_err[queue] = false;
  1230. }
  1231. for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
  1232. CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
  1233. USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
  1234. FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
  1235. p_eth_port_ctrl->tx_resource_err[queue] = false;
  1236. }
  1237. eth_port_reset (p_eth_port_ctrl->port_num);
  1238. /* Set access parameters for DRAM bank 0 */
  1239. win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
  1240. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1241. win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
  1242. #ifndef CONFIG_NOT_COHERENT_CACHE
  1243. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1244. #endif
  1245. win_param.high_addr = 0;
  1246. /* Get bank base */
  1247. win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
  1248. win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
  1249. if (win_param.size == 0)
  1250. win_param.enable = 0;
  1251. else
  1252. win_param.enable = 1; /* Enable the access */
  1253. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1254. /* Set the access control for address window (EPAPR) READ & WRITE */
  1255. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1256. /* Set access parameters for DRAM bank 1 */
  1257. win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
  1258. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1259. win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
  1260. #ifndef CONFIG_NOT_COHERENT_CACHE
  1261. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1262. #endif
  1263. win_param.high_addr = 0;
  1264. /* Get bank base */
  1265. win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
  1266. win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
  1267. if (win_param.size == 0)
  1268. win_param.enable = 0;
  1269. else
  1270. win_param.enable = 1; /* Enable the access */
  1271. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1272. /* Set the access control for address window (EPAPR) READ & WRITE */
  1273. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1274. /* Set access parameters for DRAM bank 2 */
  1275. win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
  1276. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1277. win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
  1278. #ifndef CONFIG_NOT_COHERENT_CACHE
  1279. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1280. #endif
  1281. win_param.high_addr = 0;
  1282. /* Get bank base */
  1283. win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
  1284. win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
  1285. if (win_param.size == 0)
  1286. win_param.enable = 0;
  1287. else
  1288. win_param.enable = 1; /* Enable the access */
  1289. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1290. /* Set the access control for address window (EPAPR) READ & WRITE */
  1291. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1292. /* Set access parameters for DRAM bank 3 */
  1293. win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
  1294. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1295. win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
  1296. #ifndef CONFIG_NOT_COHERENT_CACHE
  1297. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1298. #endif
  1299. win_param.high_addr = 0;
  1300. /* Get bank base */
  1301. win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
  1302. win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
  1303. if (win_param.size == 0)
  1304. win_param.enable = 0;
  1305. else
  1306. win_param.enable = 1; /* Enable the access */
  1307. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1308. /* Set the access control for address window (EPAPR) READ & WRITE */
  1309. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1310. /* Set access parameters for Internal SRAM */
  1311. win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
  1312. win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
  1313. win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
  1314. win_param.high_addr = 0;
  1315. win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
  1316. win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */
  1317. win_param.enable = 1; /* Enable the access */
  1318. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1319. /* Set the access control for address window (EPAPR) READ & WRITE */
  1320. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1321. eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
  1322. ethernet_phy_set (p_eth_port_ctrl->port_num,
  1323. p_eth_port_ctrl->port_phy_addr);
  1324. return;
  1325. }
  1326. /*******************************************************************************
  1327. * eth_port_start - Start the Ethernet port activity.
  1328. *
  1329. * DESCRIPTION:
  1330. * This routine prepares the Ethernet port for Rx and Tx activity:
  1331. * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
  1332. * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
  1333. * for Tx and ether_init_rx_desc_ring for Rx)
  1334. * 2. Initialize and enable the Ethernet configuration port by writing to
  1335. * the port's configuration and command registers.
  1336. * 3. Initialize and enable the SDMA by writing to the SDMA's
  1337. * configuration and command registers.
  1338. * After completing these steps, the ethernet port SDMA can starts to
  1339. * perform Rx and Tx activities.
  1340. *
  1341. * Note: Each Rx and Tx queue descriptor's list must be initialized prior
  1342. * to calling this function (use ether_init_tx_desc_ring for Tx queues and
  1343. * ether_init_rx_desc_ring for Rx queues).
  1344. *
  1345. * INPUT:
  1346. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
  1347. *
  1348. * OUTPUT:
  1349. * Ethernet port is ready to receive and transmit.
  1350. *
  1351. * RETURN:
  1352. * false if the port PHY is not up.
  1353. * true otherwise.
  1354. *
  1355. *******************************************************************************/
  1356. static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
  1357. {
  1358. int queue;
  1359. volatile ETH_TX_DESC *p_tx_curr_desc;
  1360. volatile ETH_RX_DESC *p_rx_curr_desc;
  1361. unsigned int phy_reg_data;
  1362. ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
  1363. /* Assignment of Tx CTRP of given queue */
  1364. for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
  1365. CURR_TFD_GET (p_tx_curr_desc, queue);
  1366. MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
  1367. (eth_port_num)
  1368. + (4 * queue)),
  1369. ((unsigned int) p_tx_curr_desc));
  1370. }
  1371. /* Assignment of Rx CRDP of given queue */
  1372. for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
  1373. CURR_RFD_GET (p_rx_curr_desc, queue);
  1374. MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
  1375. (eth_port_num)
  1376. + (4 * queue)),
  1377. ((unsigned int) p_rx_curr_desc));
  1378. if (p_rx_curr_desc != NULL)
  1379. /* Add the assigned Ethernet address to the port's address table */
  1380. eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
  1381. p_eth_port_ctrl->port_mac_addr,
  1382. queue);
  1383. }
  1384. /* Assign port configuration and command. */
  1385. MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
  1386. p_eth_port_ctrl->port_config);
  1387. MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
  1388. p_eth_port_ctrl->port_config_extend);
  1389. MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
  1390. p_eth_port_ctrl->port_serial_control);
  1391. MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
  1392. ETH_SERIAL_PORT_ENABLE);
  1393. /* Assign port SDMA configuration */
  1394. MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
  1395. p_eth_port_ctrl->port_sdma_config);
  1396. MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
  1397. (eth_port_num), 0x3fffffff);
  1398. MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
  1399. (eth_port_num), 0x03fffcff);
  1400. /* Turn off the port/queue bandwidth limitation */
  1401. MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
  1402. /* Enable port Rx. */
  1403. MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
  1404. p_eth_port_ctrl->port_rx_queue_command);
  1405. /* Check if link is up */
  1406. eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
  1407. if (!(phy_reg_data & 0x20))
  1408. return false;
  1409. return true;
  1410. }
  1411. /*******************************************************************************
  1412. * eth_port_uc_addr_set - This function Set the port Unicast address.
  1413. *
  1414. * DESCRIPTION:
  1415. * This function Set the port Ethernet MAC address.
  1416. *
  1417. * INPUT:
  1418. * ETH_PORT eth_port_num Port number.
  1419. * char * p_addr Address to be set
  1420. * ETH_QUEUE queue Rx queue number for this MAC address.
  1421. *
  1422. * OUTPUT:
  1423. * Set MAC address low and high registers. also calls eth_port_uc_addr()
  1424. * To set the unicast table with the proper information.
  1425. *
  1426. * RETURN:
  1427. * N/A.
  1428. *
  1429. *******************************************************************************/
  1430. static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
  1431. unsigned char *p_addr, ETH_QUEUE queue)
  1432. {
  1433. unsigned int mac_h;
  1434. unsigned int mac_l;
  1435. mac_l = (p_addr[4] << 8) | (p_addr[5]);
  1436. mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
  1437. (p_addr[2] << 8) | (p_addr[3] << 0);
  1438. MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
  1439. MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
  1440. /* Accept frames of this address */
  1441. eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
  1442. return;
  1443. }
  1444. /*******************************************************************************
  1445. * eth_port_uc_addr - This function Set the port unicast address table
  1446. *
  1447. * DESCRIPTION:
  1448. * This function locates the proper entry in the Unicast table for the
  1449. * specified MAC nibble and sets its properties according to function
  1450. * parameters.
  1451. *
  1452. * INPUT:
  1453. * ETH_PORT eth_port_num Port number.
  1454. * unsigned char uc_nibble Unicast MAC Address last nibble.
  1455. * ETH_QUEUE queue Rx queue number for this MAC address.
  1456. * int option 0 = Add, 1 = remove address.
  1457. *
  1458. * OUTPUT:
  1459. * This function add/removes MAC addresses from the port unicast address
  1460. * table.
  1461. *
  1462. * RETURN:
  1463. * true is output succeeded.
  1464. * false if option parameter is invalid.
  1465. *
  1466. *******************************************************************************/
  1467. static bool eth_port_uc_addr (ETH_PORT eth_port_num,
  1468. unsigned char uc_nibble,
  1469. ETH_QUEUE queue, int option)
  1470. {
  1471. unsigned int unicast_reg;
  1472. unsigned int tbl_offset;
  1473. unsigned int reg_offset;
  1474. /* Locate the Unicast table entry */
  1475. uc_nibble = (0xf & uc_nibble);
  1476. tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
  1477. reg_offset = uc_nibble % 4; /* Entry offset within the above register */
  1478. switch (option) {
  1479. case REJECT_MAC_ADDR:
  1480. /* Clear accepts frame bit at specified unicast DA table entry */
  1481. unicast_reg =
  1482. MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1483. (eth_port_num)
  1484. + tbl_offset));
  1485. unicast_reg &= (0x0E << (8 * reg_offset));
  1486. MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1487. (eth_port_num)
  1488. + tbl_offset), unicast_reg);
  1489. break;
  1490. case ACCEPT_MAC_ADDR:
  1491. /* Set accepts frame bit at unicast DA filter table entry */
  1492. unicast_reg =
  1493. MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1494. (eth_port_num)
  1495. + tbl_offset));
  1496. unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
  1497. MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1498. (eth_port_num)
  1499. + tbl_offset), unicast_reg);
  1500. break;
  1501. default:
  1502. return false;
  1503. }
  1504. return true;
  1505. }
  1506. #if 0 /* FIXME */
  1507. /*******************************************************************************
  1508. * eth_port_mc_addr - Multicast address settings.
  1509. *
  1510. * DESCRIPTION:
  1511. * This API controls the MV device MAC multicast support.
  1512. * The MV device supports multicast using two tables:
  1513. * 1) Special Multicast Table for MAC addresses of the form
  1514. * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
  1515. * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
  1516. * Table entries in the DA-Filter table.
  1517. * In this case, the function calls eth_port_smc_addr() routine to set the
  1518. * Special Multicast Table.
  1519. * 2) Other Multicast Table for multicast of another type. A CRC-8bit
  1520. * is used as an index to the Other Multicast Table entries in the
  1521. * DA-Filter table.
  1522. * In this case, the function calculates the CRC-8bit value and calls
  1523. * eth_port_omc_addr() routine to set the Other Multicast Table.
  1524. * INPUT:
  1525. * ETH_PORT eth_port_num Port number.
  1526. * unsigned char *p_addr Unicast MAC Address.
  1527. * ETH_QUEUE queue Rx queue number for this MAC address.
  1528. * int option 0 = Add, 1 = remove address.
  1529. *
  1530. * OUTPUT:
  1531. * See description.
  1532. *
  1533. * RETURN:
  1534. * true is output succeeded.
  1535. * false if add_address_table_entry( ) failed.
  1536. *
  1537. *******************************************************************************/
  1538. static void eth_port_mc_addr (ETH_PORT eth_port_num,
  1539. unsigned char *p_addr,
  1540. ETH_QUEUE queue, int option)
  1541. {
  1542. unsigned int mac_h;
  1543. unsigned int mac_l;
  1544. unsigned char crc_result = 0;
  1545. int mac_array[48];
  1546. int crc[8];
  1547. int i;
  1548. if ((p_addr[0] == 0x01) &&
  1549. (p_addr[1] == 0x00) &&
  1550. (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
  1551. eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
  1552. else {
  1553. /* Calculate CRC-8 out of the given address */
  1554. mac_h = (p_addr[0] << 8) | (p_addr[1]);
  1555. mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
  1556. (p_addr[4] << 8) | (p_addr[5] << 0);
  1557. for (i = 0; i < 32; i++)
  1558. mac_array[i] = (mac_l >> i) & 0x1;
  1559. for (i = 32; i < 48; i++)
  1560. mac_array[i] = (mac_h >> (i - 32)) & 0x1;
  1561. crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
  1562. mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
  1563. mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
  1564. mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
  1565. mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
  1566. mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
  1567. mac_array[6] ^ mac_array[0];
  1568. crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
  1569. mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
  1570. mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
  1571. mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
  1572. mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
  1573. mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
  1574. mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
  1575. mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
  1576. mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
  1577. mac_array[0];
  1578. crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
  1579. mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
  1580. mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
  1581. mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
  1582. mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
  1583. mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
  1584. mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
  1585. mac_array[2] ^ mac_array[1] ^ mac_array[0];
  1586. crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
  1587. mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
  1588. mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
  1589. mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
  1590. mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
  1591. mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
  1592. mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
  1593. mac_array[2] ^ mac_array[1];
  1594. crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
  1595. mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
  1596. mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
  1597. mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
  1598. mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
  1599. mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
  1600. mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
  1601. mac_array[2];
  1602. crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
  1603. mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
  1604. mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
  1605. mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
  1606. mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
  1607. mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
  1608. mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
  1609. mac_array[3];
  1610. crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
  1611. mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
  1612. mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
  1613. mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
  1614. mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
  1615. mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
  1616. mac_array[6] ^ mac_array[5] ^ mac_array[4];
  1617. crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
  1618. mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
  1619. mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
  1620. mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
  1621. mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
  1622. mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
  1623. mac_array[6] ^ mac_array[5];
  1624. for (i = 0; i < 8; i++)
  1625. crc_result = crc_result | (crc[i] << i);
  1626. eth_port_omc_addr (eth_port_num, crc_result, queue, option);
  1627. }
  1628. return;
  1629. }
  1630. /*******************************************************************************
  1631. * eth_port_smc_addr - Special Multicast address settings.
  1632. *
  1633. * DESCRIPTION:
  1634. * This routine controls the MV device special MAC multicast support.
  1635. * The Special Multicast Table for MAC addresses supports MAC of the form
  1636. * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
  1637. * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
  1638. * Table entries in the DA-Filter table.
  1639. * This function set the Special Multicast Table appropriate entry
  1640. * according to the argument given.
  1641. *
  1642. * INPUT:
  1643. * ETH_PORT eth_port_num Port number.
  1644. * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
  1645. * ETH_QUEUE queue Rx queue number for this MAC address.
  1646. * int option 0 = Add, 1 = remove address.
  1647. *
  1648. * OUTPUT:
  1649. * See description.
  1650. *
  1651. * RETURN:
  1652. * true is output succeeded.
  1653. * false if option parameter is invalid.
  1654. *
  1655. *******************************************************************************/
  1656. static bool eth_port_smc_addr (ETH_PORT eth_port_num,
  1657. unsigned char mc_byte,
  1658. ETH_QUEUE queue, int option)
  1659. {
  1660. unsigned int smc_table_reg;
  1661. unsigned int tbl_offset;
  1662. unsigned int reg_offset;
  1663. /* Locate the SMC table entry */
  1664. tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
  1665. reg_offset = mc_byte % 4; /* Entry offset within the above register */
  1666. queue &= 0x7;
  1667. switch (option) {
  1668. case REJECT_MAC_ADDR:
  1669. /* Clear accepts frame bit at specified Special DA table entry */
  1670. smc_table_reg =
  1671. MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1672. smc_table_reg &= (0x0E << (8 * reg_offset));
  1673. MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
  1674. break;
  1675. case ACCEPT_MAC_ADDR:
  1676. /* Set accepts frame bit at specified Special DA table entry */
  1677. smc_table_reg =
  1678. MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1679. smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
  1680. MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
  1681. break;
  1682. default:
  1683. return false;
  1684. }
  1685. return true;
  1686. }
  1687. /*******************************************************************************
  1688. * eth_port_omc_addr - Multicast address settings.
  1689. *
  1690. * DESCRIPTION:
  1691. * This routine controls the MV device Other MAC multicast support.
  1692. * The Other Multicast Table is used for multicast of another type.
  1693. * A CRC-8bit is used as an index to the Other Multicast Table entries
  1694. * in the DA-Filter table.
  1695. * The function gets the CRC-8bit value from the calling routine and
  1696. * set the Other Multicast Table appropriate entry according to the
  1697. * CRC-8 argument given.
  1698. *
  1699. * INPUT:
  1700. * ETH_PORT eth_port_num Port number.
  1701. * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
  1702. * ETH_QUEUE queue Rx queue number for this MAC address.
  1703. * int option 0 = Add, 1 = remove address.
  1704. *
  1705. * OUTPUT:
  1706. * See description.
  1707. *
  1708. * RETURN:
  1709. * true is output succeeded.
  1710. * false if option parameter is invalid.
  1711. *
  1712. *******************************************************************************/
  1713. static bool eth_port_omc_addr (ETH_PORT eth_port_num,
  1714. unsigned char crc8,
  1715. ETH_QUEUE queue, int option)
  1716. {
  1717. unsigned int omc_table_reg;
  1718. unsigned int tbl_offset;
  1719. unsigned int reg_offset;
  1720. /* Locate the OMC table entry */
  1721. tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
  1722. reg_offset = crc8 % 4; /* Entry offset within the above register */
  1723. queue &= 0x7;
  1724. switch (option) {
  1725. case REJECT_MAC_ADDR:
  1726. /* Clear accepts frame bit at specified Other DA table entry */
  1727. omc_table_reg =
  1728. MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1729. omc_table_reg &= (0x0E << (8 * reg_offset));
  1730. MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
  1731. break;
  1732. case ACCEPT_MAC_ADDR:
  1733. /* Set accepts frame bit at specified Other DA table entry */
  1734. omc_table_reg =
  1735. MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1736. omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
  1737. MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
  1738. break;
  1739. default:
  1740. return false;
  1741. }
  1742. return true;
  1743. }
  1744. #endif
  1745. /*******************************************************************************
  1746. * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
  1747. *
  1748. * DESCRIPTION:
  1749. * Go through all the DA filter tables (Unicast, Special Multicast & Other
  1750. * Multicast) and set each entry to 0.
  1751. *
  1752. * INPUT:
  1753. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1754. *
  1755. * OUTPUT:
  1756. * Multicast and Unicast packets are rejected.
  1757. *
  1758. * RETURN:
  1759. * None.
  1760. *
  1761. *******************************************************************************/
  1762. static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
  1763. {
  1764. int table_index;
  1765. /* Clear DA filter unicast table (Ex_dFUT) */
  1766. for (table_index = 0; table_index <= 0xC; table_index += 4)
  1767. MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1768. (eth_port_num) + table_index), 0);
  1769. for (table_index = 0; table_index <= 0xFC; table_index += 4) {
  1770. /* Clear DA filter special multicast table (Ex_dFSMT) */
  1771. MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
  1772. /* Clear DA filter other multicast table (Ex_dFOMT) */
  1773. MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
  1774. }
  1775. }
  1776. /*******************************************************************************
  1777. * eth_clear_mib_counters - Clear all MIB counters
  1778. *
  1779. * DESCRIPTION:
  1780. * This function clears all MIB counters of a specific ethernet port.
  1781. * A read from the MIB counter will reset the counter.
  1782. *
  1783. * INPUT:
  1784. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1785. *
  1786. * OUTPUT:
  1787. * After reading all MIB counters, the counters resets.
  1788. *
  1789. * RETURN:
  1790. * MIB counter value.
  1791. *
  1792. *******************************************************************************/
  1793. static void eth_clear_mib_counters (ETH_PORT eth_port_num)
  1794. {
  1795. int i;
  1796. unsigned int dummy;
  1797. /* Perform dummy reads from MIB counters */
  1798. for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
  1799. i += 4)
  1800. dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
  1801. (eth_port_num) + i));
  1802. return;
  1803. }
  1804. /*******************************************************************************
  1805. * eth_read_mib_counter - Read a MIB counter
  1806. *
  1807. * DESCRIPTION:
  1808. * This function reads a MIB counter of a specific ethernet port.
  1809. * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
  1810. * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
  1811. * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
  1812. * ETH_MIB_GOOD_OCTETS_SENT_HIGH
  1813. *
  1814. * INPUT:
  1815. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1816. * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
  1817. *
  1818. * OUTPUT:
  1819. * After reading the MIB counter, the counter resets.
  1820. *
  1821. * RETURN:
  1822. * MIB counter value.
  1823. *
  1824. *******************************************************************************/
  1825. unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
  1826. unsigned int mib_offset)
  1827. {
  1828. return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
  1829. + mib_offset));
  1830. }
  1831. /*******************************************************************************
  1832. * ethernet_phy_set - Set the ethernet port PHY address.
  1833. *
  1834. * DESCRIPTION:
  1835. * This routine set the ethernet port PHY address according to given
  1836. * parameter.
  1837. *
  1838. * INPUT:
  1839. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1840. *
  1841. * OUTPUT:
  1842. * Set PHY Address Register with given PHY address parameter.
  1843. *
  1844. * RETURN:
  1845. * None.
  1846. *
  1847. *******************************************************************************/
  1848. static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
  1849. {
  1850. unsigned int reg_data;
  1851. reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
  1852. reg_data &= ~(0x1F << (5 * eth_port_num));
  1853. reg_data |= (phy_addr << (5 * eth_port_num));
  1854. MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
  1855. return;
  1856. }
  1857. /*******************************************************************************
  1858. * ethernet_phy_get - Get the ethernet port PHY address.
  1859. *
  1860. * DESCRIPTION:
  1861. * This routine returns the given ethernet port PHY address.
  1862. *
  1863. * INPUT:
  1864. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1865. *
  1866. * OUTPUT:
  1867. * None.
  1868. *
  1869. * RETURN:
  1870. * PHY address.
  1871. *
  1872. *******************************************************************************/
  1873. static int ethernet_phy_get (ETH_PORT eth_port_num)
  1874. {
  1875. unsigned int reg_data;
  1876. reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
  1877. return ((reg_data >> (5 * eth_port_num)) & 0x1f);
  1878. }
  1879. /*******************************************************************************
  1880. * ethernet_phy_reset - Reset Ethernet port PHY.
  1881. *
  1882. * DESCRIPTION:
  1883. * This routine utilize the SMI interface to reset the ethernet port PHY.
  1884. * The routine waits until the link is up again or link up is timeout.
  1885. *
  1886. * INPUT:
  1887. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1888. *
  1889. * OUTPUT:
  1890. * The ethernet port PHY renew its link.
  1891. *
  1892. * RETURN:
  1893. * None.
  1894. *
  1895. *******************************************************************************/
  1896. static bool ethernet_phy_reset (ETH_PORT eth_port_num)
  1897. {
  1898. unsigned int time_out = 50;
  1899. unsigned int phy_reg_data;
  1900. /* Reset the PHY */
  1901. eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
  1902. phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
  1903. eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
  1904. /* Poll on the PHY LINK */
  1905. do {
  1906. eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
  1907. if (time_out-- == 0)
  1908. return false;
  1909. }
  1910. while (!(phy_reg_data & 0x20));
  1911. return true;
  1912. }
  1913. /*******************************************************************************
  1914. * eth_port_reset - Reset Ethernet port
  1915. *
  1916. * DESCRIPTION:
  1917. * This routine resets the chip by aborting any SDMA engine activity and
  1918. * clearing the MIB counters. The Receiver and the Transmit unit are in
  1919. * idle state after this command is performed and the port is disabled.
  1920. *
  1921. * INPUT:
  1922. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1923. *
  1924. * OUTPUT:
  1925. * Channel activity is halted.
  1926. *
  1927. * RETURN:
  1928. * None.
  1929. *
  1930. *******************************************************************************/
  1931. static void eth_port_reset (ETH_PORT eth_port_num)
  1932. {
  1933. unsigned int reg_data;
  1934. /* Stop Tx port activity. Check port Tx activity. */
  1935. reg_data =
  1936. MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
  1937. (eth_port_num));
  1938. if (reg_data & 0xFF) {
  1939. /* Issue stop command for active channels only */
  1940. MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
  1941. (eth_port_num), (reg_data << 8));
  1942. /* Wait for all Tx activity to terminate. */
  1943. do {
  1944. /* Check port cause register that all Tx queues are stopped */
  1945. reg_data =
  1946. MV_REG_READ
  1947. (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
  1948. (eth_port_num));
  1949. }
  1950. while (reg_data & 0xFF);
  1951. }
  1952. /* Stop Rx port activity. Check port Rx activity. */
  1953. reg_data =
  1954. MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
  1955. (eth_port_num));
  1956. if (reg_data & 0xFF) {
  1957. /* Issue stop command for active channels only */
  1958. MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
  1959. (eth_port_num), (reg_data << 8));
  1960. /* Wait for all Rx activity to terminate. */
  1961. do {
  1962. /* Check port cause register that all Rx queues are stopped */
  1963. reg_data =
  1964. MV_REG_READ
  1965. (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
  1966. (eth_port_num));
  1967. }
  1968. while (reg_data & 0xFF);
  1969. }
  1970. /* Clear all MIB counters */
  1971. eth_clear_mib_counters (eth_port_num);
  1972. /* Reset the Enable bit in the Configuration Register */
  1973. reg_data =
  1974. MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
  1975. (eth_port_num));
  1976. reg_data &= ~ETH_SERIAL_PORT_ENABLE;
  1977. MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
  1978. reg_data);
  1979. return;
  1980. }
  1981. #if 0 /* Not needed here */
  1982. /*******************************************************************************
  1983. * ethernet_set_config_reg - Set specified bits in configuration register.
  1984. *
  1985. * DESCRIPTION:
  1986. * This function sets specified bits in the given ethernet
  1987. * configuration register.
  1988. *
  1989. * INPUT:
  1990. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1991. * unsigned int value 32 bit value.
  1992. *
  1993. * OUTPUT:
  1994. * The set bits in the value parameter are set in the configuration
  1995. * register.
  1996. *
  1997. * RETURN:
  1998. * None.
  1999. *
  2000. *******************************************************************************/
  2001. static void ethernet_set_config_reg (ETH_PORT eth_port_num,
  2002. unsigned int value)
  2003. {
  2004. unsigned int eth_config_reg;
  2005. eth_config_reg =
  2006. MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
  2007. eth_config_reg |= value;
  2008. MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
  2009. eth_config_reg);
  2010. return;
  2011. }
  2012. #endif
  2013. #if 0 /* FIXME */
  2014. /*******************************************************************************
  2015. * ethernet_reset_config_reg - Reset specified bits in configuration register.
  2016. *
  2017. * DESCRIPTION:
  2018. * This function resets specified bits in the given Ethernet
  2019. * configuration register.
  2020. *
  2021. * INPUT:
  2022. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2023. * unsigned int value 32 bit value.
  2024. *
  2025. * OUTPUT:
  2026. * The set bits in the value parameter are reset in the configuration
  2027. * register.
  2028. *
  2029. * RETURN:
  2030. * None.
  2031. *
  2032. *******************************************************************************/
  2033. static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
  2034. unsigned int value)
  2035. {
  2036. unsigned int eth_config_reg;
  2037. eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
  2038. (eth_port_num));
  2039. eth_config_reg &= ~value;
  2040. MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
  2041. eth_config_reg);
  2042. return;
  2043. }
  2044. #endif
  2045. #if 0 /* Not needed here */
  2046. /*******************************************************************************
  2047. * ethernet_get_config_reg - Get the port configuration register
  2048. *
  2049. * DESCRIPTION:
  2050. * This function returns the configuration register value of the given
  2051. * ethernet port.
  2052. *
  2053. * INPUT:
  2054. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2055. *
  2056. * OUTPUT:
  2057. * None.
  2058. *
  2059. * RETURN:
  2060. * Port configuration register value.
  2061. *
  2062. *******************************************************************************/
  2063. static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
  2064. {
  2065. unsigned int eth_config_reg;
  2066. eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
  2067. (eth_port_num));
  2068. return eth_config_reg;
  2069. }
  2070. #endif
  2071. /*******************************************************************************
  2072. * eth_port_read_smi_reg - Read PHY registers
  2073. *
  2074. * DESCRIPTION:
  2075. * This routine utilize the SMI interface to interact with the PHY in
  2076. * order to perform PHY register read.
  2077. *
  2078. * INPUT:
  2079. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2080. * unsigned int phy_reg PHY register address offset.
  2081. * unsigned int *value Register value buffer.
  2082. *
  2083. * OUTPUT:
  2084. * Write the value of a specified PHY register into given buffer.
  2085. *
  2086. * RETURN:
  2087. * false if the PHY is busy or read data is not in valid state.
  2088. * true otherwise.
  2089. *
  2090. *******************************************************************************/
  2091. static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
  2092. unsigned int phy_reg, unsigned int *value)
  2093. {
  2094. unsigned int reg_value;
  2095. unsigned int time_out = PHY_BUSY_TIMEOUT;
  2096. int phy_addr;
  2097. phy_addr = ethernet_phy_get (eth_port_num);
  2098. /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
  2099. /* first check that it is not busy */
  2100. do {
  2101. reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
  2102. if (time_out-- == 0) {
  2103. return false;
  2104. }
  2105. }
  2106. while (reg_value & ETH_SMI_BUSY);
  2107. /* not busy */
  2108. MV_REG_WRITE (MV64460_ETH_SMI_REG,
  2109. (phy_addr << 16) | (phy_reg << 21) |
  2110. ETH_SMI_OPCODE_READ);
  2111. time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
  2112. do {
  2113. reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
  2114. if (time_out-- == 0) {
  2115. return false;
  2116. }
  2117. }
  2118. while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
  2119. /* Wait for the data to update in the SMI register */
  2120. #define PHY_UPDATE_TIMEOUT 10000
  2121. for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
  2122. reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
  2123. *value = reg_value & 0xffff;
  2124. return true;
  2125. }
  2126. /*******************************************************************************
  2127. * eth_port_write_smi_reg - Write to PHY registers
  2128. *
  2129. * DESCRIPTION:
  2130. * This routine utilize the SMI interface to interact with the PHY in
  2131. * order to perform writes to PHY registers.
  2132. *
  2133. * INPUT:
  2134. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2135. * unsigned int phy_reg PHY register address offset.
  2136. * unsigned int value Register value.
  2137. *
  2138. * OUTPUT:
  2139. * Write the given value to the specified PHY register.
  2140. *
  2141. * RETURN:
  2142. * false if the PHY is busy.
  2143. * true otherwise.
  2144. *
  2145. *******************************************************************************/
  2146. static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
  2147. unsigned int phy_reg, unsigned int value)
  2148. {
  2149. unsigned int reg_value;
  2150. unsigned int time_out = PHY_BUSY_TIMEOUT;
  2151. int phy_addr;
  2152. phy_addr = ethernet_phy_get (eth_port_num);
  2153. /* first check that it is not busy */
  2154. do {
  2155. reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
  2156. if (time_out-- == 0) {
  2157. return false;
  2158. }
  2159. }
  2160. while (reg_value & ETH_SMI_BUSY);
  2161. /* not busy */
  2162. MV_REG_WRITE (MV64460_ETH_SMI_REG,
  2163. (phy_addr << 16) | (phy_reg << 21) |
  2164. ETH_SMI_OPCODE_WRITE | (value & 0xffff));
  2165. return true;
  2166. }
  2167. /*******************************************************************************
  2168. * eth_set_access_control - Config address decode parameters for Ethernet unit
  2169. *
  2170. * DESCRIPTION:
  2171. * This function configures the address decode parameters for the Gigabit
  2172. * Ethernet Controller according the given parameters struct.
  2173. *
  2174. * INPUT:
  2175. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2176. * ETH_WIN_PARAM *param Address decode parameter struct.
  2177. *
  2178. * OUTPUT:
  2179. * An access window is opened using the given access parameters.
  2180. *
  2181. * RETURN:
  2182. * None.
  2183. *
  2184. *******************************************************************************/
  2185. static void eth_set_access_control (ETH_PORT eth_port_num,
  2186. ETH_WIN_PARAM * param)
  2187. {
  2188. unsigned int access_prot_reg;
  2189. /* Set access control register */
  2190. access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
  2191. (eth_port_num));
  2192. access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
  2193. access_prot_reg |= (param->access_ctrl << (param->win * 2));
  2194. MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
  2195. access_prot_reg);
  2196. /* Set window Size reg (SR) */
  2197. MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
  2198. (ETH_SIZE_REG_GAP * param->win)),
  2199. (((param->size / 0x10000) - 1) << 16));
  2200. /* Set window Base address reg (BA) */
  2201. MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
  2202. (param->target | param->attributes | param->base_addr));
  2203. /* High address remap reg (HARR) */
  2204. if (param->win < 4)
  2205. MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
  2206. (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
  2207. param->high_addr);
  2208. /* Base address enable reg (BARER) */
  2209. if (param->enable == 1)
  2210. MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
  2211. (1 << param->win));
  2212. else
  2213. MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
  2214. (1 << param->win));
  2215. }
  2216. /*******************************************************************************
  2217. * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
  2218. *
  2219. * DESCRIPTION:
  2220. * This function prepares a Rx chained list of descriptors and packet
  2221. * buffers in a form of a ring. The routine must be called after port
  2222. * initialization routine and before port start routine.
  2223. * The Ethernet SDMA engine uses CPU bus addresses to access the various
  2224. * devices in the system (i.e. DRAM). This function uses the ethernet
  2225. * struct 'virtual to physical' routine (set by the user) to set the ring
  2226. * with physical addresses.
  2227. *
  2228. * INPUT:
  2229. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2230. * ETH_QUEUE rx_queue Number of Rx queue.
  2231. * int rx_desc_num Number of Rx descriptors
  2232. * int rx_buff_size Size of Rx buffer
  2233. * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
  2234. * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
  2235. *
  2236. * OUTPUT:
  2237. * The routine updates the Ethernet port control struct with information
  2238. * regarding the Rx descriptors and buffers.
  2239. *
  2240. * RETURN:
  2241. * false if the given descriptors memory area is not aligned according to
  2242. * Ethernet SDMA specifications.
  2243. * true otherwise.
  2244. *
  2245. *******************************************************************************/
  2246. static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  2247. ETH_QUEUE rx_queue,
  2248. int rx_desc_num,
  2249. int rx_buff_size,
  2250. unsigned int rx_desc_base_addr,
  2251. unsigned int rx_buff_base_addr)
  2252. {
  2253. ETH_RX_DESC *p_rx_desc;
  2254. ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
  2255. unsigned int buffer_addr;
  2256. int ix; /* a counter */
  2257. p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
  2258. p_rx_prev_desc = p_rx_desc;
  2259. buffer_addr = rx_buff_base_addr;
  2260. /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
  2261. if (rx_buff_base_addr & 0xF)
  2262. return false;
  2263. /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
  2264. if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
  2265. return false;
  2266. /* Rx buffers must be 64-bit aligned. */
  2267. if ((rx_buff_base_addr + rx_buff_size) & 0x7)
  2268. return false;
  2269. /* initialize the Rx descriptors ring */
  2270. for (ix = 0; ix < rx_desc_num; ix++) {
  2271. p_rx_desc->buf_size = rx_buff_size;
  2272. p_rx_desc->byte_cnt = 0x0000;
  2273. p_rx_desc->cmd_sts =
  2274. ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
  2275. p_rx_desc->next_desc_ptr =
  2276. ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
  2277. p_rx_desc->buf_ptr = buffer_addr;
  2278. p_rx_desc->return_info = 0x00000000;
  2279. D_CACHE_FLUSH_LINE (p_rx_desc, 0);
  2280. buffer_addr += rx_buff_size;
  2281. p_rx_prev_desc = p_rx_desc;
  2282. p_rx_desc = (ETH_RX_DESC *)
  2283. ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
  2284. }
  2285. /* Closing Rx descriptors ring */
  2286. p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
  2287. D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
  2288. /* Save Rx desc pointer to driver struct. */
  2289. CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
  2290. USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
  2291. p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
  2292. (ETH_RX_DESC *) rx_desc_base_addr;
  2293. p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
  2294. rx_desc_num * RX_DESC_ALIGNED_SIZE;
  2295. p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
  2296. return true;
  2297. }
  2298. /*******************************************************************************
  2299. * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
  2300. *
  2301. * DESCRIPTION:
  2302. * This function prepares a Tx chained list of descriptors and packet
  2303. * buffers in a form of a ring. The routine must be called after port
  2304. * initialization routine and before port start routine.
  2305. * The Ethernet SDMA engine uses CPU bus addresses to access the various
  2306. * devices in the system (i.e. DRAM). This function uses the ethernet
  2307. * struct 'virtual to physical' routine (set by the user) to set the ring
  2308. * with physical addresses.
  2309. *
  2310. * INPUT:
  2311. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2312. * ETH_QUEUE tx_queue Number of Tx queue.
  2313. * int tx_desc_num Number of Tx descriptors
  2314. * int tx_buff_size Size of Tx buffer
  2315. * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
  2316. * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
  2317. *
  2318. * OUTPUT:
  2319. * The routine updates the Ethernet port control struct with information
  2320. * regarding the Tx descriptors and buffers.
  2321. *
  2322. * RETURN:
  2323. * false if the given descriptors memory area is not aligned according to
  2324. * Ethernet SDMA specifications.
  2325. * true otherwise.
  2326. *
  2327. *******************************************************************************/
  2328. static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  2329. ETH_QUEUE tx_queue,
  2330. int tx_desc_num,
  2331. int tx_buff_size,
  2332. unsigned int tx_desc_base_addr,
  2333. unsigned int tx_buff_base_addr)
  2334. {
  2335. ETH_TX_DESC *p_tx_desc;
  2336. ETH_TX_DESC *p_tx_prev_desc;
  2337. unsigned int buffer_addr;
  2338. int ix; /* a counter */
  2339. /* save the first desc pointer to link with the last descriptor */
  2340. p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
  2341. p_tx_prev_desc = p_tx_desc;
  2342. buffer_addr = tx_buff_base_addr;
  2343. /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
  2344. if (tx_buff_base_addr & 0xF)
  2345. return false;
  2346. /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
  2347. if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
  2348. || (tx_buff_size < TX_BUFFER_MIN_SIZE))
  2349. return false;
  2350. /* Initialize the Tx descriptors ring */
  2351. for (ix = 0; ix < tx_desc_num; ix++) {
  2352. p_tx_desc->byte_cnt = 0x0000;
  2353. p_tx_desc->l4i_chk = 0x0000;
  2354. p_tx_desc->cmd_sts = 0x00000000;
  2355. p_tx_desc->next_desc_ptr =
  2356. ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
  2357. p_tx_desc->buf_ptr = buffer_addr;
  2358. p_tx_desc->return_info = 0x00000000;
  2359. D_CACHE_FLUSH_LINE (p_tx_desc, 0);
  2360. buffer_addr += tx_buff_size;
  2361. p_tx_prev_desc = p_tx_desc;
  2362. p_tx_desc = (ETH_TX_DESC *)
  2363. ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
  2364. }
  2365. /* Closing Tx descriptors ring */
  2366. p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
  2367. D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
  2368. /* Set Tx desc pointer in driver struct. */
  2369. CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
  2370. USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
  2371. /* Init Tx ring base and size parameters */
  2372. p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
  2373. (ETH_TX_DESC *) tx_desc_base_addr;
  2374. p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
  2375. (tx_desc_num * TX_DESC_ALIGNED_SIZE);
  2376. /* Add the queue to the list of Tx queues of this port */
  2377. p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
  2378. return true;
  2379. }
  2380. /*******************************************************************************
  2381. * eth_port_send - Send an Ethernet packet
  2382. *
  2383. * DESCRIPTION:
  2384. * This routine send a given packet described by p_pktinfo parameter. It
  2385. * supports transmitting of a packet spaned over multiple buffers. The
  2386. * routine updates 'curr' and 'first' indexes according to the packet
  2387. * segment passed to the routine. In case the packet segment is first,
  2388. * the 'first' index is update. In any case, the 'curr' index is updated.
  2389. * If the routine get into Tx resource error it assigns 'curr' index as
  2390. * 'first'. This way the function can abort Tx process of multiple
  2391. * descriptors per packet.
  2392. *
  2393. * INPUT:
  2394. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2395. * ETH_QUEUE tx_queue Number of Tx queue.
  2396. * PKT_INFO *p_pkt_info User packet buffer.
  2397. *
  2398. * OUTPUT:
  2399. * Tx ring 'curr' and 'first' indexes are updated.
  2400. *
  2401. * RETURN:
  2402. * ETH_QUEUE_FULL in case of Tx resource error.
  2403. * ETH_ERROR in case the routine can not access Tx desc ring.
  2404. * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
  2405. * ETH_OK otherwise.
  2406. *
  2407. *******************************************************************************/
  2408. static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
  2409. ETH_QUEUE tx_queue,
  2410. PKT_INFO * p_pkt_info)
  2411. {
  2412. volatile ETH_TX_DESC *p_tx_desc_first;
  2413. volatile ETH_TX_DESC *p_tx_desc_curr;
  2414. volatile ETH_TX_DESC *p_tx_next_desc_curr;
  2415. volatile ETH_TX_DESC *p_tx_desc_used;
  2416. unsigned int command_status;
  2417. /* Do not process Tx ring in case of Tx ring resource error */
  2418. if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
  2419. return ETH_QUEUE_FULL;
  2420. /* Get the Tx Desc ring indexes */
  2421. CURR_TFD_GET (p_tx_desc_curr, tx_queue);
  2422. USED_TFD_GET (p_tx_desc_used, tx_queue);
  2423. if (p_tx_desc_curr == NULL)
  2424. return ETH_ERROR;
  2425. /* The following parameters are used to save readings from memory */
  2426. p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
  2427. command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
  2428. if (command_status & (ETH_TX_FIRST_DESC)) {
  2429. /* Update first desc */
  2430. FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
  2431. p_tx_desc_first = p_tx_desc_curr;
  2432. } else {
  2433. FIRST_TFD_GET (p_tx_desc_first, tx_queue);
  2434. command_status |= ETH_BUFFER_OWNED_BY_DMA;
  2435. }
  2436. /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
  2437. /* boundary. We use the memory allocated for Tx descriptor. This memory */
  2438. /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
  2439. if (p_pkt_info->byte_cnt <= 8) {
  2440. printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
  2441. return ETH_ERROR;
  2442. p_tx_desc_curr->buf_ptr =
  2443. (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
  2444. eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
  2445. p_pkt_info->byte_cnt);
  2446. } else
  2447. p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
  2448. p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
  2449. p_tx_desc_curr->return_info = p_pkt_info->return_info;
  2450. if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
  2451. /* Set last desc with DMA ownership and interrupt enable. */
  2452. p_tx_desc_curr->cmd_sts = command_status |
  2453. ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
  2454. if (p_tx_desc_curr != p_tx_desc_first)
  2455. p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
  2456. /* Flush CPU pipe */
  2457. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
  2458. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
  2459. CPU_PIPE_FLUSH;
  2460. /* Apply send command */
  2461. ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
  2462. /* Finish Tx packet. Update first desc in case of Tx resource error */
  2463. p_tx_desc_first = p_tx_next_desc_curr;
  2464. FIRST_TFD_SET (p_tx_desc_first, tx_queue);
  2465. } else {
  2466. p_tx_desc_curr->cmd_sts = command_status;
  2467. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
  2468. }
  2469. /* Check for ring index overlap in the Tx desc ring */
  2470. if (p_tx_next_desc_curr == p_tx_desc_used) {
  2471. /* Update the current descriptor */
  2472. CURR_TFD_SET (p_tx_desc_first, tx_queue);
  2473. p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
  2474. return ETH_QUEUE_LAST_RESOURCE;
  2475. } else {
  2476. /* Update the current descriptor */
  2477. CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
  2478. return ETH_OK;
  2479. }
  2480. }
  2481. /*******************************************************************************
  2482. * eth_tx_return_desc - Free all used Tx descriptors
  2483. *
  2484. * DESCRIPTION:
  2485. * This routine returns the transmitted packet information to the caller.
  2486. * It uses the 'first' index to support Tx desc return in case a transmit
  2487. * of a packet spanned over multiple buffer still in process.
  2488. * In case the Tx queue was in "resource error" condition, where there are
  2489. * no available Tx resources, the function resets the resource error flag.
  2490. *
  2491. * INPUT:
  2492. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2493. * ETH_QUEUE tx_queue Number of Tx queue.
  2494. * PKT_INFO *p_pkt_info User packet buffer.
  2495. *
  2496. * OUTPUT:
  2497. * Tx ring 'first' and 'used' indexes are updated.
  2498. *
  2499. * RETURN:
  2500. * ETH_ERROR in case the routine can not access Tx desc ring.
  2501. * ETH_RETRY in case there is transmission in process.
  2502. * ETH_END_OF_JOB if the routine has nothing to release.
  2503. * ETH_OK otherwise.
  2504. *
  2505. *******************************************************************************/
  2506. static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
  2507. p_eth_port_ctrl,
  2508. ETH_QUEUE tx_queue,
  2509. PKT_INFO * p_pkt_info)
  2510. {
  2511. volatile ETH_TX_DESC *p_tx_desc_used = NULL;
  2512. volatile ETH_TX_DESC *p_tx_desc_first = NULL;
  2513. unsigned int command_status;
  2514. /* Get the Tx Desc ring indexes */
  2515. USED_TFD_GET (p_tx_desc_used, tx_queue);
  2516. FIRST_TFD_GET (p_tx_desc_first, tx_queue);
  2517. /* Sanity check */
  2518. if (p_tx_desc_used == NULL)
  2519. return ETH_ERROR;
  2520. command_status = p_tx_desc_used->cmd_sts;
  2521. /* Still transmitting... */
  2522. if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
  2523. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
  2524. return ETH_RETRY;
  2525. }
  2526. /* Stop release. About to overlap the current available Tx descriptor */
  2527. if ((p_tx_desc_used == p_tx_desc_first) &&
  2528. (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
  2529. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
  2530. return ETH_END_OF_JOB;
  2531. }
  2532. /* Pass the packet information to the caller */
  2533. p_pkt_info->cmd_sts = command_status;
  2534. p_pkt_info->return_info = p_tx_desc_used->return_info;
  2535. p_tx_desc_used->return_info = 0;
  2536. /* Update the next descriptor to release. */
  2537. USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
  2538. /* Any Tx return cancels the Tx resource error status */
  2539. if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
  2540. p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
  2541. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
  2542. return ETH_OK;
  2543. }
  2544. /*******************************************************************************
  2545. * eth_port_receive - Get received information from Rx ring.
  2546. *
  2547. * DESCRIPTION:
  2548. * This routine returns the received data to the caller. There is no
  2549. * data copying during routine operation. All information is returned
  2550. * using pointer to packet information struct passed from the caller.
  2551. * If the routine exhausts Rx ring resources then the resource error flag
  2552. * is set.
  2553. *
  2554. * INPUT:
  2555. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2556. * ETH_QUEUE rx_queue Number of Rx queue.
  2557. * PKT_INFO *p_pkt_info User packet buffer.
  2558. *
  2559. * OUTPUT:
  2560. * Rx ring current and used indexes are updated.
  2561. *
  2562. * RETURN:
  2563. * ETH_ERROR in case the routine can not access Rx desc ring.
  2564. * ETH_QUEUE_FULL if Rx ring resources are exhausted.
  2565. * ETH_END_OF_JOB if there is no received data.
  2566. * ETH_OK otherwise.
  2567. *
  2568. *******************************************************************************/
  2569. static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
  2570. ETH_QUEUE rx_queue,
  2571. PKT_INFO * p_pkt_info)
  2572. {
  2573. volatile ETH_RX_DESC *p_rx_curr_desc;
  2574. volatile ETH_RX_DESC *p_rx_next_curr_desc;
  2575. volatile ETH_RX_DESC *p_rx_used_desc;
  2576. unsigned int command_status;
  2577. /* Do not process Rx ring in case of Rx ring resource error */
  2578. if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
  2579. printf ("\nRx Queue is full ...\n");
  2580. return ETH_QUEUE_FULL;
  2581. }
  2582. /* Get the Rx Desc ring 'curr and 'used' indexes */
  2583. CURR_RFD_GET (p_rx_curr_desc, rx_queue);
  2584. USED_RFD_GET (p_rx_used_desc, rx_queue);
  2585. /* Sanity check */
  2586. if (p_rx_curr_desc == NULL)
  2587. return ETH_ERROR;
  2588. /* The following parameters are used to save readings from memory */
  2589. p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
  2590. command_status = p_rx_curr_desc->cmd_sts;
  2591. /* Nothing to receive... */
  2592. if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
  2593. /* DP(printf("Rx: command_status: %08x\n", command_status)); */
  2594. D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
  2595. /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
  2596. return ETH_END_OF_JOB;
  2597. }
  2598. p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
  2599. p_pkt_info->cmd_sts = command_status;
  2600. p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
  2601. p_pkt_info->return_info = p_rx_curr_desc->return_info;
  2602. p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
  2603. /* Clean the return info field to indicate that the packet has been */
  2604. /* moved to the upper layers */
  2605. p_rx_curr_desc->return_info = 0;
  2606. /* Update 'curr' in data structure */
  2607. CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
  2608. /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
  2609. if (p_rx_next_curr_desc == p_rx_used_desc)
  2610. p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
  2611. D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
  2612. CPU_PIPE_FLUSH;
  2613. return ETH_OK;
  2614. }
  2615. /*******************************************************************************
  2616. * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
  2617. *
  2618. * DESCRIPTION:
  2619. * This routine returns a Rx buffer back to the Rx ring. It retrieves the
  2620. * next 'used' descriptor and attached the returned buffer to it.
  2621. * In case the Rx ring was in "resource error" condition, where there are
  2622. * no available Rx resources, the function resets the resource error flag.
  2623. *
  2624. * INPUT:
  2625. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2626. * ETH_QUEUE rx_queue Number of Rx queue.
  2627. * PKT_INFO *p_pkt_info Information on the returned buffer.
  2628. *
  2629. * OUTPUT:
  2630. * New available Rx resource in Rx descriptor ring.
  2631. *
  2632. * RETURN:
  2633. * ETH_ERROR in case the routine can not access Rx desc ring.
  2634. * ETH_OK otherwise.
  2635. *
  2636. *******************************************************************************/
  2637. static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
  2638. p_eth_port_ctrl,
  2639. ETH_QUEUE rx_queue,
  2640. PKT_INFO * p_pkt_info)
  2641. {
  2642. volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
  2643. /* Get 'used' Rx descriptor */
  2644. USED_RFD_GET (p_used_rx_desc, rx_queue);
  2645. /* Sanity check */
  2646. if (p_used_rx_desc == NULL)
  2647. return ETH_ERROR;
  2648. p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
  2649. p_used_rx_desc->return_info = p_pkt_info->return_info;
  2650. p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
  2651. p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */
  2652. /* Flush the write pipe */
  2653. CPU_PIPE_FLUSH;
  2654. /* Return the descriptor to DMA ownership */
  2655. p_used_rx_desc->cmd_sts =
  2656. ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
  2657. /* Flush descriptor and CPU pipe */
  2658. D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
  2659. CPU_PIPE_FLUSH;
  2660. /* Move the used descriptor pointer to the next descriptor */
  2661. USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
  2662. /* Any Rx return cancels the Rx resource error status */
  2663. if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
  2664. p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
  2665. return ETH_OK;
  2666. }
  2667. /*******************************************************************************
  2668. * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
  2669. *
  2670. * DESCRIPTION:
  2671. * This routine sets the RX coalescing interrupt mechanism parameter.
  2672. * This parameter is a timeout counter, that counts in 64 t_clk
  2673. * chunks ; that when timeout event occurs a maskable interrupt
  2674. * occurs.
  2675. * The parameter is calculated using the tClk of the MV-643xx chip
  2676. * , and the required delay of the interrupt in usec.
  2677. *
  2678. * INPUT:
  2679. * ETH_PORT eth_port_num Ethernet port number
  2680. * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
  2681. * unsigned int delay Delay in usec
  2682. *
  2683. * OUTPUT:
  2684. * Interrupt coalescing mechanism value is set in MV-643xx chip.
  2685. *
  2686. * RETURN:
  2687. * The interrupt coalescing value set in the gigE port.
  2688. *
  2689. *******************************************************************************/
  2690. #if 0 /* FIXME */
  2691. static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
  2692. unsigned int t_clk,
  2693. unsigned int delay)
  2694. {
  2695. unsigned int coal;
  2696. coal = ((t_clk / 1000000) * delay) / 64;
  2697. /* Set RX Coalescing mechanism */
  2698. MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
  2699. ((coal & 0x3fff) << 8) |
  2700. (MV_REG_READ
  2701. (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
  2702. & 0xffc000ff));
  2703. return coal;
  2704. }
  2705. #endif
  2706. /*******************************************************************************
  2707. * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
  2708. *
  2709. * DESCRIPTION:
  2710. * This routine sets the TX coalescing interrupt mechanism parameter.
  2711. * This parameter is a timeout counter, that counts in 64 t_clk
  2712. * chunks ; that when timeout event occurs a maskable interrupt
  2713. * occurs.
  2714. * The parameter is calculated using the t_cLK frequency of the
  2715. * MV-643xx chip and the required delay in the interrupt in uSec
  2716. *
  2717. * INPUT:
  2718. * ETH_PORT eth_port_num Ethernet port number
  2719. * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
  2720. * unsigned int delay Delay in uSeconds
  2721. *
  2722. * OUTPUT:
  2723. * Interrupt coalescing mechanism value is set in MV-643xx chip.
  2724. *
  2725. * RETURN:
  2726. * The interrupt coalescing value set in the gigE port.
  2727. *
  2728. *******************************************************************************/
  2729. #if 0 /* FIXME */
  2730. static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
  2731. unsigned int t_clk,
  2732. unsigned int delay)
  2733. {
  2734. unsigned int coal;
  2735. coal = ((t_clk / 1000000) * delay) / 64;
  2736. /* Set TX Coalescing mechanism */
  2737. MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
  2738. coal << 4);
  2739. return coal;
  2740. }
  2741. #endif
  2742. /*******************************************************************************
  2743. * eth_b_copy - Copy bytes from source to destination
  2744. *
  2745. * DESCRIPTION:
  2746. * This function supports the eight bytes limitation on Tx buffer size.
  2747. * The routine will zero eight bytes starting from the destination address
  2748. * followed by copying bytes from the source address to the destination.
  2749. *
  2750. * INPUT:
  2751. * unsigned int src_addr 32 bit source address.
  2752. * unsigned int dst_addr 32 bit destination address.
  2753. * int byte_count Number of bytes to copy.
  2754. *
  2755. * OUTPUT:
  2756. * See description.
  2757. *
  2758. * RETURN:
  2759. * None.
  2760. *
  2761. *******************************************************************************/
  2762. static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
  2763. int byte_count)
  2764. {
  2765. /* Zero the dst_addr area */
  2766. *(unsigned int *) dst_addr = 0x0;
  2767. while (byte_count != 0) {
  2768. *(char *) dst_addr = *(char *) src_addr;
  2769. dst_addr++;
  2770. src_addr++;
  2771. byte_count--;
  2772. }
  2773. }