ae350.dts 4.8 KB

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  1. /dts-v1/;
  2. / {
  3. #address-cells = <2>;
  4. #size-cells = <2>;
  5. compatible = "andestech,ax25";
  6. model = "andestech,ax25";
  7. aliases {
  8. uart0 = &serial0;
  9. spi0 = &spi;
  10. };
  11. chosen {
  12. bootargs = "console=ttyS0,38400n8 debug loglevel=7";
  13. stdout-path = "uart0:38400n8";
  14. };
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. timebase-frequency = <60000000>;
  19. CPU0: cpu@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. status = "okay";
  23. compatible = "riscv";
  24. riscv,isa = "rv64imafdc";
  25. mmu-type = "riscv,sv39";
  26. clock-frequency = <60000000>;
  27. d-cache-size = <0x8000>;
  28. d-cache-line-size = <32>;
  29. CPU0_intc: interrupt-controller {
  30. #interrupt-cells = <1>;
  31. interrupt-controller;
  32. compatible = "riscv,cpu-intc";
  33. };
  34. };
  35. };
  36. memory@0 {
  37. device_type = "memory";
  38. reg = <0x0 0x00000000 0x0 0x40000000>;
  39. };
  40. soc {
  41. #address-cells = <2>;
  42. #size-cells = <2>;
  43. compatible = "andestech,riscv-ae350-soc";
  44. ranges;
  45. plic0: interrupt-controller@e4000000 {
  46. compatible = "riscv,plic0";
  47. #address-cells = <2>;
  48. #interrupt-cells = <2>;
  49. interrupt-controller;
  50. reg = <0x0 0xe4000000 0x0 0x2000000>;
  51. riscv,ndev=<71>;
  52. interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
  53. };
  54. plic1: interrupt-controller@e6400000 {
  55. compatible = "riscv,plic1";
  56. #address-cells = <2>;
  57. #interrupt-cells = <2>;
  58. interrupt-controller;
  59. reg = <0x0 0xe6400000 0x0 0x400000>;
  60. riscv,ndev=<1>;
  61. interrupts-extended = <&CPU0_intc 3>;
  62. };
  63. plmt0@e6000000 {
  64. compatible = "riscv,plmt0";
  65. interrupts-extended = <&CPU0_intc 7>;
  66. reg = <0x0 0xe6000000 0x0 0x100000>;
  67. };
  68. };
  69. spiclk: virt_100mhz {
  70. #clock-cells = <0>;
  71. compatible = "fixed-clock";
  72. clock-frequency = <100000000>;
  73. };
  74. timer0: timer@f0400000 {
  75. compatible = "andestech,atcpit100";
  76. reg = <0x0 0xf0400000 0x0 0x1000>;
  77. clock-frequency = <60000000>;
  78. interrupts = <3 4>;
  79. interrupt-parent = <&plic0>;
  80. };
  81. serial0: serial@f0300000 {
  82. compatible = "andestech,uart16550", "ns16550a";
  83. reg = <0x0 0xf0300000 0x0 0x1000>;
  84. interrupts = <9 4>;
  85. clock-frequency = <19660800>;
  86. reg-shift = <2>;
  87. reg-offset = <32>;
  88. no-loopback-test = <1>;
  89. interrupt-parent = <&plic0>;
  90. };
  91. mac0: mac@e0100000 {
  92. compatible = "andestech,atmac100";
  93. reg = <0x0 0xe0100000 0x0 0x1000>;
  94. interrupts = <19 4>;
  95. interrupt-parent = <&plic0>;
  96. };
  97. mmc0: mmc@f0e00000 {
  98. compatible = "andestech,atfsdc010";
  99. max-frequency = <100000000>;
  100. clock-freq-min-max = <400000 100000000>;
  101. fifo-depth = <0x10>;
  102. reg = <0x0 0xf0e00000 0x0 0x1000>;
  103. interrupts = <18 4>;
  104. cap-sd-highspeed;
  105. interrupt-parent = <&plic0>;
  106. };
  107. dma0: dma@f0c00000 {
  108. compatible = "andestech,atcdmac300";
  109. reg = <0x0 0xf0c00000 0x0 0x1000>;
  110. interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
  111. dma-channels = <8>;
  112. interrupt-parent = <&plic0>;
  113. };
  114. lcd0: lcd@e0200000 {
  115. compatible = "andestech,atflcdc100";
  116. reg = <0x0 0xe0200000 0x0 0x1000>;
  117. interrupts = <20 4>;
  118. interrupt-parent = <&plic0>;
  119. };
  120. smc0: smc@e0400000 {
  121. compatible = "andestech,atfsmc020";
  122. reg = <0x0 0xe0400000 0x0 0x1000>;
  123. };
  124. snd0: snd@f0d00000 {
  125. compatible = "andestech,atfac97";
  126. reg = <0x0 0xf0d00000 0x0 0x1000>;
  127. interrupts = <17 4>;
  128. interrupt-parent = <&plic0>;
  129. };
  130. virtio_mmio@fe007000 {
  131. interrupts = <0x17 0x4>;
  132. interrupt-parent = <0x2>;
  133. reg = <0x0 0xfe007000 0x0 0x1000>;
  134. compatible = "virtio,mmio";
  135. };
  136. virtio_mmio@fe006000 {
  137. interrupts = <0x16 0x4>;
  138. interrupt-parent = <0x2>;
  139. reg = <0x0 0xfe006000 0x0 0x1000>;
  140. compatible = "virtio,mmio";
  141. };
  142. virtio_mmio@fe005000 {
  143. interrupts = <0x15 0x4>;
  144. interrupt-parent = <0x2>;
  145. reg = <0x0 0xfe005000 0x0 0x1000>;
  146. compatible = "virtio,mmio";
  147. };
  148. virtio_mmio@fe004000 {
  149. interrupts = <0x14 0x4>;
  150. interrupt-parent = <0x2>;
  151. reg = <0x0 0xfe004000 0x0 0x1000>;
  152. compatible = "virtio,mmio";
  153. };
  154. virtio_mmio@fe003000 {
  155. interrupts = <0x13 0x4>;
  156. interrupt-parent = <0x2>;
  157. reg = <0x0 0xfe003000 0x0 0x1000>;
  158. compatible = "virtio,mmio";
  159. };
  160. virtio_mmio@fe002000 {
  161. interrupts = <0x12 0x4>;
  162. interrupt-parent = <0x2>;
  163. reg = <0x0 0xfe002000 0x0 0x1000>;
  164. compatible = "virtio,mmio";
  165. };
  166. virtio_mmio@fe001000 {
  167. interrupts = <0x11 0x4>;
  168. interrupt-parent = <0x2>;
  169. reg = <0x0 0xfe001000 0x0 0x1000>;
  170. compatible = "virtio,mmio";
  171. };
  172. virtio_mmio@fe000000 {
  173. interrupts = <0x10 0x4>;
  174. interrupt-parent = <0x2>;
  175. reg = <0x0 0xfe000000 0x0 0x1000>;
  176. compatible = "virtio,mmio";
  177. };
  178. nor@0,0 {
  179. compatible = "cfi-flash";
  180. reg = <0x0 0x88000000 0x0 0x1000>;
  181. bank-width = <2>;
  182. device-width = <1>;
  183. };
  184. spi: spi@f0b00000 {
  185. compatible = "andestech,atcspi200";
  186. reg = <0x0 0xf0b00000 0x0 0x1000>;
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. num-cs = <1>;
  190. clocks = <&spiclk>;
  191. interrupts = <4 4>;
  192. interrupt-parent = <&plic0>;
  193. flash@0 {
  194. compatible = "spi-flash";
  195. spi-max-frequency = <50000000>;
  196. reg = <0>;
  197. spi-cpol;
  198. spi-cpha;
  199. };
  200. };
  201. };