cache.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Andes Technology Corporation
  4. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  5. */
  6. #include <common.h>
  7. void icache_enable(void)
  8. {
  9. #ifndef CONFIG_SYS_ICACHE_OFF
  10. #ifdef CONFIG_RISCV_NDS
  11. asm volatile (
  12. "csrr t1, mcache_ctl\n\t"
  13. "ori t0, t1, 0x1\n\t"
  14. "csrw mcache_ctl, t0\n\t"
  15. );
  16. #endif
  17. #endif
  18. }
  19. void icache_disable(void)
  20. {
  21. #ifndef CONFIG_SYS_ICACHE_OFF
  22. #ifdef CONFIG_RISCV_NDS
  23. asm volatile (
  24. "fence.i\n\t"
  25. "csrr t1, mcache_ctl\n\t"
  26. "andi t0, t1, ~0x1\n\t"
  27. "csrw mcache_ctl, t0\n\t"
  28. );
  29. #endif
  30. #endif
  31. }
  32. void dcache_enable(void)
  33. {
  34. #ifndef CONFIG_SYS_DCACHE_OFF
  35. #ifdef CONFIG_RISCV_NDS
  36. asm volatile (
  37. "csrr t1, mcache_ctl\n\t"
  38. "ori t0, t1, 0x2\n\t"
  39. "csrw mcache_ctl, t0\n\t"
  40. );
  41. #endif
  42. #endif
  43. }
  44. void dcache_disable(void)
  45. {
  46. #ifndef CONFIG_SYS_DCACHE_OFF
  47. #ifdef CONFIG_RISCV_NDS
  48. asm volatile (
  49. "fence\n\t"
  50. "csrr t1, mcache_ctl\n\t"
  51. "andi t0, t1, ~0x2\n\t"
  52. "csrw mcache_ctl, t0\n\t"
  53. );
  54. #endif
  55. #endif
  56. }
  57. int icache_status(void)
  58. {
  59. int ret = 0;
  60. #ifdef CONFIG_RISCV_NDS
  61. asm volatile (
  62. "csrr t1, mcache_ctl\n\t"
  63. "andi %0, t1, 0x01\n\t"
  64. : "=r" (ret)
  65. :
  66. : "memory"
  67. );
  68. #endif
  69. return ret;
  70. }
  71. int dcache_status(void)
  72. {
  73. int ret = 0;
  74. #ifdef CONFIG_RISCV_NDS
  75. asm volatile (
  76. "csrr t1, mcache_ctl\n\t"
  77. "andi %0, t1, 0x02\n\t"
  78. : "=r" (ret)
  79. :
  80. : "memory"
  81. );
  82. #endif
  83. return ret;
  84. }