ti_qspi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI QSPI driver
  4. *
  5. * Copyright (C) 2013, Texas Instruments, Incorporated
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/omap.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <spi-mem.h>
  14. #include <dm.h>
  15. #include <asm/gpio.h>
  16. #include <asm/omap_gpio.h>
  17. #include <asm/omap_common.h>
  18. #include <asm/ti-common/ti-edma3.h>
  19. #include <linux/kernel.h>
  20. #include <regmap.h>
  21. #include <syscon.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. /* ti qpsi register bit masks */
  24. #define QSPI_TIMEOUT 2000000
  25. #define QSPI_FCLK 192000000
  26. #define QSPI_DRA7XX_FCLK 76800000
  27. #define QSPI_WLEN_MAX_BITS 128
  28. #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
  29. #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  30. /* clock control */
  31. #define QSPI_CLK_EN BIT(31)
  32. #define QSPI_CLK_DIV_MAX 0xffff
  33. /* command */
  34. #define QSPI_EN_CS(n) (n << 28)
  35. #define QSPI_WLEN(n) ((n-1) << 19)
  36. #define QSPI_3_PIN BIT(18)
  37. #define QSPI_RD_SNGL BIT(16)
  38. #define QSPI_WR_SNGL (2 << 16)
  39. #define QSPI_INVAL (4 << 16)
  40. #define QSPI_RD_QUAD (7 << 16)
  41. /* device control */
  42. #define QSPI_CKPHA(n) (1 << (2 + n*8))
  43. #define QSPI_CSPOL(n) (1 << (1 + n*8))
  44. #define QSPI_CKPOL(n) (1 << (n*8))
  45. /* status */
  46. #define QSPI_WC BIT(1)
  47. #define QSPI_BUSY BIT(0)
  48. #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
  49. #define QSPI_XFER_DONE QSPI_WC
  50. #define MM_SWITCH 0x01
  51. #define MEM_CS(cs) ((cs + 1) << 8)
  52. #define MEM_CS_UNSELECT 0xfffff8ff
  53. #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
  54. #define QSPI_SETUP0_READ_DUAL (0x1 << 12)
  55. #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
  56. #define QSPI_SETUP0_ADDR_SHIFT (8)
  57. #define QSPI_SETUP0_DBITS_SHIFT (10)
  58. /* ti qspi register set */
  59. struct ti_qspi_regs {
  60. u32 pid;
  61. u32 pad0[3];
  62. u32 sysconfig;
  63. u32 pad1[3];
  64. u32 int_stat_raw;
  65. u32 int_stat_en;
  66. u32 int_en_set;
  67. u32 int_en_ctlr;
  68. u32 intc_eoi;
  69. u32 pad2[3];
  70. u32 clk_ctrl;
  71. u32 dc;
  72. u32 cmd;
  73. u32 status;
  74. u32 data;
  75. u32 setup0;
  76. u32 setup1;
  77. u32 setup2;
  78. u32 setup3;
  79. u32 memswitch;
  80. u32 data1;
  81. u32 data2;
  82. u32 data3;
  83. };
  84. /* ti qspi priv */
  85. struct ti_qspi_priv {
  86. void *memory_map;
  87. size_t mmap_size;
  88. uint max_hz;
  89. u32 num_cs;
  90. struct ti_qspi_regs *base;
  91. void *ctrl_mod_mmap;
  92. ulong fclk;
  93. unsigned int mode;
  94. u32 cmd;
  95. u32 dc;
  96. };
  97. static int ti_qspi_set_speed(struct udevice *bus, uint hz)
  98. {
  99. struct ti_qspi_priv *priv = dev_get_priv(bus);
  100. uint clk_div;
  101. if (!hz)
  102. clk_div = 0;
  103. else
  104. clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
  105. /* truncate clk_div value to QSPI_CLK_DIV_MAX */
  106. if (clk_div > QSPI_CLK_DIV_MAX)
  107. clk_div = QSPI_CLK_DIV_MAX;
  108. debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
  109. /* disable SCLK */
  110. writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
  111. &priv->base->clk_ctrl);
  112. /* enable SCLK and program the clk divider */
  113. writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
  114. return 0;
  115. }
  116. static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
  117. {
  118. writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
  119. /* dummy readl to ensure bus sync */
  120. readl(&priv->base->cmd);
  121. }
  122. static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
  123. {
  124. u32 val;
  125. val = readl(ctrl_mod_mmap);
  126. if (enable)
  127. val |= MEM_CS(cs);
  128. else
  129. val &= MEM_CS_UNSELECT;
  130. writel(val, ctrl_mod_mmap);
  131. }
  132. static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  133. const void *dout, void *din, unsigned long flags)
  134. {
  135. struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
  136. struct ti_qspi_priv *priv;
  137. struct udevice *bus;
  138. uint words = bitlen >> 3; /* fixed 8-bit word length */
  139. const uchar *txp = dout;
  140. uchar *rxp = din;
  141. uint status;
  142. int timeout;
  143. unsigned int cs = slave->cs;
  144. bus = dev->parent;
  145. priv = dev_get_priv(bus);
  146. if (cs > priv->num_cs) {
  147. debug("invalid qspi chip select\n");
  148. return -EINVAL;
  149. }
  150. if (bitlen == 0)
  151. return -1;
  152. if (bitlen % 8) {
  153. debug("spi_xfer: Non byte aligned SPI transfer\n");
  154. return -1;
  155. }
  156. /* Setup command reg */
  157. priv->cmd = 0;
  158. priv->cmd |= QSPI_WLEN(8);
  159. priv->cmd |= QSPI_EN_CS(cs);
  160. if (priv->mode & SPI_3WIRE)
  161. priv->cmd |= QSPI_3_PIN;
  162. priv->cmd |= 0xfff;
  163. while (words) {
  164. u8 xfer_len = 0;
  165. if (txp) {
  166. u32 cmd = priv->cmd;
  167. if (words >= QSPI_WLEN_MAX_BYTES) {
  168. u32 *txbuf = (u32 *)txp;
  169. u32 data;
  170. data = cpu_to_be32(*txbuf++);
  171. writel(data, &priv->base->data3);
  172. data = cpu_to_be32(*txbuf++);
  173. writel(data, &priv->base->data2);
  174. data = cpu_to_be32(*txbuf++);
  175. writel(data, &priv->base->data1);
  176. data = cpu_to_be32(*txbuf++);
  177. writel(data, &priv->base->data);
  178. cmd &= ~QSPI_WLEN_MASK;
  179. cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
  180. xfer_len = QSPI_WLEN_MAX_BYTES;
  181. } else {
  182. writeb(*txp, &priv->base->data);
  183. xfer_len = 1;
  184. }
  185. debug("tx cmd %08x dc %08x\n",
  186. cmd | QSPI_WR_SNGL, priv->dc);
  187. writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
  188. status = readl(&priv->base->status);
  189. timeout = QSPI_TIMEOUT;
  190. while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
  191. if (--timeout < 0) {
  192. printf("spi_xfer: TX timeout!\n");
  193. return -1;
  194. }
  195. status = readl(&priv->base->status);
  196. }
  197. txp += xfer_len;
  198. debug("tx done, status %08x\n", status);
  199. }
  200. if (rxp) {
  201. debug("rx cmd %08x dc %08x\n",
  202. ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
  203. writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
  204. status = readl(&priv->base->status);
  205. timeout = QSPI_TIMEOUT;
  206. while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
  207. if (--timeout < 0) {
  208. printf("spi_xfer: RX timeout!\n");
  209. return -1;
  210. }
  211. status = readl(&priv->base->status);
  212. }
  213. *rxp++ = readl(&priv->base->data);
  214. xfer_len = 1;
  215. debug("rx done, status %08x, read %02x\n",
  216. status, *(rxp-1));
  217. }
  218. words -= xfer_len;
  219. }
  220. /* Terminate frame */
  221. if (flags & SPI_XFER_END)
  222. ti_qspi_cs_deactivate(priv);
  223. return 0;
  224. }
  225. /* TODO: control from sf layer to here through dm-spi */
  226. static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
  227. {
  228. #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
  229. unsigned int addr = (unsigned int) (data);
  230. unsigned int edma_slot_num = 1;
  231. /* Invalidate the area, so no writeback into the RAM races with DMA */
  232. invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
  233. /* enable edma3 clocks */
  234. enable_edma3_clocks();
  235. /* Call edma3 api to do actual DMA transfer */
  236. edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
  237. /* disable edma3 clocks */
  238. disable_edma3_clocks();
  239. #else
  240. memcpy_fromio(data, offset, len);
  241. #endif
  242. *((unsigned int *)offset) += len;
  243. }
  244. static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
  245. u8 data_nbits, u8 addr_width,
  246. u8 dummy_bytes)
  247. {
  248. u32 memval = opcode;
  249. switch (data_nbits) {
  250. case 4:
  251. memval |= QSPI_SETUP0_READ_QUAD;
  252. break;
  253. case 2:
  254. memval |= QSPI_SETUP0_READ_DUAL;
  255. break;
  256. default:
  257. memval |= QSPI_SETUP0_READ_NORMAL;
  258. break;
  259. }
  260. memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
  261. dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
  262. writel(memval, &priv->base->setup0);
  263. }
  264. static int ti_qspi_set_mode(struct udevice *bus, uint mode)
  265. {
  266. struct ti_qspi_priv *priv = dev_get_priv(bus);
  267. priv->dc = 0;
  268. if (mode & SPI_CPHA)
  269. priv->dc |= QSPI_CKPHA(0);
  270. if (mode & SPI_CPOL)
  271. priv->dc |= QSPI_CKPOL(0);
  272. if (mode & SPI_CS_HIGH)
  273. priv->dc |= QSPI_CSPOL(0);
  274. return 0;
  275. }
  276. static int ti_qspi_exec_mem_op(struct spi_slave *slave,
  277. const struct spi_mem_op *op)
  278. {
  279. struct ti_qspi_priv *priv;
  280. struct udevice *bus;
  281. bus = slave->dev->parent;
  282. priv = dev_get_priv(bus);
  283. u32 from = 0;
  284. int ret = 0;
  285. /* Only optimize read path. */
  286. if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
  287. !op->addr.nbytes || op->addr.nbytes > 4)
  288. return -ENOTSUPP;
  289. /* Address exceeds MMIO window size, fall back to regular mode. */
  290. from = op->addr.val;
  291. if (from + op->data.nbytes > priv->mmap_size)
  292. return -ENOTSUPP;
  293. ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth,
  294. op->addr.nbytes, op->dummy.nbytes);
  295. ti_qspi_copy_mmap((void *)op->data.buf.in,
  296. (void *)priv->memory_map + from, op->data.nbytes);
  297. return ret;
  298. }
  299. static int ti_qspi_claim_bus(struct udevice *dev)
  300. {
  301. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  302. struct ti_qspi_priv *priv;
  303. struct udevice *bus;
  304. bus = dev->parent;
  305. priv = dev_get_priv(bus);
  306. if (slave_plat->cs > priv->num_cs) {
  307. debug("invalid qspi chip select\n");
  308. return -EINVAL;
  309. }
  310. writel(MM_SWITCH, &priv->base->memswitch);
  311. if (priv->ctrl_mod_mmap)
  312. ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
  313. slave_plat->cs, true);
  314. writel(priv->dc, &priv->base->dc);
  315. writel(0, &priv->base->cmd);
  316. writel(0, &priv->base->data);
  317. priv->dc <<= slave_plat->cs * 8;
  318. writel(priv->dc, &priv->base->dc);
  319. return 0;
  320. }
  321. static int ti_qspi_release_bus(struct udevice *dev)
  322. {
  323. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  324. struct ti_qspi_priv *priv;
  325. struct udevice *bus;
  326. bus = dev->parent;
  327. priv = dev_get_priv(bus);
  328. writel(~MM_SWITCH, &priv->base->memswitch);
  329. if (priv->ctrl_mod_mmap)
  330. ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
  331. slave_plat->cs, false);
  332. writel(0, &priv->base->dc);
  333. writel(0, &priv->base->cmd);
  334. writel(0, &priv->base->data);
  335. writel(0, &priv->base->setup0);
  336. return 0;
  337. }
  338. static int ti_qspi_probe(struct udevice *bus)
  339. {
  340. struct ti_qspi_priv *priv = dev_get_priv(bus);
  341. priv->fclk = dev_get_driver_data(bus);
  342. return 0;
  343. }
  344. static void *map_syscon_chipselects(struct udevice *bus)
  345. {
  346. #if CONFIG_IS_ENABLED(SYSCON)
  347. struct udevice *syscon;
  348. struct regmap *regmap;
  349. const fdt32_t *cell;
  350. int len, err;
  351. err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
  352. "syscon-chipselects", &syscon);
  353. if (err) {
  354. debug("%s: unable to find syscon device (%d)\n", __func__,
  355. err);
  356. return NULL;
  357. }
  358. regmap = syscon_get_regmap(syscon);
  359. if (IS_ERR(regmap)) {
  360. debug("%s: unable to find regmap (%ld)\n", __func__,
  361. PTR_ERR(regmap));
  362. return NULL;
  363. }
  364. cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
  365. "syscon-chipselects", &len);
  366. if (len < 2*sizeof(fdt32_t)) {
  367. debug("%s: offset not available\n", __func__);
  368. return NULL;
  369. }
  370. return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
  371. #else
  372. fdt_addr_t addr;
  373. addr = devfdt_get_addr_index(bus, 2);
  374. return (addr == FDT_ADDR_T_NONE) ? NULL :
  375. map_physmem(addr, 0, MAP_NOCACHE);
  376. #endif
  377. }
  378. static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
  379. {
  380. struct ti_qspi_priv *priv = dev_get_priv(bus);
  381. const void *blob = gd->fdt_blob;
  382. int node = dev_of_offset(bus);
  383. fdt_addr_t mmap_addr;
  384. fdt_addr_t mmap_size;
  385. priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
  386. priv->base = map_physmem(devfdt_get_addr(bus),
  387. sizeof(struct ti_qspi_regs), MAP_NOCACHE);
  388. mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
  389. priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
  390. priv->mmap_size = mmap_size;
  391. priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
  392. if (priv->max_hz < 0) {
  393. debug("Error: Max frequency missing\n");
  394. return -ENODEV;
  395. }
  396. priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
  397. debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
  398. (int)priv->base, priv->max_hz);
  399. return 0;
  400. }
  401. static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
  402. .exec_op = ti_qspi_exec_mem_op,
  403. };
  404. static const struct dm_spi_ops ti_qspi_ops = {
  405. .claim_bus = ti_qspi_claim_bus,
  406. .release_bus = ti_qspi_release_bus,
  407. .xfer = ti_qspi_xfer,
  408. .set_speed = ti_qspi_set_speed,
  409. .set_mode = ti_qspi_set_mode,
  410. .mem_ops = &ti_qspi_mem_ops,
  411. };
  412. static const struct udevice_id ti_qspi_ids[] = {
  413. { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
  414. { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
  415. { }
  416. };
  417. U_BOOT_DRIVER(ti_qspi) = {
  418. .name = "ti_qspi",
  419. .id = UCLASS_SPI,
  420. .of_match = ti_qspi_ids,
  421. .ops = &ti_qspi_ops,
  422. .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
  423. .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
  424. .probe = ti_qspi_probe,
  425. };