spi-sunxi.c 15 KB

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  1. /*
  2. * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
  3. * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
  4. * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
  5. *
  6. * (C) Copyright 2017 Olimex Ltd..
  7. * Stefan Mavrodiev <stefan@olimex.com>
  8. *
  9. * Based on linux spi driver. Original copyright follows:
  10. * linux/drivers/spi/spi-sun4i.c
  11. *
  12. * Copyright (C) 2012 - 2014 Allwinner Tech
  13. * Pan Nan <pannan@allwinnertech.com>
  14. *
  15. * Copyright (C) 2014 Maxime Ripard
  16. * Maxime Ripard <maxime.ripard@free-electrons.com>
  17. *
  18. * SPDX-License-Identifier: GPL-2.0+
  19. */
  20. #include <common.h>
  21. #include <clk.h>
  22. #include <dm.h>
  23. #include <spi.h>
  24. #include <errno.h>
  25. #include <fdt_support.h>
  26. #include <reset.h>
  27. #include <wait_bit.h>
  28. #include <asm/bitops.h>
  29. #include <asm/gpio.h>
  30. #include <asm/io.h>
  31. #include <linux/iopoll.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. /* sun4i spi registers */
  34. #define SUN4I_RXDATA_REG 0x00
  35. #define SUN4I_TXDATA_REG 0x04
  36. #define SUN4I_CTL_REG 0x08
  37. #define SUN4I_CLK_CTL_REG 0x1c
  38. #define SUN4I_BURST_CNT_REG 0x20
  39. #define SUN4I_XMIT_CNT_REG 0x24
  40. #define SUN4I_FIFO_STA_REG 0x28
  41. /* sun6i spi registers */
  42. #define SUN6I_GBL_CTL_REG 0x04
  43. #define SUN6I_TFR_CTL_REG 0x08
  44. #define SUN6I_FIFO_CTL_REG 0x18
  45. #define SUN6I_FIFO_STA_REG 0x1c
  46. #define SUN6I_CLK_CTL_REG 0x24
  47. #define SUN6I_BURST_CNT_REG 0x30
  48. #define SUN6I_XMIT_CNT_REG 0x34
  49. #define SUN6I_BURST_CTL_REG 0x38
  50. #define SUN6I_TXDATA_REG 0x200
  51. #define SUN6I_RXDATA_REG 0x300
  52. /* sun spi bits */
  53. #define SUN4I_CTL_ENABLE BIT(0)
  54. #define SUN4I_CTL_MASTER BIT(1)
  55. #define SUN4I_CLK_CTL_CDR2_MASK 0xff
  56. #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
  57. #define SUN4I_CLK_CTL_CDR1_MASK 0xf
  58. #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
  59. #define SUN4I_CLK_CTL_DRS BIT(12)
  60. #define SUN4I_MAX_XFER_SIZE 0xffffff
  61. #define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
  62. #define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
  63. #define SUN4I_FIFO_STA_RF_CNT_BITS 0
  64. #define SUN4I_SPI_MAX_RATE 24000000
  65. #define SUN4I_SPI_MIN_RATE 3000
  66. #define SUN4I_SPI_DEFAULT_RATE 1000000
  67. #define SUN4I_SPI_TIMEOUT_US 1000000
  68. #define SPI_REG(priv, reg) ((priv)->base + \
  69. (priv)->variant->regs[reg])
  70. #define SPI_BIT(priv, bit) ((priv)->variant->bits[bit])
  71. #define SPI_CS(priv, cs) (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \
  72. SPI_BIT(priv, SPI_TCR_CS_MASK))
  73. /* sun spi register set */
  74. enum sun4i_spi_regs {
  75. SPI_GCR,
  76. SPI_TCR,
  77. SPI_FCR,
  78. SPI_FSR,
  79. SPI_CCR,
  80. SPI_BC,
  81. SPI_TC,
  82. SPI_BCTL,
  83. SPI_TXD,
  84. SPI_RXD,
  85. };
  86. /* sun spi register bits */
  87. enum sun4i_spi_bits {
  88. SPI_GCR_TP,
  89. SPI_GCR_SRST,
  90. SPI_TCR_CPHA,
  91. SPI_TCR_CPOL,
  92. SPI_TCR_CS_ACTIVE_LOW,
  93. SPI_TCR_CS_SEL,
  94. SPI_TCR_CS_MASK,
  95. SPI_TCR_XCH,
  96. SPI_TCR_CS_MANUAL,
  97. SPI_TCR_CS_LEVEL,
  98. SPI_FCR_TF_RST,
  99. SPI_FCR_RF_RST,
  100. SPI_FSR_RF_CNT_MASK,
  101. };
  102. struct sun4i_spi_variant {
  103. const unsigned long *regs;
  104. const u32 *bits;
  105. u32 fifo_depth;
  106. bool has_soft_reset;
  107. bool has_burst_ctl;
  108. };
  109. struct sun4i_spi_platdata {
  110. struct sun4i_spi_variant *variant;
  111. u32 base;
  112. u32 max_hz;
  113. };
  114. struct sun4i_spi_priv {
  115. struct sun4i_spi_variant *variant;
  116. struct clk clk_ahb, clk_mod;
  117. struct reset_ctl reset;
  118. u32 base;
  119. u32 freq;
  120. u32 mode;
  121. const u8 *tx_buf;
  122. u8 *rx_buf;
  123. };
  124. static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
  125. {
  126. u8 byte;
  127. while (len--) {
  128. byte = readb(SPI_REG(priv, SPI_RXD));
  129. if (priv->rx_buf)
  130. *priv->rx_buf++ = byte;
  131. }
  132. }
  133. static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
  134. {
  135. u8 byte;
  136. while (len--) {
  137. byte = priv->tx_buf ? *priv->tx_buf++ : 0;
  138. writeb(byte, SPI_REG(priv, SPI_TXD));
  139. }
  140. }
  141. static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
  142. {
  143. struct sun4i_spi_priv *priv = dev_get_priv(bus);
  144. u32 reg;
  145. reg = readl(SPI_REG(priv, SPI_TCR));
  146. reg &= ~SPI_BIT(priv, SPI_TCR_CS_MASK);
  147. reg |= SPI_CS(priv, cs);
  148. if (enable)
  149. reg &= ~SPI_BIT(priv, SPI_TCR_CS_LEVEL);
  150. else
  151. reg |= SPI_BIT(priv, SPI_TCR_CS_LEVEL);
  152. writel(reg, SPI_REG(priv, SPI_TCR));
  153. }
  154. static int sun4i_spi_parse_pins(struct udevice *dev)
  155. {
  156. const void *fdt = gd->fdt_blob;
  157. const char *pin_name;
  158. const fdt32_t *list;
  159. u32 phandle;
  160. int drive, pull = 0, pin, i;
  161. int offset;
  162. int size;
  163. list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
  164. if (!list) {
  165. printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
  166. return -EINVAL;
  167. }
  168. while (size) {
  169. phandle = fdt32_to_cpu(*list++);
  170. size -= sizeof(*list);
  171. offset = fdt_node_offset_by_phandle(fdt, phandle);
  172. if (offset < 0)
  173. return offset;
  174. drive = fdt_getprop_u32_default_node(fdt, offset, 0,
  175. "drive-strength", 0);
  176. if (drive) {
  177. if (drive <= 10)
  178. drive = 0;
  179. else if (drive <= 20)
  180. drive = 1;
  181. else if (drive <= 30)
  182. drive = 2;
  183. else
  184. drive = 3;
  185. } else {
  186. drive = fdt_getprop_u32_default_node(fdt, offset, 0,
  187. "allwinner,drive",
  188. 0);
  189. drive = min(drive, 3);
  190. }
  191. if (fdt_get_property(fdt, offset, "bias-disable", NULL))
  192. pull = 0;
  193. else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
  194. pull = 1;
  195. else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
  196. pull = 2;
  197. else
  198. pull = fdt_getprop_u32_default_node(fdt, offset, 0,
  199. "allwinner,pull",
  200. 0);
  201. pull = min(pull, 2);
  202. for (i = 0; ; i++) {
  203. pin_name = fdt_stringlist_get(fdt, offset,
  204. "pins", i, NULL);
  205. if (!pin_name) {
  206. pin_name = fdt_stringlist_get(fdt, offset,
  207. "allwinner,pins",
  208. i, NULL);
  209. if (!pin_name)
  210. break;
  211. }
  212. pin = name_to_gpio(pin_name);
  213. if (pin < 0)
  214. break;
  215. if (IS_ENABLED(CONFIG_MACH_SUN50I))
  216. sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
  217. else
  218. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
  219. sunxi_gpio_set_drv(pin, drive);
  220. sunxi_gpio_set_pull(pin, pull);
  221. }
  222. }
  223. return 0;
  224. }
  225. static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
  226. {
  227. struct sun4i_spi_priv *priv = dev_get_priv(dev);
  228. int ret;
  229. if (!enable) {
  230. clk_disable(&priv->clk_ahb);
  231. clk_disable(&priv->clk_mod);
  232. if (reset_valid(&priv->reset))
  233. reset_assert(&priv->reset);
  234. return 0;
  235. }
  236. ret = clk_enable(&priv->clk_ahb);
  237. if (ret) {
  238. dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret);
  239. return ret;
  240. }
  241. ret = clk_enable(&priv->clk_mod);
  242. if (ret) {
  243. dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret);
  244. goto err_ahb;
  245. }
  246. if (reset_valid(&priv->reset)) {
  247. ret = reset_deassert(&priv->reset);
  248. if (ret) {
  249. dev_err(dev, "failed to deassert reset\n");
  250. goto err_mod;
  251. }
  252. }
  253. return 0;
  254. err_mod:
  255. clk_disable(&priv->clk_mod);
  256. err_ahb:
  257. clk_disable(&priv->clk_ahb);
  258. return ret;
  259. }
  260. static int sun4i_spi_claim_bus(struct udevice *dev)
  261. {
  262. struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
  263. int ret;
  264. ret = sun4i_spi_set_clock(dev->parent, true);
  265. if (ret)
  266. return ret;
  267. setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE |
  268. SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP));
  269. if (priv->variant->has_soft_reset)
  270. setbits_le32(SPI_REG(priv, SPI_GCR),
  271. SPI_BIT(priv, SPI_GCR_SRST));
  272. setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
  273. SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
  274. return 0;
  275. }
  276. static int sun4i_spi_release_bus(struct udevice *dev)
  277. {
  278. struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
  279. clrbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE);
  280. sun4i_spi_set_clock(dev->parent, false);
  281. return 0;
  282. }
  283. static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
  284. const void *dout, void *din, unsigned long flags)
  285. {
  286. struct udevice *bus = dev->parent;
  287. struct sun4i_spi_priv *priv = dev_get_priv(bus);
  288. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  289. u32 len = bitlen / 8;
  290. u32 rx_fifocnt;
  291. u8 nbytes;
  292. int ret;
  293. priv->tx_buf = dout;
  294. priv->rx_buf = din;
  295. if (bitlen % 8) {
  296. debug("%s: non byte-aligned SPI transfer.\n", __func__);
  297. return -ENAVAIL;
  298. }
  299. if (flags & SPI_XFER_BEGIN)
  300. sun4i_spi_set_cs(bus, slave_plat->cs, true);
  301. /* Reset FIFOs */
  302. setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |
  303. SPI_BIT(priv, SPI_FCR_TF_RST));
  304. while (len) {
  305. /* Setup the transfer now... */
  306. nbytes = min(len, (priv->variant->fifo_depth - 1));
  307. /* Setup the counters */
  308. writel(SUN4I_BURST_CNT(nbytes), SPI_REG(priv, SPI_BC));
  309. writel(SUN4I_XMIT_CNT(nbytes), SPI_REG(priv, SPI_TC));
  310. if (priv->variant->has_burst_ctl)
  311. writel(SUN4I_BURST_CNT(nbytes),
  312. SPI_REG(priv, SPI_BCTL));
  313. /* Fill the TX FIFO */
  314. sun4i_spi_fill_fifo(priv, nbytes);
  315. /* Start the transfer */
  316. setbits_le32(SPI_REG(priv, SPI_TCR),
  317. SPI_BIT(priv, SPI_TCR_XCH));
  318. /* Wait till RX FIFO to be empty */
  319. ret = readl_poll_timeout(SPI_REG(priv, SPI_FSR),
  320. rx_fifocnt,
  321. (((rx_fifocnt &
  322. SPI_BIT(priv, SPI_FSR_RF_CNT_MASK)) >>
  323. SUN4I_FIFO_STA_RF_CNT_BITS) >= nbytes),
  324. SUN4I_SPI_TIMEOUT_US);
  325. if (ret < 0) {
  326. printf("ERROR: sun4i_spi: Timeout transferring data\n");
  327. sun4i_spi_set_cs(bus, slave_plat->cs, false);
  328. return ret;
  329. }
  330. /* Drain the RX FIFO */
  331. sun4i_spi_drain_fifo(priv, nbytes);
  332. len -= nbytes;
  333. }
  334. if (flags & SPI_XFER_END)
  335. sun4i_spi_set_cs(bus, slave_plat->cs, false);
  336. return 0;
  337. }
  338. static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
  339. {
  340. struct sun4i_spi_platdata *plat = dev_get_platdata(dev);
  341. struct sun4i_spi_priv *priv = dev_get_priv(dev);
  342. unsigned int div;
  343. u32 reg;
  344. if (speed > plat->max_hz)
  345. speed = plat->max_hz;
  346. if (speed < SUN4I_SPI_MIN_RATE)
  347. speed = SUN4I_SPI_MIN_RATE;
  348. /*
  349. * Setup clock divider.
  350. *
  351. * We have two choices there. Either we can use the clock
  352. * divide rate 1, which is calculated thanks to this formula:
  353. * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
  354. * Or we can use CDR2, which is calculated with the formula:
  355. * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
  356. * Whether we use the former or the latter is set through the
  357. * DRS bit.
  358. *
  359. * First try CDR2, and if we can't reach the expected
  360. * frequency, fall back to CDR1.
  361. */
  362. div = SUN4I_SPI_MAX_RATE / (2 * speed);
  363. reg = readl(SPI_REG(priv, SPI_CCR));
  364. if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
  365. if (div > 0)
  366. div--;
  367. reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
  368. reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
  369. } else {
  370. div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);
  371. reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
  372. reg |= SUN4I_CLK_CTL_CDR1(div);
  373. }
  374. priv->freq = speed;
  375. writel(reg, SPI_REG(priv, SPI_CCR));
  376. return 0;
  377. }
  378. static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
  379. {
  380. struct sun4i_spi_priv *priv = dev_get_priv(dev);
  381. u32 reg;
  382. reg = readl(SPI_REG(priv, SPI_TCR));
  383. reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
  384. if (mode & SPI_CPOL)
  385. reg |= SPI_BIT(priv, SPI_TCR_CPOL);
  386. if (mode & SPI_CPHA)
  387. reg |= SPI_BIT(priv, SPI_TCR_CPHA);
  388. priv->mode = mode;
  389. writel(reg, SPI_REG(priv, SPI_TCR));
  390. return 0;
  391. }
  392. static const struct dm_spi_ops sun4i_spi_ops = {
  393. .claim_bus = sun4i_spi_claim_bus,
  394. .release_bus = sun4i_spi_release_bus,
  395. .xfer = sun4i_spi_xfer,
  396. .set_speed = sun4i_spi_set_speed,
  397. .set_mode = sun4i_spi_set_mode,
  398. };
  399. static int sun4i_spi_probe(struct udevice *bus)
  400. {
  401. struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
  402. struct sun4i_spi_priv *priv = dev_get_priv(bus);
  403. int ret;
  404. ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
  405. if (ret) {
  406. dev_err(dev, "failed to get ahb clock\n");
  407. return ret;
  408. }
  409. ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
  410. if (ret) {
  411. dev_err(dev, "failed to get mod clock\n");
  412. return ret;
  413. }
  414. ret = reset_get_by_index(bus, 0, &priv->reset);
  415. if (ret && ret != -ENOENT) {
  416. dev_err(dev, "failed to get reset\n");
  417. return ret;
  418. }
  419. sun4i_spi_parse_pins(bus);
  420. priv->variant = plat->variant;
  421. priv->base = plat->base;
  422. priv->freq = plat->max_hz;
  423. return 0;
  424. }
  425. static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
  426. {
  427. struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
  428. int node = dev_of_offset(bus);
  429. plat->base = devfdt_get_addr(bus);
  430. plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
  431. plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
  432. "spi-max-frequency",
  433. SUN4I_SPI_DEFAULT_RATE);
  434. if (plat->max_hz > SUN4I_SPI_MAX_RATE)
  435. plat->max_hz = SUN4I_SPI_MAX_RATE;
  436. return 0;
  437. }
  438. static const unsigned long sun4i_spi_regs[] = {
  439. [SPI_GCR] = SUN4I_CTL_REG,
  440. [SPI_TCR] = SUN4I_CTL_REG,
  441. [SPI_FCR] = SUN4I_CTL_REG,
  442. [SPI_FSR] = SUN4I_FIFO_STA_REG,
  443. [SPI_CCR] = SUN4I_CLK_CTL_REG,
  444. [SPI_BC] = SUN4I_BURST_CNT_REG,
  445. [SPI_TC] = SUN4I_XMIT_CNT_REG,
  446. [SPI_TXD] = SUN4I_TXDATA_REG,
  447. [SPI_RXD] = SUN4I_RXDATA_REG,
  448. };
  449. static const u32 sun4i_spi_bits[] = {
  450. [SPI_GCR_TP] = BIT(18),
  451. [SPI_TCR_CPHA] = BIT(2),
  452. [SPI_TCR_CPOL] = BIT(3),
  453. [SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
  454. [SPI_TCR_XCH] = BIT(10),
  455. [SPI_TCR_CS_SEL] = 12,
  456. [SPI_TCR_CS_MASK] = 0x3000,
  457. [SPI_TCR_CS_MANUAL] = BIT(16),
  458. [SPI_TCR_CS_LEVEL] = BIT(17),
  459. [SPI_FCR_TF_RST] = BIT(8),
  460. [SPI_FCR_RF_RST] = BIT(9),
  461. [SPI_FSR_RF_CNT_MASK] = GENMASK(6, 0),
  462. };
  463. static const unsigned long sun6i_spi_regs[] = {
  464. [SPI_GCR] = SUN6I_GBL_CTL_REG,
  465. [SPI_TCR] = SUN6I_TFR_CTL_REG,
  466. [SPI_FCR] = SUN6I_FIFO_CTL_REG,
  467. [SPI_FSR] = SUN6I_FIFO_STA_REG,
  468. [SPI_CCR] = SUN6I_CLK_CTL_REG,
  469. [SPI_BC] = SUN6I_BURST_CNT_REG,
  470. [SPI_TC] = SUN6I_XMIT_CNT_REG,
  471. [SPI_BCTL] = SUN6I_BURST_CTL_REG,
  472. [SPI_TXD] = SUN6I_TXDATA_REG,
  473. [SPI_RXD] = SUN6I_RXDATA_REG,
  474. };
  475. static const u32 sun6i_spi_bits[] = {
  476. [SPI_GCR_TP] = BIT(7),
  477. [SPI_GCR_SRST] = BIT(31),
  478. [SPI_TCR_CPHA] = BIT(0),
  479. [SPI_TCR_CPOL] = BIT(1),
  480. [SPI_TCR_CS_ACTIVE_LOW] = BIT(2),
  481. [SPI_TCR_CS_SEL] = 4,
  482. [SPI_TCR_CS_MASK] = 0x30,
  483. [SPI_TCR_CS_MANUAL] = BIT(6),
  484. [SPI_TCR_CS_LEVEL] = BIT(7),
  485. [SPI_TCR_XCH] = BIT(31),
  486. [SPI_FCR_RF_RST] = BIT(15),
  487. [SPI_FCR_TF_RST] = BIT(31),
  488. [SPI_FSR_RF_CNT_MASK] = GENMASK(7, 0),
  489. };
  490. static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
  491. .regs = sun4i_spi_regs,
  492. .bits = sun4i_spi_bits,
  493. .fifo_depth = 64,
  494. };
  495. static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
  496. .regs = sun6i_spi_regs,
  497. .bits = sun6i_spi_bits,
  498. .fifo_depth = 128,
  499. .has_soft_reset = true,
  500. .has_burst_ctl = true,
  501. };
  502. static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
  503. .regs = sun6i_spi_regs,
  504. .bits = sun6i_spi_bits,
  505. .fifo_depth = 64,
  506. .has_soft_reset = true,
  507. .has_burst_ctl = true,
  508. };
  509. static const struct udevice_id sun4i_spi_ids[] = {
  510. {
  511. .compatible = "allwinner,sun4i-a10-spi",
  512. .data = (ulong)&sun4i_a10_spi_variant,
  513. },
  514. {
  515. .compatible = "allwinner,sun6i-a31-spi",
  516. .data = (ulong)&sun6i_a31_spi_variant,
  517. },
  518. {
  519. .compatible = "allwinner,sun8i-h3-spi",
  520. .data = (ulong)&sun8i_h3_spi_variant,
  521. },
  522. { /* sentinel */ }
  523. };
  524. U_BOOT_DRIVER(sun4i_spi) = {
  525. .name = "sun4i_spi",
  526. .id = UCLASS_SPI,
  527. .of_match = sun4i_spi_ids,
  528. .ops = &sun4i_spi_ops,
  529. .ofdata_to_platdata = sun4i_spi_ofdata_to_platdata,
  530. .platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata),
  531. .priv_auto_alloc_size = sizeof(struct sun4i_spi_priv),
  532. .probe = sun4i_spi_probe,
  533. };