fsl_qspi.h 3.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013-2014 Freescale Semiconductor, Inc.
  4. *
  5. * Register definitions for Freescale QSPI
  6. */
  7. #ifndef _FSL_QSPI_H_
  8. #define _FSL_QSPI_H_
  9. struct fsl_qspi_regs {
  10. u32 mcr;
  11. u32 rsvd0[1];
  12. u32 ipcr;
  13. u32 flshcr;
  14. u32 buf0cr;
  15. u32 buf1cr;
  16. u32 buf2cr;
  17. u32 buf3cr;
  18. u32 bfgencr;
  19. u32 soccr;
  20. u32 rsvd1[2];
  21. u32 buf0ind;
  22. u32 buf1ind;
  23. u32 buf2ind;
  24. u32 rsvd2[49];
  25. u32 sfar;
  26. u32 rsvd3[1];
  27. u32 smpr;
  28. u32 rbsr;
  29. u32 rbct;
  30. u32 rsvd4[15];
  31. u32 tbsr;
  32. u32 tbdr;
  33. u32 rsvd5[1];
  34. u32 sr;
  35. u32 fr;
  36. u32 rser;
  37. u32 spndst;
  38. u32 sptrclr;
  39. u32 rsvd6[4];
  40. u32 sfa1ad;
  41. u32 sfa2ad;
  42. u32 sfb1ad;
  43. u32 sfb2ad;
  44. u32 rsvd7[28];
  45. u32 rbdr[32];
  46. u32 rsvd8[32];
  47. u32 lutkey;
  48. u32 lckcr;
  49. u32 rsvd9[2];
  50. u32 lut[64];
  51. };
  52. #define QSPI_IPCR_SEQID_SHIFT 24
  53. #define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT)
  54. #define QSPI_MCR_END_CFD_SHIFT 2
  55. #define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT)
  56. #ifdef CONFIG_SYS_FSL_QSPI_AHB
  57. /* AHB needs 64bit operation */
  58. #define QSPI_MCR_END_CFD_LE (3 << QSPI_MCR_END_CFD_SHIFT)
  59. #else
  60. #define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT)
  61. #endif
  62. #define QSPI_MCR_DDR_EN_SHIFT 7
  63. #define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT)
  64. #define QSPI_MCR_CLR_RXF_SHIFT 10
  65. #define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT)
  66. #define QSPI_MCR_CLR_TXF_SHIFT 11
  67. #define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT)
  68. #define QSPI_MCR_MDIS_SHIFT 14
  69. #define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT)
  70. #define QSPI_MCR_RESERVED_SHIFT 16
  71. #define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT)
  72. #define QSPI_MCR_SWRSTHD_SHIFT 1
  73. #define QSPI_MCR_SWRSTHD_MASK (1 << QSPI_MCR_SWRSTHD_SHIFT)
  74. #define QSPI_MCR_SWRSTSD_SHIFT 0
  75. #define QSPI_MCR_SWRSTSD_MASK (1 << QSPI_MCR_SWRSTSD_SHIFT)
  76. #define QSPI_SMPR_HSENA_SHIFT 0
  77. #define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT)
  78. #define QSPI_SMPR_FSPHS_SHIFT 5
  79. #define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT)
  80. #define QSPI_SMPR_FSDLY_SHIFT 6
  81. #define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT)
  82. #define QSPI_SMPR_DDRSMP_SHIFT 16
  83. #define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT)
  84. #define QSPI_BUFXCR_INVALID_MSTRID 0xe
  85. #define QSPI_BUF3CR_ALLMST_SHIFT 31
  86. #define QSPI_BUF3CR_ALLMST_MASK (1 << QSPI_BUF3CR_ALLMST_SHIFT)
  87. #define QSPI_BUF3CR_ADATSZ_SHIFT 8
  88. #define QSPI_BUF3CR_ADATSZ_MASK (0xFF << QSPI_BUF3CR_ADATSZ_SHIFT)
  89. #define QSPI_BFGENCR_SEQID_SHIFT 12
  90. #define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT)
  91. #define QSPI_BFGENCR_PAR_EN_SHIFT 16
  92. #define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT)
  93. #define QSPI_RBSR_RDBFL_SHIFT 8
  94. #define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT)
  95. #define QSPI_RBCT_RXBRD_SHIFT 8
  96. #define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
  97. #define QSPI_SR_AHB_ACC_SHIFT 2
  98. #define QSPI_SR_AHB_ACC_MASK (1 << QSPI_SR_AHB_ACC_SHIFT)
  99. #define QSPI_SR_IP_ACC_SHIFT 1
  100. #define QSPI_SR_IP_ACC_MASK (1 << QSPI_SR_IP_ACC_SHIFT)
  101. #define QSPI_SR_BUSY_SHIFT 0
  102. #define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT)
  103. #define QSPI_LCKCR_LOCK 0x1
  104. #define QSPI_LCKCR_UNLOCK 0x2
  105. #define LUT_KEY_VALUE 0x5af05af0
  106. #define OPRND0_SHIFT 0
  107. #define OPRND0(x) ((x) << OPRND0_SHIFT)
  108. #define PAD0_SHIFT 8
  109. #define PAD0(x) ((x) << PAD0_SHIFT)
  110. #define INSTR0_SHIFT 10
  111. #define INSTR0(x) ((x) << INSTR0_SHIFT)
  112. #define OPRND1_SHIFT 16
  113. #define OPRND1(x) ((x) << OPRND1_SHIFT)
  114. #define PAD1_SHIFT 24
  115. #define PAD1(x) ((x) << PAD1_SHIFT)
  116. #define INSTR1_SHIFT 26
  117. #define INSTR1(x) ((x) << INSTR1_SHIFT)
  118. #define LUT_CMD 1
  119. #define LUT_ADDR 2
  120. #define LUT_DUMMY 3
  121. #define LUT_READ 7
  122. #define LUT_WRITE 8
  123. #define LUT_PAD1 0
  124. #define LUT_PAD2 1
  125. #define LUT_PAD4 2
  126. #define ADDR24BIT 0x18
  127. #define ADDR32BIT 0x20
  128. #endif /* _FSL_QSPI_H_ */