pcie_layerscape_gen4_fixup.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2018-2019 NXP
  4. *
  5. * PCIe Gen4 driver for NXP Layerscape SoCs
  6. * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
  7. *
  8. */
  9. #include <common.h>
  10. #include <pci.h>
  11. #include <asm/arch/fsl_serdes.h>
  12. #include <asm/io.h>
  13. #include <errno.h>
  14. #ifdef CONFIG_OF_BOARD_SETUP
  15. #include <linux/libfdt.h>
  16. #include <fdt_support.h>
  17. #ifdef CONFIG_ARM
  18. #include <asm/arch/clock.h>
  19. #endif
  20. #include "pcie_layerscape_gen4.h"
  21. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  22. /*
  23. * Return next available LUT index.
  24. */
  25. static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
  26. {
  27. if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
  28. return pcie->next_lut_index++;
  29. return -ENOSPC; /* LUT is full */
  30. }
  31. /* returns the next available streamid for pcie, -errno if failed */
  32. static int ls_pcie_g4_next_streamid(struct ls_pcie_g4 *pcie)
  33. {
  34. int stream_id = pcie->stream_id_cur;
  35. if (stream_id > FSL_PEX_STREAM_ID_NUM)
  36. return -EINVAL;
  37. pcie->stream_id_cur++;
  38. return stream_id | ((pcie->idx + 1) << 11);
  39. }
  40. /*
  41. * Program a single LUT entry
  42. */
  43. static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
  44. u32 devid, u32 streamid)
  45. {
  46. /* leave mask as all zeroes, want to match all bits */
  47. lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
  48. lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
  49. }
  50. /*
  51. * An msi-map is a property to be added to the pci controller
  52. * node. It is a table, where each entry consists of 4 fields
  53. * e.g.:
  54. *
  55. * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
  56. * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
  57. */
  58. static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie_g4 *pcie,
  59. u32 devid, u32 streamid)
  60. {
  61. u32 *prop;
  62. u32 phandle;
  63. int nodeoff;
  64. #ifdef CONFIG_FSL_PCIE_COMPAT
  65. nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
  66. pcie->ccsr_res.start);
  67. #else
  68. #error "No CONFIG_FSL_PCIE_COMPAT defined"
  69. #endif
  70. if (nodeoff < 0) {
  71. debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
  72. return;
  73. }
  74. /* get phandle to MSI controller */
  75. prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0);
  76. if (!prop) {
  77. debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
  78. __func__, pcie->idx);
  79. return;
  80. }
  81. phandle = fdt32_to_cpu(*prop);
  82. /* set one msi-map row */
  83. fdt_appendprop_u32(blob, nodeoff, "msi-map", devid);
  84. fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle);
  85. fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid);
  86. fdt_appendprop_u32(blob, nodeoff, "msi-map", 1);
  87. }
  88. /*
  89. * An iommu-map is a property to be added to the pci controller
  90. * node. It is a table, where each entry consists of 4 fields
  91. * e.g.:
  92. *
  93. * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
  94. * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
  95. */
  96. static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie_g4 *pcie,
  97. u32 devid, u32 streamid)
  98. {
  99. u32 *prop;
  100. u32 iommu_map[4];
  101. int nodeoff;
  102. int lenp;
  103. #ifdef CONFIG_FSL_PCIE_COMPAT
  104. nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
  105. pcie->ccsr_res.start);
  106. #else
  107. #error "No CONFIG_FSL_PCIE_COMPAT defined"
  108. #endif
  109. if (nodeoff < 0) {
  110. debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
  111. return;
  112. }
  113. /* get phandle to iommu controller */
  114. prop = fdt_getprop_w(blob, nodeoff, "iommu-map", &lenp);
  115. if (!prop) {
  116. debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
  117. __func__, pcie->idx);
  118. return;
  119. }
  120. /* set iommu-map row */
  121. iommu_map[0] = cpu_to_fdt32(devid);
  122. iommu_map[1] = *++prop;
  123. iommu_map[2] = cpu_to_fdt32(streamid);
  124. iommu_map[3] = cpu_to_fdt32(1);
  125. if (devid == 0)
  126. fdt_setprop_inplace(blob, nodeoff, "iommu-map", iommu_map, 16);
  127. else
  128. fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16);
  129. }
  130. static void fdt_fixup_pcie(void *blob)
  131. {
  132. struct udevice *dev, *bus;
  133. struct ls_pcie_g4 *pcie;
  134. int streamid;
  135. int index;
  136. pci_dev_t bdf;
  137. /* Scan all known buses */
  138. for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {
  139. for (bus = dev; device_is_on_pci_bus(bus);)
  140. bus = bus->parent;
  141. pcie = dev_get_priv(bus);
  142. streamid = ls_pcie_g4_next_streamid(pcie);
  143. if (streamid < 0) {
  144. debug("ERROR: no stream ids free\n");
  145. continue;
  146. }
  147. index = ls_pcie_g4_next_lut_index(pcie);
  148. if (index < 0) {
  149. debug("ERROR: no LUT indexes free\n");
  150. continue;
  151. }
  152. /* the DT fixup must be relative to the hose first_busno */
  153. bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
  154. /* map PCI b.d.f to streamID in LUT */
  155. ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);
  156. /* update msi-map in device tree */
  157. fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, streamid);
  158. /* update iommu-map in device tree */
  159. fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8, streamid);
  160. }
  161. }
  162. #endif
  163. static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
  164. {
  165. int off;
  166. off = fdt_node_offset_by_compat_reg(blob, "fsl,lx2160a-pcie-ep",
  167. pcie->ccsr_res.start);
  168. if (off < 0) {
  169. debug("%s: ERROR: failed to find pcie compatiable\n",
  170. __func__);
  171. return;
  172. }
  173. if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
  174. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  175. else
  176. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  177. }
  178. static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
  179. {
  180. int off;
  181. #ifdef CONFIG_FSL_PCIE_COMPAT
  182. off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
  183. pcie->ccsr_res.start);
  184. #else
  185. #error "No CONFIG_FSL_PCIE_COMPAT defined"
  186. #endif
  187. if (off < 0) {
  188. debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
  189. return;
  190. }
  191. if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
  192. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  193. else
  194. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  195. }
  196. static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
  197. {
  198. ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
  199. ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
  200. }
  201. /* Fixup Kernel DT for PCIe */
  202. void ft_pci_setup(void *blob, bd_t *bd)
  203. {
  204. struct ls_pcie_g4 *pcie;
  205. list_for_each_entry(pcie, &ls_pcie_g4_list, list)
  206. ft_pcie_layerscape_gen4_setup(blob, pcie);
  207. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  208. fdt_fixup_pcie(blob);
  209. #endif
  210. }
  211. #else /* !CONFIG_OF_BOARD_SETUP */
  212. void ft_pci_setup(void *blob, bd_t *bd)
  213. {
  214. }
  215. #endif