ti-edma3.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Enhanced Direct Memory Access (EDMA3) Controller
  4. *
  5. * (C) Copyright 2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. *
  8. * Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
  9. */
  10. #include <asm/io.h>
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <dma-uclass.h>
  14. #include <asm/omap_common.h>
  15. #include <asm/ti-common/ti-edma3.h>
  16. #define EDMA3_SL_BASE(slot) (0x4000 + ((slot) << 5))
  17. #define EDMA3_SL_MAX_NUM 512
  18. #define EDMA3_SLOPT_FIFO_WIDTH_MASK (0x7 << 8)
  19. #define EDMA3_QCHMAP(ch) 0x0200 + ((ch) << 2)
  20. #define EDMA3_CHMAP_PARSET_MASK 0x1ff
  21. #define EDMA3_CHMAP_PARSET_SHIFT 0x5
  22. #define EDMA3_CHMAP_TRIGWORD_SHIFT 0x2
  23. #define EDMA3_QEMCR 0x314
  24. #define EDMA3_IPR 0x1068
  25. #define EDMA3_IPRH 0x106c
  26. #define EDMA3_ICR 0x1070
  27. #define EDMA3_ICRH 0x1074
  28. #define EDMA3_QEECR 0x1088
  29. #define EDMA3_QEESR 0x108c
  30. #define EDMA3_QSECR 0x1094
  31. #define EDMA_FILL_BUFFER_SIZE 512
  32. struct ti_edma3_priv {
  33. u32 base;
  34. };
  35. static u8 edma_fill_buffer[EDMA_FILL_BUFFER_SIZE] __aligned(ARCH_DMA_MINALIGN);
  36. /**
  37. * qedma3_start - start qdma on a channel
  38. * @base: base address of edma
  39. * @cfg: pinter to struct edma3_channel_config where you can set
  40. * the slot number to associate with, the chnum, which corresponds
  41. * your quick channel number 0-7, complete code - transfer complete code
  42. * and trigger slot word - which has to correspond to the word number in
  43. * edma3_slot_layout struct for generating event.
  44. *
  45. */
  46. void qedma3_start(u32 base, struct edma3_channel_config *cfg)
  47. {
  48. u32 qchmap;
  49. /* Clear the pending int bit */
  50. if (cfg->complete_code < 32)
  51. __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);
  52. else
  53. __raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);
  54. /* Map parameter set and trigger word 7 to quick channel */
  55. qchmap = ((EDMA3_CHMAP_PARSET_MASK & cfg->slot)
  56. << EDMA3_CHMAP_PARSET_SHIFT) |
  57. (cfg->trigger_slot_word << EDMA3_CHMAP_TRIGWORD_SHIFT);
  58. __raw_writel(qchmap, base + EDMA3_QCHMAP(cfg->chnum));
  59. /* Clear missed event if set*/
  60. __raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);
  61. __raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);
  62. /* Enable qdma channel event */
  63. __raw_writel(1 << cfg->chnum, base + EDMA3_QEESR);
  64. }
  65. /**
  66. * edma3_set_dest - set initial DMA destination address in parameter RAM slot
  67. * @base: base address of edma
  68. * @slot: parameter RAM slot being configured
  69. * @dst: physical address of destination (memory, controller FIFO, etc)
  70. * @addressMode: INCR, except in very rare cases
  71. * @width: ignored unless @addressMode is FIFO, else specifies the
  72. * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
  73. *
  74. * Note that the destination address is modified during the DMA transfer
  75. * according to edma3_set_dest_index().
  76. */
  77. void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
  78. enum edma3_fifo_width width)
  79. {
  80. u32 opt;
  81. struct edma3_slot_layout *rg;
  82. rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
  83. opt = __raw_readl(&rg->opt);
  84. if (mode == FIFO)
  85. opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) |
  86. (EDMA3_SLOPT_DST_ADDR_CONST_MODE |
  87. EDMA3_SLOPT_FIFO_WIDTH_SET(width));
  88. else
  89. opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE;
  90. __raw_writel(opt, &rg->opt);
  91. __raw_writel(dst, &rg->dst);
  92. }
  93. /**
  94. * edma3_set_dest_index - configure DMA destination address indexing
  95. * @base: base address of edma
  96. * @slot: parameter RAM slot being configured
  97. * @bidx: byte offset between destination arrays in a frame
  98. * @cidx: byte offset between destination frames in a block
  99. *
  100. * Offsets are specified to support either contiguous or discontiguous
  101. * memory transfers, or repeated access to a hardware register, as needed.
  102. * When accessing hardware registers, both offsets are normally zero.
  103. */
  104. void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx)
  105. {
  106. u32 src_dst_bidx;
  107. u32 src_dst_cidx;
  108. struct edma3_slot_layout *rg;
  109. rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
  110. src_dst_bidx = __raw_readl(&rg->src_dst_bidx);
  111. src_dst_cidx = __raw_readl(&rg->src_dst_cidx);
  112. __raw_writel((src_dst_bidx & 0x0000ffff) | (bidx << 16),
  113. &rg->src_dst_bidx);
  114. __raw_writel((src_dst_cidx & 0x0000ffff) | (cidx << 16),
  115. &rg->src_dst_cidx);
  116. }
  117. /**
  118. * edma3_set_dest_addr - set destination address for slot only
  119. */
  120. void edma3_set_dest_addr(u32 base, int slot, u32 dst)
  121. {
  122. struct edma3_slot_layout *rg;
  123. rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
  124. __raw_writel(dst, &rg->dst);
  125. }
  126. /**
  127. * edma3_set_src - set initial DMA source address in parameter RAM slot
  128. * @base: base address of edma
  129. * @slot: parameter RAM slot being configured
  130. * @src_port: physical address of source (memory, controller FIFO, etc)
  131. * @mode: INCR, except in very rare cases
  132. * @width: ignored unless @addressMode is FIFO, else specifies the
  133. * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
  134. *
  135. * Note that the source address is modified during the DMA transfer
  136. * according to edma3_set_src_index().
  137. */
  138. void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
  139. enum edma3_fifo_width width)
  140. {
  141. u32 opt;
  142. struct edma3_slot_layout *rg;
  143. rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
  144. opt = __raw_readl(&rg->opt);
  145. if (mode == FIFO)
  146. opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) |
  147. (EDMA3_SLOPT_DST_ADDR_CONST_MODE |
  148. EDMA3_SLOPT_FIFO_WIDTH_SET(width));
  149. else
  150. opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE;
  151. __raw_writel(opt, &rg->opt);
  152. __raw_writel(src, &rg->src);
  153. }
  154. /**
  155. * edma3_set_src_index - configure DMA source address indexing
  156. * @base: base address of edma
  157. * @slot: parameter RAM slot being configured
  158. * @bidx: byte offset between source arrays in a frame
  159. * @cidx: byte offset between source frames in a block
  160. *
  161. * Offsets are specified to support either contiguous or discontiguous
  162. * memory transfers, or repeated access to a hardware register, as needed.
  163. * When accessing hardware registers, both offsets are normally zero.
  164. */
  165. void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx)
  166. {
  167. u32 src_dst_bidx;
  168. u32 src_dst_cidx;
  169. struct edma3_slot_layout *rg;
  170. rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
  171. src_dst_bidx = __raw_readl(&rg->src_dst_bidx);
  172. src_dst_cidx = __raw_readl(&rg->src_dst_cidx);
  173. __raw_writel((src_dst_bidx & 0xffff0000) | bidx,
  174. &rg->src_dst_bidx);
  175. __raw_writel((src_dst_cidx & 0xffff0000) | cidx,
  176. &rg->src_dst_cidx);
  177. }
  178. /**
  179. * edma3_set_src_addr - set source address for slot only
  180. */
  181. void edma3_set_src_addr(u32 base, int slot, u32 src)
  182. {
  183. struct edma3_slot_layout *rg;
  184. rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
  185. __raw_writel(src, &rg->src);
  186. }
  187. /**
  188. * edma3_set_transfer_params - configure DMA transfer parameters
  189. * @base: base address of edma
  190. * @slot: parameter RAM slot being configured
  191. * @acnt: how many bytes per array (at least one)
  192. * @bcnt: how many arrays per frame (at least one)
  193. * @ccnt: how many frames per block (at least one)
  194. * @bcnt_rld: used only for A-Synchronized transfers; this specifies
  195. * the value to reload into bcnt when it decrements to zero
  196. * @sync_mode: ASYNC or ABSYNC
  197. *
  198. * See the EDMA3 documentation to understand how to configure and link
  199. * transfers using the fields in PaRAM slots. If you are not doing it
  200. * all at once with edma3_write_slot(), you will use this routine
  201. * plus two calls each for source and destination, setting the initial
  202. * address and saying how to index that address.
  203. *
  204. * An example of an A-Synchronized transfer is a serial link using a
  205. * single word shift register. In that case, @acnt would be equal to
  206. * that word size; the serial controller issues a DMA synchronization
  207. * event to transfer each word, and memory access by the DMA transfer
  208. * controller will be word-at-a-time.
  209. *
  210. * An example of an AB-Synchronized transfer is a device using a FIFO.
  211. * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
  212. * The controller with the FIFO issues DMA synchronization events when
  213. * the FIFO threshold is reached, and the DMA transfer controller will
  214. * transfer one frame to (or from) the FIFO. It will probably use
  215. * efficient burst modes to access memory.
  216. */
  217. void edma3_set_transfer_params(u32 base, int slot, int acnt,
  218. int bcnt, int ccnt, u16 bcnt_rld,
  219. enum edma3_sync_dimension sync_mode)
  220. {
  221. u32 opt;
  222. u32 link_bcntrld;
  223. struct edma3_slot_layout *rg;
  224. rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
  225. link_bcntrld = __raw_readl(&rg->link_bcntrld);
  226. __raw_writel((bcnt_rld << 16) | (0x0000ffff & link_bcntrld),
  227. &rg->link_bcntrld);
  228. opt = __raw_readl(&rg->opt);
  229. if (sync_mode == ASYNC)
  230. __raw_writel(opt & ~EDMA3_SLOPT_AB_SYNC, &rg->opt);
  231. else
  232. __raw_writel(opt | EDMA3_SLOPT_AB_SYNC, &rg->opt);
  233. /* Set the acount, bcount, ccount registers */
  234. __raw_writel((bcnt << 16) | (acnt & 0xffff), &rg->a_b_cnt);
  235. __raw_writel(0xffff & ccnt, &rg->ccnt);
  236. }
  237. /**
  238. * edma3_write_slot - write parameter RAM data for slot
  239. * @base: base address of edma
  240. * @slot: number of parameter RAM slot being modified
  241. * @param: data to be written into parameter RAM slot
  242. *
  243. * Use this to assign all parameters of a transfer at once. This
  244. * allows more efficient setup of transfers than issuing multiple
  245. * calls to set up those parameters in small pieces, and provides
  246. * complete control over all transfer options.
  247. */
  248. void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param)
  249. {
  250. int i;
  251. u32 *p = (u32 *)param;
  252. u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot));
  253. for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4)
  254. __raw_writel(*p++, addr++);
  255. }
  256. /**
  257. * edma3_read_slot - read parameter RAM data from slot
  258. * @base: base address of edma
  259. * @slot: number of parameter RAM slot being copied
  260. * @param: where to store copy of parameter RAM data
  261. *
  262. * Use this to read data from a parameter RAM slot, perhaps to
  263. * save them as a template for later reuse.
  264. */
  265. void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param)
  266. {
  267. int i;
  268. u32 *p = (u32 *)param;
  269. u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot));
  270. for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4)
  271. *p++ = __raw_readl(addr++);
  272. }
  273. void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg)
  274. {
  275. struct edma3_slot_layout *rg;
  276. rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
  277. __raw_writel(cfg->opt, &rg->opt);
  278. __raw_writel(cfg->src, &rg->src);
  279. __raw_writel((cfg->bcnt << 16) | (cfg->acnt & 0xffff), &rg->a_b_cnt);
  280. __raw_writel(cfg->dst, &rg->dst);
  281. __raw_writel((cfg->dst_bidx << 16) |
  282. (cfg->src_bidx & 0xffff), &rg->src_dst_bidx);
  283. __raw_writel((cfg->bcntrld << 16) |
  284. (cfg->link & 0xffff), &rg->link_bcntrld);
  285. __raw_writel((cfg->dst_cidx << 16) |
  286. (cfg->src_cidx & 0xffff), &rg->src_dst_cidx);
  287. __raw_writel(0xffff & cfg->ccnt, &rg->ccnt);
  288. }
  289. /**
  290. * edma3_check_for_transfer - check if transfer coplete by checking
  291. * interrupt pending bit. Clear interrupt pending bit if complete.
  292. * @base: base address of edma
  293. * @cfg: pinter to struct edma3_channel_config which was passed
  294. * to qedma3_start when you started qdma channel
  295. *
  296. * Return 0 if complete, 1 if not.
  297. */
  298. int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg)
  299. {
  300. u32 inum;
  301. u32 ipr_base;
  302. u32 icr_base;
  303. if (cfg->complete_code < 32) {
  304. ipr_base = base + EDMA3_IPR;
  305. icr_base = base + EDMA3_ICR;
  306. inum = 1 << cfg->complete_code;
  307. } else {
  308. ipr_base = base + EDMA3_IPRH;
  309. icr_base = base + EDMA3_ICRH;
  310. inum = 1 << (cfg->complete_code - 32);
  311. }
  312. /* check complete interrupt */
  313. if (!(__raw_readl(ipr_base) & inum))
  314. return 1;
  315. /* clean up the pending int bit */
  316. __raw_writel(inum, icr_base);
  317. return 0;
  318. }
  319. /**
  320. * qedma3_stop - stops dma on the channel passed
  321. * @base: base address of edma
  322. * @cfg: pinter to struct edma3_channel_config which was passed
  323. * to qedma3_start when you started qdma channel
  324. */
  325. void qedma3_stop(u32 base, struct edma3_channel_config *cfg)
  326. {
  327. /* Disable qdma channel event */
  328. __raw_writel(1 << cfg->chnum, base + EDMA3_QEECR);
  329. /* clean up the interrupt indication */
  330. if (cfg->complete_code < 32)
  331. __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);
  332. else
  333. __raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);
  334. /* Clear missed event if set*/
  335. __raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);
  336. __raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);
  337. /* Clear the channel map */
  338. __raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum));
  339. }
  340. void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
  341. void *dst, void *src, size_t len, size_t s_len)
  342. {
  343. struct edma3_slot_config slot;
  344. struct edma3_channel_config edma_channel;
  345. int b_cnt_value = 1;
  346. int rem_bytes = 0;
  347. int a_cnt_value = len;
  348. unsigned int addr = (unsigned int) (dst);
  349. unsigned int max_acnt = 0x7FFFU;
  350. if (len > s_len) {
  351. b_cnt_value = (len / s_len);
  352. rem_bytes = (len % s_len);
  353. a_cnt_value = s_len;
  354. } else if (len > max_acnt) {
  355. b_cnt_value = (len / max_acnt);
  356. rem_bytes = (len % max_acnt);
  357. a_cnt_value = max_acnt;
  358. }
  359. slot.opt = 0;
  360. slot.src = ((unsigned int) src);
  361. slot.acnt = a_cnt_value;
  362. slot.bcnt = b_cnt_value;
  363. slot.ccnt = 1;
  364. if (len == s_len)
  365. slot.src_bidx = a_cnt_value;
  366. else
  367. slot.src_bidx = 0;
  368. slot.dst_bidx = a_cnt_value;
  369. slot.src_cidx = 0;
  370. slot.dst_cidx = 0;
  371. slot.link = EDMA3_PARSET_NULL_LINK;
  372. slot.bcntrld = 0;
  373. slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
  374. EDMA3_SLOPT_COMP_CODE(0) |
  375. EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
  376. edma3_slot_configure(edma3_base_addr, edma_slot_num, &slot);
  377. edma_channel.slot = edma_slot_num;
  378. edma_channel.chnum = 0;
  379. edma_channel.complete_code = 0;
  380. /* set event trigger to dst update */
  381. edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
  382. qedma3_start(edma3_base_addr, &edma_channel);
  383. edma3_set_dest_addr(edma3_base_addr, edma_channel.slot, addr);
  384. while (edma3_check_for_transfer(edma3_base_addr, &edma_channel))
  385. ;
  386. qedma3_stop(edma3_base_addr, &edma_channel);
  387. if (rem_bytes != 0) {
  388. slot.opt = 0;
  389. if (len == s_len)
  390. slot.src =
  391. (b_cnt_value * max_acnt) + ((unsigned int) src);
  392. else
  393. slot.src = (unsigned int) src;
  394. slot.acnt = rem_bytes;
  395. slot.bcnt = 1;
  396. slot.ccnt = 1;
  397. slot.src_bidx = rem_bytes;
  398. slot.dst_bidx = rem_bytes;
  399. slot.src_cidx = 0;
  400. slot.dst_cidx = 0;
  401. slot.link = EDMA3_PARSET_NULL_LINK;
  402. slot.bcntrld = 0;
  403. slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
  404. EDMA3_SLOPT_COMP_CODE(0) |
  405. EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
  406. edma3_slot_configure(edma3_base_addr, edma_slot_num, &slot);
  407. edma_channel.slot = edma_slot_num;
  408. edma_channel.chnum = 0;
  409. edma_channel.complete_code = 0;
  410. /* set event trigger to dst update */
  411. edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
  412. qedma3_start(edma3_base_addr, &edma_channel);
  413. edma3_set_dest_addr(edma3_base_addr, edma_channel.slot, addr +
  414. (max_acnt * b_cnt_value));
  415. while (edma3_check_for_transfer(edma3_base_addr, &edma_channel))
  416. ;
  417. qedma3_stop(edma3_base_addr, &edma_channel);
  418. }
  419. }
  420. void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
  421. void *dst, u8 val, size_t len)
  422. {
  423. int xfer_len;
  424. int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535;
  425. memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer));
  426. while (len) {
  427. xfer_len = len;
  428. if (xfer_len > max_xfer)
  429. xfer_len = max_xfer;
  430. __edma3_transfer(edma3_base_addr, edma_slot_num, dst,
  431. edma_fill_buffer, xfer_len,
  432. EDMA_FILL_BUFFER_SIZE);
  433. len -= xfer_len;
  434. dst += xfer_len;
  435. }
  436. }
  437. #ifndef CONFIG_DMA
  438. void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
  439. void *dst, void *src, size_t len)
  440. {
  441. __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len);
  442. }
  443. void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
  444. void *dst, u8 val, size_t len)
  445. {
  446. __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len);
  447. }
  448. #else
  449. static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst,
  450. void *src, size_t len)
  451. {
  452. struct ti_edma3_priv *priv = dev_get_priv(dev);
  453. /* enable edma3 clocks */
  454. enable_edma3_clocks();
  455. switch (direction) {
  456. case DMA_MEM_TO_MEM:
  457. __edma3_transfer(priv->base, 1, dst, src, len, len);
  458. break;
  459. default:
  460. pr_err("Transfer type not implemented in DMA driver\n");
  461. break;
  462. }
  463. /* disable edma3 clocks */
  464. disable_edma3_clocks();
  465. return 0;
  466. }
  467. static int ti_edma3_ofdata_to_platdata(struct udevice *dev)
  468. {
  469. struct ti_edma3_priv *priv = dev_get_priv(dev);
  470. priv->base = devfdt_get_addr(dev);
  471. return 0;
  472. }
  473. static int ti_edma3_probe(struct udevice *dev)
  474. {
  475. struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  476. uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM;
  477. return 0;
  478. }
  479. static const struct dma_ops ti_edma3_ops = {
  480. .transfer = ti_edma3_transfer,
  481. };
  482. static const struct udevice_id ti_edma3_ids[] = {
  483. { .compatible = "ti,edma3" },
  484. { }
  485. };
  486. U_BOOT_DRIVER(ti_edma3) = {
  487. .name = "ti_edma3",
  488. .id = UCLASS_DMA,
  489. .of_match = ti_edma3_ids,
  490. .ops = &ti_edma3_ops,
  491. .ofdata_to_platdata = ti_edma3_ofdata_to_platdata,
  492. .probe = ti_edma3_probe,
  493. .priv_auto_alloc_size = sizeof(struct ti_edma3_priv),
  494. };
  495. #endif /* CONFIG_DMA */