common.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * K3: Common Architecture initialization
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <image.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <spl.h>
  14. #include <asm/global_data.h>
  15. #include "common.h"
  16. #include <dm.h>
  17. #include <remoteproc.h>
  18. #include <asm/cache.h>
  19. #include <linux/soc/ti/ti_sci_protocol.h>
  20. #include <fdt_support.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/hardware.h>
  23. #include <asm/io.h>
  24. #include <fs_loader.h>
  25. #include <fs.h>
  26. #include <env.h>
  27. #include <elf.h>
  28. #include <soc.h>
  29. #if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
  30. enum {
  31. IMAGE_ID_ATF,
  32. IMAGE_ID_OPTEE,
  33. IMAGE_ID_SPL,
  34. IMAGE_ID_DM_FW,
  35. IMAGE_AMT,
  36. };
  37. #if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
  38. static const char *image_os_match[IMAGE_AMT] = {
  39. "arm-trusted-firmware",
  40. "tee",
  41. "U-Boot",
  42. "DM",
  43. };
  44. #endif
  45. static struct image_info fit_image_info[IMAGE_AMT];
  46. #endif
  47. struct ti_sci_handle *get_ti_sci_handle(void)
  48. {
  49. struct udevice *dev;
  50. int ret;
  51. ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
  52. DM_DRIVER_GET(ti_sci), &dev);
  53. if (ret)
  54. panic("Failed to get SYSFW (%d)\n", ret);
  55. return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
  56. }
  57. void k3_sysfw_print_ver(void)
  58. {
  59. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  60. char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
  61. /*
  62. * Output System Firmware version info. Note that since the
  63. * 'firmware_description' field is not guaranteed to be zero-
  64. * terminated we manually add a \0 terminator if needed. Further
  65. * note that we intentionally no longer rely on the extended
  66. * printf() formatter '%.*s' to not having to require a more
  67. * full-featured printf() implementation.
  68. */
  69. strncpy(fw_desc, ti_sci->version.firmware_description,
  70. sizeof(ti_sci->version.firmware_description));
  71. fw_desc[sizeof(fw_desc) - 1] = '\0';
  72. printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
  73. ti_sci->version.abi_major, ti_sci->version.abi_minor,
  74. ti_sci->version.firmware_revision, fw_desc);
  75. }
  76. void mmr_unlock(phys_addr_t base, u32 partition)
  77. {
  78. /* Translate the base address */
  79. phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
  80. /* Unlock the requested partition if locked using two-step sequence */
  81. writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
  82. writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
  83. }
  84. bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data)
  85. {
  86. if (strncmp(data->header, K3_ROM_BOOT_HEADER_MAGIC, 7))
  87. return false;
  88. return data->num_components > 1;
  89. }
  90. DECLARE_GLOBAL_DATA_PTR;
  91. #ifdef CONFIG_K3_EARLY_CONS
  92. int early_console_init(void)
  93. {
  94. struct udevice *dev;
  95. int ret;
  96. gd->baudrate = CONFIG_BAUDRATE;
  97. ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
  98. &dev);
  99. if (ret) {
  100. printf("Error getting serial dev for early console! (%d)\n",
  101. ret);
  102. return ret;
  103. }
  104. gd->cur_serial_dev = dev;
  105. gd->flags |= GD_FLG_SERIAL_READY;
  106. gd->have_console = 1;
  107. return 0;
  108. }
  109. #endif
  110. #if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
  111. void init_env(void)
  112. {
  113. #ifdef CONFIG_SPL_ENV_SUPPORT
  114. char *part;
  115. env_init();
  116. env_relocate();
  117. switch (spl_boot_device()) {
  118. case BOOT_DEVICE_MMC2:
  119. part = env_get("bootpart");
  120. env_set("storage_interface", "mmc");
  121. env_set("fw_dev_part", part);
  122. break;
  123. case BOOT_DEVICE_SPI:
  124. env_set("storage_interface", "ubi");
  125. env_set("fw_ubi_mtdpart", "UBI");
  126. env_set("fw_ubi_volume", "UBI0");
  127. break;
  128. default:
  129. printf("%s from device %u not supported!\n",
  130. __func__, spl_boot_device());
  131. return;
  132. }
  133. #endif
  134. }
  135. #ifdef CONFIG_FS_LOADER
  136. int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
  137. {
  138. struct udevice *fsdev;
  139. char *name = NULL;
  140. int size = 0;
  141. *loadaddr = 0;
  142. #ifdef CONFIG_SPL_ENV_SUPPORT
  143. switch (spl_boot_device()) {
  144. case BOOT_DEVICE_MMC2:
  145. name = env_get(name_fw);
  146. *loadaddr = env_get_hex(name_loadaddr, *loadaddr);
  147. break;
  148. default:
  149. printf("Loading rproc fw image from device %u not supported!\n",
  150. spl_boot_device());
  151. return 0;
  152. }
  153. #endif
  154. if (!*loadaddr)
  155. return 0;
  156. if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
  157. size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr,
  158. 0, 0);
  159. }
  160. return size;
  161. }
  162. #else
  163. int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
  164. {
  165. return 0;
  166. }
  167. #endif
  168. __weak void release_resources_for_core_shutdown(void)
  169. {
  170. debug("%s not implemented...\n", __func__);
  171. }
  172. void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
  173. {
  174. typedef void __noreturn (*image_entry_noargs_t)(void);
  175. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  176. u32 loadaddr = 0;
  177. int ret, size = 0, shut_cpu = 0;
  178. /* Release all the exclusive devices held by SPL before starting ATF */
  179. ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
  180. ret = rproc_init();
  181. if (ret)
  182. panic("rproc failed to be initialized (%d)\n", ret);
  183. init_env();
  184. if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
  185. size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
  186. &loadaddr);
  187. }
  188. /*
  189. * It is assumed that remoteproc device 1 is the corresponding
  190. * Cortex-A core which runs ATF. Make sure DT reflects the same.
  191. */
  192. if (!fit_image_info[IMAGE_ID_ATF].image_start)
  193. fit_image_info[IMAGE_ID_ATF].image_start =
  194. spl_image->entry_point;
  195. ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
  196. if (ret)
  197. panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
  198. if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
  199. !(size > 0 && valid_elf_image(loadaddr))) {
  200. shut_cpu = 1;
  201. goto start_arm64;
  202. }
  203. if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
  204. loadaddr = load_elf_image_phdr(loadaddr);
  205. } else {
  206. loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
  207. if (valid_elf_image(loadaddr))
  208. loadaddr = load_elf_image_phdr(loadaddr);
  209. }
  210. debug("%s: jumping to address %x\n", __func__, loadaddr);
  211. start_arm64:
  212. /* Add an extra newline to differentiate the ATF logs from SPL */
  213. printf("Starting ATF on ARM64 core...\n\n");
  214. ret = rproc_start(1);
  215. if (ret)
  216. panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
  217. if (shut_cpu) {
  218. debug("Shutting down...\n");
  219. release_resources_for_core_shutdown();
  220. while (1)
  221. asm volatile("wfe");
  222. }
  223. image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
  224. image_entry();
  225. }
  226. #endif
  227. #if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
  228. void board_fit_image_post_process(const void *fit, int node, void **p_image,
  229. size_t *p_size)
  230. {
  231. #if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
  232. int len;
  233. int i;
  234. const char *os;
  235. u32 addr;
  236. os = fdt_getprop(fit, node, "os", &len);
  237. addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
  238. debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
  239. addr, *p_size, os);
  240. for (i = 0; i < IMAGE_AMT; i++) {
  241. if (!strcmp(os, image_os_match[i])) {
  242. fit_image_info[i].image_start = addr;
  243. fit_image_info[i].image_len = *p_size;
  244. debug("%s: matched image for ID %d\n", __func__, i);
  245. break;
  246. }
  247. }
  248. #endif
  249. #if IS_ENABLED(CONFIG_TI_SECURE_DEVICE)
  250. ti_secure_image_post_process(p_image, p_size);
  251. #endif
  252. }
  253. #endif
  254. #if defined(CONFIG_OF_LIBFDT)
  255. int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
  256. {
  257. u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
  258. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  259. int ret, node, subnode, len, prev_node;
  260. u32 range[4], addr, size;
  261. const fdt32_t *sub_reg;
  262. ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
  263. msmc_size = msmc_end - msmc_start + 1;
  264. debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
  265. msmc_start, msmc_size);
  266. /* find or create "msmc_sram node */
  267. ret = fdt_path_offset(blob, parent_path);
  268. if (ret < 0)
  269. return ret;
  270. node = fdt_find_or_add_subnode(blob, ret, node_name);
  271. if (node < 0)
  272. return node;
  273. ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
  274. if (ret < 0)
  275. return ret;
  276. reg[0] = cpu_to_fdt64(msmc_start);
  277. reg[1] = cpu_to_fdt64(msmc_size);
  278. ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
  279. if (ret < 0)
  280. return ret;
  281. fdt_setprop_cell(blob, node, "#address-cells", 1);
  282. fdt_setprop_cell(blob, node, "#size-cells", 1);
  283. range[0] = 0;
  284. range[1] = cpu_to_fdt32(msmc_start >> 32);
  285. range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
  286. range[3] = cpu_to_fdt32(msmc_size);
  287. ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
  288. if (ret < 0)
  289. return ret;
  290. subnode = fdt_first_subnode(blob, node);
  291. prev_node = 0;
  292. /* Look for invalid subnodes and delete them */
  293. while (subnode >= 0) {
  294. sub_reg = fdt_getprop(blob, subnode, "reg", &len);
  295. addr = fdt_read_number(sub_reg, 1);
  296. sub_reg++;
  297. size = fdt_read_number(sub_reg, 1);
  298. debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
  299. subnode, addr, size);
  300. if (addr + size > msmc_size ||
  301. !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
  302. !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
  303. fdt_del_node(blob, subnode);
  304. debug("%s: deleting subnode %d\n", __func__, subnode);
  305. if (!prev_node)
  306. subnode = fdt_first_subnode(blob, node);
  307. else
  308. subnode = fdt_next_subnode(blob, prev_node);
  309. } else {
  310. prev_node = subnode;
  311. subnode = fdt_next_subnode(blob, prev_node);
  312. }
  313. }
  314. return 0;
  315. }
  316. int fdt_disable_node(void *blob, char *node_path)
  317. {
  318. int offs;
  319. int ret;
  320. offs = fdt_path_offset(blob, node_path);
  321. if (offs < 0) {
  322. printf("Node %s not found.\n", node_path);
  323. return offs;
  324. }
  325. ret = fdt_setprop_string(blob, offs, "status", "disabled");
  326. if (ret < 0) {
  327. printf("Could not add status property to node %s: %s\n",
  328. node_path, fdt_strerror(ret));
  329. return ret;
  330. }
  331. return 0;
  332. }
  333. #endif
  334. #ifndef CONFIG_SYSRESET
  335. void reset_cpu(void)
  336. {
  337. }
  338. #endif
  339. #if defined(CONFIG_DISPLAY_CPUINFO)
  340. int print_cpuinfo(void)
  341. {
  342. struct udevice *soc;
  343. char name[64];
  344. int ret;
  345. printf("SoC: ");
  346. ret = soc_get(&soc);
  347. if (ret) {
  348. printf("UNKNOWN\n");
  349. return 0;
  350. }
  351. ret = soc_get_family(soc, name, 64);
  352. if (!ret) {
  353. printf("%s ", name);
  354. }
  355. ret = soc_get_revision(soc, name, 64);
  356. if (!ret) {
  357. printf("%s\n", name);
  358. }
  359. return 0;
  360. }
  361. #endif
  362. bool soc_is_j721e(void)
  363. {
  364. u32 soc;
  365. soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
  366. JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
  367. return soc == J721E;
  368. }
  369. bool soc_is_j7200(void)
  370. {
  371. u32 soc;
  372. soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
  373. JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
  374. return soc == J7200;
  375. }
  376. #ifdef CONFIG_ARM64
  377. void board_prep_linux(bootm_headers_t *images)
  378. {
  379. debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
  380. images->os.start, images->os.end);
  381. __asm_flush_dcache_range(images->os.start,
  382. ROUND(images->os.end,
  383. CONFIG_SYS_CACHELINE_SIZE));
  384. }
  385. #endif
  386. #ifdef CONFIG_CPU_V7R
  387. void disable_linefill_optimization(void)
  388. {
  389. u32 actlr;
  390. /*
  391. * On K3 devices there are 2 conditions where R5F can deadlock:
  392. * 1.When software is performing series of store operations to
  393. * cacheable write back/write allocate memory region and later
  394. * on software execute barrier operation (DSB or DMB). R5F may
  395. * hang at the barrier instruction.
  396. * 2.When software is performing a mix of load and store operations
  397. * within a tight loop and store operations are all writing to
  398. * cacheable write back/write allocates memory regions, R5F may
  399. * hang at one of the load instruction.
  400. *
  401. * To avoid the above two conditions disable linefill optimization
  402. * inside Cortex R5F.
  403. */
  404. asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
  405. actlr |= (1 << 13); /* Set DLFO bit */
  406. asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
  407. }
  408. #endif
  409. void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
  410. {
  411. struct ti_sci_msg_fwl_region region;
  412. struct ti_sci_fwl_ops *fwl_ops;
  413. struct ti_sci_handle *ti_sci;
  414. size_t i, j;
  415. ti_sci = get_ti_sci_handle();
  416. fwl_ops = &ti_sci->ops.fwl_ops;
  417. for (i = 0; i < fwl_data_size; i++) {
  418. for (j = 0; j < fwl_data[i].regions; j++) {
  419. region.fwl_id = fwl_data[i].fwl_id;
  420. region.region = j;
  421. region.n_permission_regs = 3;
  422. fwl_ops->get_fwl_region(ti_sci, &region);
  423. if (region.control != 0) {
  424. pr_debug("Attempting to disable firewall %5d (%25s)\n",
  425. region.fwl_id, fwl_data[i].name);
  426. region.control = 0;
  427. if (fwl_ops->set_fwl_region(ti_sci, &region))
  428. pr_err("Could not disable firewall %5d (%25s)\n",
  429. region.fwl_id, fwl_data[i].name);
  430. }
  431. }
  432. }
  433. }
  434. void spl_enable_dcache(void)
  435. {
  436. #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  437. phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
  438. dram_init_banksize();
  439. /* reserve TLB table */
  440. gd->arch.tlb_size = PGTABLE_SIZE;
  441. ram_top += get_effective_memsize();
  442. /* keep ram_top in the 32-bit address space */
  443. if (ram_top >= 0x100000000)
  444. ram_top = (phys_addr_t) 0x100000000;
  445. gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
  446. debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  447. gd->arch.tlb_addr + gd->arch.tlb_size);
  448. dcache_enable();
  449. #endif
  450. }
  451. #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  452. void spl_board_prepare_for_boot(void)
  453. {
  454. dcache_disable();
  455. }
  456. void spl_board_prepare_for_linux(void)
  457. {
  458. dcache_disable();
  459. }
  460. #endif