T4240RDB.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020-2021 NXP
  5. */
  6. /*
  7. * T4240 RDB board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include <linux/stringify.h>
  12. #define CONFIG_FSL_SATA_V2
  13. #define CONFIG_PCIE4
  14. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  15. #ifdef CONFIG_RAMBOOT_PBL
  16. #ifndef CONFIG_SDCARD
  17. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  18. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  19. #else
  20. #define CONFIG_SPL_FLUSH_IMAGE
  21. #define CONFIG_SPL_PAD_TO 0x40000
  22. #define CONFIG_SPL_MAX_SIZE 0x28000
  23. #define RESET_VECTOR_OFFSET 0x27FFC
  24. #define BOOT_PAGE_OFFSET 0x27000
  25. #ifdef CONFIG_SDCARD
  26. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  27. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  28. #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
  29. #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
  30. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  31. #ifndef CONFIG_SPL_BUILD
  32. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  33. #endif
  34. #endif
  35. #ifdef CONFIG_SPL_BUILD
  36. #define CONFIG_SPL_SKIP_RELOCATE
  37. #define CONFIG_SPL_COMMON_INIT_DDR
  38. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  39. #endif
  40. #endif
  41. #endif /* CONFIG_RAMBOOT_PBL */
  42. /* High Level Configuration Options */
  43. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  44. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  45. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  46. #endif
  47. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  48. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  49. #define CONFIG_PCIE1 /* PCIE controller 1 */
  50. #define CONFIG_PCIE2 /* PCIE controller 2 */
  51. #define CONFIG_PCIE3 /* PCIE controller 3 */
  52. /*
  53. * These can be toggled for performance analysis, otherwise use default.
  54. */
  55. #define CONFIG_SYS_CACHE_STASHING
  56. #define CONFIG_BTB /* toggle branch predition */
  57. #ifdef CONFIG_DDR_ECC
  58. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  59. #endif
  60. #define CONFIG_ENABLE_36BIT_PHYS
  61. /*
  62. * Config the L3 Cache as L3 SRAM
  63. */
  64. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  65. #define CONFIG_SYS_L3_SIZE (512 << 10)
  66. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  67. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  68. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  69. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  70. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  71. #define CONFIG_SYS_DCSRBAR 0xf0000000
  72. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  73. /*
  74. * DDR Setup
  75. */
  76. #define CONFIG_VERY_BIG_RAM
  77. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  78. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  79. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  80. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  81. /*
  82. * IFC Definitions
  83. */
  84. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  85. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  86. #ifdef CONFIG_SPL_BUILD
  87. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  88. #else
  89. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  90. #endif
  91. #define CONFIG_HWCONFIG
  92. /* define to use L1 as initial stack */
  93. #define CONFIG_L1_INIT_RAM
  94. #define CONFIG_SYS_INIT_RAM_LOCK
  95. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  96. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  97. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  98. /* The assembler doesn't like typecast */
  99. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  100. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  101. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  102. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  103. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  104. GENERATED_GBL_DATA_SIZE)
  105. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  106. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  107. /* Serial Port - controlled on board with jumper J8
  108. * open - index 2
  109. * shorted - index 1
  110. */
  111. #define CONFIG_SYS_NS16550_SERIAL
  112. #define CONFIG_SYS_NS16550_REG_SIZE 1
  113. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  114. #define CONFIG_SYS_BAUDRATE_TABLE \
  115. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  116. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  117. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  118. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  119. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  120. /* I2C */
  121. /*
  122. * General PCI
  123. * Memory space is mapped 1-1, but I/O space must start from 0.
  124. */
  125. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  126. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  127. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  128. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  129. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  130. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  131. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  132. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  133. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  134. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  135. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  136. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  137. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  138. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  139. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  140. /* controller 4, Base address 203000 */
  141. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  142. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  143. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  144. #ifdef CONFIG_PCI
  145. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  146. #endif /* CONFIG_PCI */
  147. /* SATA */
  148. #ifdef CONFIG_FSL_SATA_V2
  149. #define CONFIG_SATA1
  150. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  151. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  152. #define CONFIG_SATA2
  153. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  154. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  155. #define CONFIG_LBA48
  156. #endif
  157. #ifdef CONFIG_FMAN_ENET
  158. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  159. #endif
  160. /*
  161. * Environment
  162. */
  163. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  164. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  165. /*
  166. * Miscellaneous configurable options
  167. */
  168. /*
  169. * For booting Linux, the board info and command line data
  170. * have to be in the first 64 MB of memory, since this is
  171. * the maximum mapped by the Linux kernel during initialization.
  172. */
  173. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  174. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  175. /*
  176. * Environment Configuration
  177. */
  178. #define CONFIG_ROOTPATH "/opt/nfsroot"
  179. #define CONFIG_BOOTFILE "uImage"
  180. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  181. #define HVBOOT \
  182. "setenv bootargs config-addr=0x60000000; " \
  183. "bootm 0x01000000 - 0x00f00000"
  184. /*
  185. * DDR Setup
  186. */
  187. #define CONFIG_SYS_SPD_BUS_NUM 0
  188. #define SPD_EEPROM_ADDRESS1 0x52
  189. #define SPD_EEPROM_ADDRESS2 0x54
  190. #define SPD_EEPROM_ADDRESS3 0x56
  191. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
  192. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  193. /*
  194. * IFC Definitions
  195. */
  196. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  197. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  198. + 0x8000000) | \
  199. CSPR_PORT_SIZE_16 | \
  200. CSPR_MSEL_NOR | \
  201. CSPR_V)
  202. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  203. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  204. CSPR_PORT_SIZE_16 | \
  205. CSPR_MSEL_NOR | \
  206. CSPR_V)
  207. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  208. /* NOR Flash Timing Params */
  209. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  210. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  211. FTIM0_NOR_TEADC(0x5) | \
  212. FTIM0_NOR_TEAHC(0x5))
  213. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  214. FTIM1_NOR_TRAD_NOR(0x1A) |\
  215. FTIM1_NOR_TSEQRAD_NOR(0x13))
  216. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  217. FTIM2_NOR_TCH(0x4) | \
  218. FTIM2_NOR_TWPH(0x0E) | \
  219. FTIM2_NOR_TWP(0x1c))
  220. #define CONFIG_SYS_NOR_FTIM3 0x0
  221. #define CONFIG_SYS_FLASH_QUIET_TEST
  222. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  223. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  224. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  225. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  226. #define CONFIG_SYS_FLASH_EMPTY_INFO
  227. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  228. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  229. /* NAND Flash on IFC */
  230. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  231. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  232. #define CONFIG_SYS_NAND_BASE 0xff800000
  233. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  234. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  235. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  236. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  237. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  238. | CSPR_V)
  239. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  240. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  241. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  242. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  243. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  244. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  245. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  246. | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
  247. /* ONFI NAND Flash mode0 Timing Params */
  248. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  249. FTIM0_NAND_TWP(0x18) | \
  250. FTIM0_NAND_TWCHT(0x07) | \
  251. FTIM0_NAND_TWH(0x0a))
  252. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  253. FTIM1_NAND_TWBE(0x39) | \
  254. FTIM1_NAND_TRR(0x0e) | \
  255. FTIM1_NAND_TRP(0x18))
  256. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  257. FTIM2_NAND_TREH(0x0a) | \
  258. FTIM2_NAND_TWHRE(0x1e))
  259. #define CONFIG_SYS_NAND_FTIM3 0x0
  260. #define CONFIG_SYS_NAND_DDR_LAW 11
  261. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  262. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  263. #if defined(CONFIG_MTD_RAW_NAND)
  264. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  265. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  266. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  267. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  268. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  269. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  270. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  271. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  272. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  273. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
  274. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  275. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  276. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  277. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  278. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  279. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  280. #else
  281. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  282. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  283. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  284. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  285. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  286. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  287. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  288. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  289. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  290. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  291. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  292. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  293. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  294. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  295. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  296. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  297. #endif
  298. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  299. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  300. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  301. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  302. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  303. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  304. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  305. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  306. /* CPLD on IFC */
  307. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  308. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  309. #define CONFIG_SYS_CSPR3_EXT (0xf)
  310. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  311. | CSPR_PORT_SIZE_8 \
  312. | CSPR_MSEL_GPCM \
  313. | CSPR_V)
  314. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  315. #define CONFIG_SYS_CSOR3 0x0
  316. /* CPLD Timing parameters for IFC CS3 */
  317. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  318. FTIM0_GPCM_TEADC(0x0e) | \
  319. FTIM0_GPCM_TEAHC(0x0e))
  320. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  321. FTIM1_GPCM_TRAD(0x1f))
  322. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  323. FTIM2_GPCM_TCH(0x8) | \
  324. FTIM2_GPCM_TWP(0x1f))
  325. #define CONFIG_SYS_CS3_FTIM3 0x0
  326. #if defined(CONFIG_RAMBOOT_PBL)
  327. #define CONFIG_SYS_RAMBOOT
  328. #endif
  329. /* I2C */
  330. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  331. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
  332. #define I2C_MUX_CH_DEFAULT 0x8
  333. #define I2C_MUX_CH_VOL_MONITOR 0xa
  334. #define I2C_MUX_CH_VSC3316_FS 0xc
  335. #define I2C_MUX_CH_VSC3316_BS 0xd
  336. /* Voltage monitor on channel 2*/
  337. #define I2C_VOL_MONITOR_ADDR 0x40
  338. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  339. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  340. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  341. /* The lowest and highest voltage allowed for T4240RDB */
  342. #define VDD_MV_MIN 819
  343. #define VDD_MV_MAX 1212
  344. /*
  345. * eSPI - Enhanced SPI
  346. */
  347. /* Qman/Bman */
  348. #ifndef CONFIG_NOBQFMAN
  349. #define CONFIG_SYS_BMAN_NUM_PORTALS 50
  350. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  351. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  352. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  353. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  354. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  355. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  356. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  357. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  358. CONFIG_SYS_BMAN_CENA_SIZE)
  359. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  360. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  361. #define CONFIG_SYS_QMAN_NUM_PORTALS 50
  362. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  363. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  364. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  365. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  366. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  367. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  368. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  369. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  370. CONFIG_SYS_QMAN_CENA_SIZE)
  371. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  372. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  373. #define CONFIG_SYS_DPAA_FMAN
  374. #define CONFIG_SYS_DPAA_PME
  375. #define CONFIG_SYS_PMAN
  376. #define CONFIG_SYS_DPAA_DCE
  377. #define CONFIG_SYS_DPAA_RMAN
  378. #define CONFIG_SYS_INTERLAKEN
  379. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  380. #endif /* CONFIG_NOBQFMAN */
  381. #ifdef CONFIG_SYS_DPAA_FMAN
  382. #define SGMII_PHY_ADDR1 0x0
  383. #define SGMII_PHY_ADDR2 0x1
  384. #define SGMII_PHY_ADDR3 0x2
  385. #define SGMII_PHY_ADDR4 0x3
  386. #define SGMII_PHY_ADDR5 0x4
  387. #define SGMII_PHY_ADDR6 0x5
  388. #define SGMII_PHY_ADDR7 0x6
  389. #define SGMII_PHY_ADDR8 0x7
  390. #define FM1_10GEC1_PHY_ADDR 0x10
  391. #define FM1_10GEC2_PHY_ADDR 0x11
  392. #define FM2_10GEC1_PHY_ADDR 0x12
  393. #define FM2_10GEC2_PHY_ADDR 0x13
  394. #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
  395. #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
  396. #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
  397. #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
  398. #endif
  399. /* SATA */
  400. #ifdef CONFIG_FSL_SATA_V2
  401. #define CONFIG_SATA1
  402. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  403. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  404. #define CONFIG_SATA2
  405. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  406. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  407. #define CONFIG_LBA48
  408. #endif
  409. #ifdef CONFIG_FMAN_ENET
  410. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  411. #endif
  412. /*
  413. * USB
  414. */
  415. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  416. #define CONFIG_HAS_FSL_DR_USB
  417. #ifdef CONFIG_MMC
  418. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  419. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  420. #endif
  421. #define __USB_PHY_TYPE utmi
  422. /*
  423. * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
  424. * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
  425. * interleaving. It can be cacheline, page, bank, superbank.
  426. * See doc/README.fsl-ddr for details.
  427. */
  428. #ifdef CONFIG_ARCH_T4240
  429. #define CTRL_INTLV_PREFERED 3way_4KB
  430. #else
  431. #define CTRL_INTLV_PREFERED cacheline
  432. #endif
  433. #define CONFIG_EXTRA_ENV_SETTINGS \
  434. "hwconfig=fsl_ddr:" \
  435. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  436. "bank_intlv=auto;" \
  437. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  438. "netdev=eth0\0" \
  439. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  440. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  441. "tftpflash=tftpboot $loadaddr $uboot && " \
  442. "protect off $ubootaddr +$filesize && " \
  443. "erase $ubootaddr +$filesize && " \
  444. "cp.b $loadaddr $ubootaddr $filesize && " \
  445. "protect on $ubootaddr +$filesize && " \
  446. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  447. "consoledev=ttyS0\0" \
  448. "ramdiskaddr=2000000\0" \
  449. "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
  450. "fdtaddr=1e00000\0" \
  451. "fdtfile=t4240rdb/t4240rdb.dtb\0" \
  452. "bdev=sda3\0"
  453. #define HVBOOT \
  454. "setenv bootargs config-addr=0x60000000; " \
  455. "bootm 0x01000000 - 0x00f00000"
  456. #include <asm/fsl_secure_boot.h>
  457. #endif /* __CONFIG_H */