T208xRDB.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020-2021 NXP
  5. */
  6. /*
  7. * T2080 RDB/PCIe board configuration file
  8. */
  9. #ifndef __T2080RDB_H
  10. #define __T2080RDB_H
  11. #include <linux/stringify.h>
  12. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  13. #define CONFIG_FSL_SATA_V2
  14. /* High Level Configuration Options */
  15. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  16. #define CONFIG_ENABLE_36BIT_PHYS
  17. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  18. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  19. #ifdef CONFIG_RAMBOOT_PBL
  20. #define CONFIG_SPL_FLUSH_IMAGE
  21. #define CONFIG_SPL_PAD_TO 0x40000
  22. #define CONFIG_SPL_MAX_SIZE 0x28000
  23. #define RESET_VECTOR_OFFSET 0x27FFC
  24. #define BOOT_PAGE_OFFSET 0x27000
  25. #ifdef CONFIG_SPL_BUILD
  26. #define CONFIG_SPL_SKIP_RELOCATE
  27. #define CONFIG_SPL_COMMON_INIT_DDR
  28. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  29. #endif
  30. #ifdef CONFIG_MTD_RAW_NAND
  31. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  32. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  33. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  34. #endif
  35. #ifdef CONFIG_SPIFLASH
  36. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  37. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  38. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  39. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  40. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  41. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  42. #ifndef CONFIG_SPL_BUILD
  43. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  44. #endif
  45. #endif
  46. #ifdef CONFIG_SDCARD
  47. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  48. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  49. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  50. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  51. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  52. #ifndef CONFIG_SPL_BUILD
  53. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  54. #endif
  55. #endif
  56. #endif /* CONFIG_RAMBOOT_PBL */
  57. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  58. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  59. /* Set 1M boot space */
  60. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  61. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  62. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  63. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  64. #endif
  65. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  66. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  67. #endif
  68. /*
  69. * These can be toggled for performance analysis, otherwise use default.
  70. */
  71. #define CONFIG_SYS_CACHE_STASHING
  72. #define CONFIG_BTB /* toggle branch predition */
  73. #ifdef CONFIG_DDR_ECC
  74. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  75. #endif
  76. /*
  77. * Config the L3 Cache as L3 SRAM
  78. */
  79. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  80. #define CONFIG_SYS_L3_SIZE (512 << 10)
  81. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  82. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  83. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  84. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  85. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  86. #define CONFIG_SYS_DCSRBAR 0xf0000000
  87. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  88. /* EEPROM */
  89. #define CONFIG_SYS_I2C_EEPROM_NXID
  90. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  91. /*
  92. * DDR Setup
  93. */
  94. #define CONFIG_VERY_BIG_RAM
  95. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  96. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  97. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  98. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  99. #define CONFIG_SYS_SPD_BUS_NUM 0
  100. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  101. #define SPD_EEPROM_ADDRESS1 0x51
  102. #define SPD_EEPROM_ADDRESS2 0x52
  103. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  104. #define CTRL_INTLV_PREFERED cacheline
  105. /*
  106. * IFC Definitions
  107. */
  108. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  109. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  110. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  111. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  112. CSPR_PORT_SIZE_16 | \
  113. CSPR_MSEL_NOR | \
  114. CSPR_V)
  115. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  116. /* NOR Flash Timing Params */
  117. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  118. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  119. FTIM0_NOR_TEADC(0x5) | \
  120. FTIM0_NOR_TEAHC(0x5))
  121. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  122. FTIM1_NOR_TRAD_NOR(0x1A) |\
  123. FTIM1_NOR_TSEQRAD_NOR(0x13))
  124. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  125. FTIM2_NOR_TCH(0x4) | \
  126. FTIM2_NOR_TWPH(0x0E) | \
  127. FTIM2_NOR_TWP(0x1c))
  128. #define CONFIG_SYS_NOR_FTIM3 0x0
  129. #define CONFIG_SYS_FLASH_QUIET_TEST
  130. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  131. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  132. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  133. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  134. #define CONFIG_SYS_FLASH_EMPTY_INFO
  135. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
  136. /* CPLD on IFC */
  137. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  138. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  139. #define CONFIG_SYS_CSPR2_EXT (0xf)
  140. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
  141. | CSPR_PORT_SIZE_8 \
  142. | CSPR_MSEL_GPCM \
  143. | CSPR_V)
  144. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  145. #define CONFIG_SYS_CSOR2 0x0
  146. /* CPLD Timing parameters for IFC CS2 */
  147. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  148. FTIM0_GPCM_TEADC(0x0e) | \
  149. FTIM0_GPCM_TEAHC(0x0e))
  150. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  151. FTIM1_GPCM_TRAD(0x1f))
  152. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  153. FTIM2_GPCM_TCH(0x8) | \
  154. FTIM2_GPCM_TWP(0x1f))
  155. #define CONFIG_SYS_CS2_FTIM3 0x0
  156. /* NAND Flash on IFC */
  157. #define CONFIG_SYS_NAND_BASE 0xff800000
  158. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  159. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  160. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  161. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  162. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  163. | CSPR_V)
  164. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  165. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  166. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  167. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  168. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  169. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  170. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  171. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  172. /* ONFI NAND Flash mode0 Timing Params */
  173. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  174. FTIM0_NAND_TWP(0x18) | \
  175. FTIM0_NAND_TWCHT(0x07) | \
  176. FTIM0_NAND_TWH(0x0a))
  177. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  178. FTIM1_NAND_TWBE(0x39) | \
  179. FTIM1_NAND_TRR(0x0e) | \
  180. FTIM1_NAND_TRP(0x18))
  181. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  182. FTIM2_NAND_TREH(0x0a) | \
  183. FTIM2_NAND_TWHRE(0x1e))
  184. #define CONFIG_SYS_NAND_FTIM3 0x0
  185. #define CONFIG_SYS_NAND_DDR_LAW 11
  186. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  187. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  188. #if defined(CONFIG_MTD_RAW_NAND)
  189. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  190. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  191. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  192. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  193. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  194. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  195. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  196. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  197. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  198. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  199. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  200. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  201. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  202. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  203. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  204. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  205. #else
  206. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  207. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  208. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  209. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  210. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  211. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  212. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  213. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  214. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  215. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  216. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  217. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  218. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  219. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  220. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  221. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  222. #endif
  223. #if defined(CONFIG_RAMBOOT_PBL)
  224. #define CONFIG_SYS_RAMBOOT
  225. #endif
  226. #ifdef CONFIG_SPL_BUILD
  227. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  228. #else
  229. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  230. #endif
  231. #define CONFIG_HWCONFIG
  232. /* define to use L1 as initial stack */
  233. #define CONFIG_L1_INIT_RAM
  234. #define CONFIG_SYS_INIT_RAM_LOCK
  235. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  236. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  237. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  238. /* The assembler doesn't like typecast */
  239. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  240. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  241. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  242. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  243. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  244. GENERATED_GBL_DATA_SIZE)
  245. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  246. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  247. /*
  248. * Serial Port
  249. */
  250. #define CONFIG_SYS_NS16550_SERIAL
  251. #define CONFIG_SYS_NS16550_REG_SIZE 1
  252. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  253. #define CONFIG_SYS_BAUDRATE_TABLE \
  254. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  255. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  256. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  257. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  258. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  259. /*
  260. * I2C
  261. */
  262. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  263. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  264. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  265. #define I2C_MUX_CH_DEFAULT 0x8
  266. #define I2C_MUX_CH_VOL_MONITOR 0xa
  267. /* The lowest and highest voltage allowed for T208xRDB */
  268. #define VDD_MV_MIN 819
  269. #define VDD_MV_MAX 1212
  270. /*
  271. * RapidIO
  272. */
  273. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  274. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  275. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  276. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  277. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  278. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  279. /*
  280. * for slave u-boot IMAGE instored in master memory space,
  281. * PHYS must be aligned based on the SIZE
  282. */
  283. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  284. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  285. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  286. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  287. /*
  288. * for slave UCODE and ENV instored in master memory space,
  289. * PHYS must be aligned based on the SIZE
  290. */
  291. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  292. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  293. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  294. /* slave core release by master*/
  295. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  296. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  297. /*
  298. * SRIO_PCIE_BOOT - SLAVE
  299. */
  300. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  301. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  302. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  303. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  304. #endif
  305. /*
  306. * eSPI - Enhanced SPI
  307. */
  308. /*
  309. * General PCI
  310. * Memory space is mapped 1-1, but I/O space must start from 0.
  311. */
  312. #define CONFIG_PCIE1 /* PCIE controller 1 */
  313. #define CONFIG_PCIE2 /* PCIE controller 2 */
  314. #define CONFIG_PCIE3 /* PCIE controller 3 */
  315. #define CONFIG_PCIE4 /* PCIE controller 4 */
  316. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  317. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  318. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  319. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  320. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  321. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  322. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  323. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  324. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  325. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  326. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  327. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  328. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  329. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  330. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  331. /* controller 4, Base address 203000 */
  332. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  333. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  334. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  335. #ifdef CONFIG_PCI
  336. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  337. #endif
  338. /* Qman/Bman */
  339. #ifndef CONFIG_NOBQFMAN
  340. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  341. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  342. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  343. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  344. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  345. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  346. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  347. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  348. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  349. CONFIG_SYS_BMAN_CENA_SIZE)
  350. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  351. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  352. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  353. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  354. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  355. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  356. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  357. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  358. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  359. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  360. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  361. CONFIG_SYS_QMAN_CENA_SIZE)
  362. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  363. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  364. #define CONFIG_SYS_DPAA_FMAN
  365. #define CONFIG_SYS_DPAA_PME
  366. #define CONFIG_SYS_PMAN
  367. #define CONFIG_SYS_DPAA_DCE
  368. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  369. #define CONFIG_SYS_INTERLAKEN
  370. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  371. #endif /* CONFIG_NOBQFMAN */
  372. #ifdef CONFIG_SYS_DPAA_FMAN
  373. #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
  374. #define RGMII_PHY2_ADDR 0x02
  375. #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
  376. #define CORTINA_PHY_ADDR2 0x0d
  377. /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
  378. #define FM1_10GEC3_PHY_ADDR 0x00
  379. #define FM1_10GEC4_PHY_ADDR 0x01
  380. /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
  381. #define AQR113C_PHY_ADDR1 0x00
  382. #define AQR113C_PHY_ADDR2 0x08
  383. #endif
  384. #ifdef CONFIG_FMAN_ENET
  385. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  386. #endif
  387. /*
  388. * SATA
  389. */
  390. #ifdef CONFIG_FSL_SATA_V2
  391. #define CONFIG_SATA1
  392. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  393. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  394. #define CONFIG_SATA2
  395. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  396. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  397. #define CONFIG_LBA48
  398. #endif
  399. /*
  400. * USB
  401. */
  402. #ifdef CONFIG_USB_EHCI_HCD
  403. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  404. #define CONFIG_HAS_FSL_DR_USB
  405. #endif
  406. /*
  407. * SDHC
  408. */
  409. #ifdef CONFIG_MMC
  410. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  411. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  412. #endif
  413. /*
  414. * Dynamic MTD Partition support with mtdparts
  415. */
  416. /*
  417. * Environment
  418. */
  419. /*
  420. * Miscellaneous configurable options
  421. */
  422. /*
  423. * For booting Linux, the board info and command line data
  424. * have to be in the first 64 MB of memory, since this is
  425. * the maximum mapped by the Linux kernel during initialization.
  426. */
  427. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  428. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  429. /*
  430. * Environment Configuration
  431. */
  432. #define CONFIG_ROOTPATH "/opt/nfsroot"
  433. #define CONFIG_BOOTFILE "uImage"
  434. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  435. #define __USB_PHY_TYPE utmi
  436. #define CONFIG_EXTRA_ENV_SETTINGS \
  437. "hwconfig=fsl_ddr:" \
  438. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  439. "bank_intlv=auto;" \
  440. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  441. "netdev=eth0\0" \
  442. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  443. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  444. "tftpflash=tftpboot $loadaddr $uboot && " \
  445. "protect off $ubootaddr +$filesize && " \
  446. "erase $ubootaddr +$filesize && " \
  447. "cp.b $loadaddr $ubootaddr $filesize && " \
  448. "protect on $ubootaddr +$filesize && " \
  449. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  450. "consoledev=ttyS0\0" \
  451. "ramdiskaddr=2000000\0" \
  452. "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
  453. "fdtaddr=1e00000\0" \
  454. "fdtfile=t2080rdb/t2080rdb.dtb\0" \
  455. "bdev=sda3\0"
  456. /*
  457. * For emulation this causes u-boot to jump to the start of the
  458. * proof point app code automatically
  459. */
  460. #define PROOF_POINTS \
  461. "setenv bootargs root=/dev/$bdev rw " \
  462. "console=$consoledev,$baudrate $othbootargs;" \
  463. "cpu 1 release 0x29000000 - - -;" \
  464. "cpu 2 release 0x29000000 - - -;" \
  465. "cpu 3 release 0x29000000 - - -;" \
  466. "cpu 4 release 0x29000000 - - -;" \
  467. "cpu 5 release 0x29000000 - - -;" \
  468. "cpu 6 release 0x29000000 - - -;" \
  469. "cpu 7 release 0x29000000 - - -;" \
  470. "go 0x29000000"
  471. #define HVBOOT \
  472. "setenv bootargs config-addr=0x60000000; " \
  473. "bootm 0x01000000 - 0x00f00000"
  474. #define ALU \
  475. "setenv bootargs root=/dev/$bdev rw " \
  476. "console=$consoledev,$baudrate $othbootargs;" \
  477. "cpu 1 release 0x01000000 - - -;" \
  478. "cpu 2 release 0x01000000 - - -;" \
  479. "cpu 3 release 0x01000000 - - -;" \
  480. "cpu 4 release 0x01000000 - - -;" \
  481. "cpu 5 release 0x01000000 - - -;" \
  482. "cpu 6 release 0x01000000 - - -;" \
  483. "cpu 7 release 0x01000000 - - -;" \
  484. "go 0x01000000"
  485. #include <asm/fsl_secure_boot.h>
  486. #endif /* __T2080RDB_H */