T208xQDS.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2013 Freescale Semiconductor, Inc.
  4. * Copyright 2020-2021 NXP
  5. */
  6. /*
  7. * T2080/T2081 QDS board configuration file
  8. */
  9. #ifndef __T208xQDS_H
  10. #define __T208xQDS_H
  11. #include <linux/stringify.h>
  12. #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  13. #if defined(CONFIG_ARCH_T2080)
  14. #define CONFIG_FSL_SATA_V2
  15. #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
  16. #define CONFIG_SRIO1 /* SRIO port 1 */
  17. #define CONFIG_SRIO2 /* SRIO port 2 */
  18. #endif
  19. /* High Level Configuration Options */
  20. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  21. #define CONFIG_ENABLE_36BIT_PHYS
  22. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  23. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  24. #ifdef CONFIG_RAMBOOT_PBL
  25. #define CONFIG_SPL_FLUSH_IMAGE
  26. #define CONFIG_SPL_PAD_TO 0x40000
  27. #define CONFIG_SPL_MAX_SIZE 0x28000
  28. #define RESET_VECTOR_OFFSET 0x27FFC
  29. #define BOOT_PAGE_OFFSET 0x27000
  30. #ifdef CONFIG_SPL_BUILD
  31. #define CONFIG_SPL_SKIP_RELOCATE
  32. #define CONFIG_SPL_COMMON_INIT_DDR
  33. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  34. #endif
  35. #ifdef CONFIG_MTD_RAW_NAND
  36. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  37. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
  38. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  39. #endif
  40. #ifdef CONFIG_SPIFLASH
  41. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  42. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  43. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  44. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
  45. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
  46. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  47. #ifndef CONFIG_SPL_BUILD
  48. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  49. #endif
  50. #endif
  51. #ifdef CONFIG_SDCARD
  52. #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  53. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  54. #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
  55. #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
  56. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  57. #ifndef CONFIG_SPL_BUILD
  58. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  59. #endif
  60. #endif
  61. #endif /* CONFIG_RAMBOOT_PBL */
  62. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  63. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  64. /* Set 1M boot space */
  65. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  66. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  67. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  68. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  69. #endif
  70. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  71. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  72. #endif
  73. /*
  74. * These can be toggled for performance analysis, otherwise use default.
  75. */
  76. #define CONFIG_SYS_CACHE_STASHING
  77. #define CONFIG_BTB /* toggle branch predition */
  78. #ifdef CONFIG_DDR_ECC
  79. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  80. #endif
  81. /*
  82. * Config the L3 Cache as L3 SRAM
  83. */
  84. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  85. #define CONFIG_SYS_L3_SIZE (512 << 10)
  86. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  87. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  88. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  89. #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  90. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  91. #define CONFIG_SYS_DCSRBAR 0xf0000000
  92. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  93. /* EEPROM */
  94. #define CONFIG_SYS_I2C_EEPROM_NXID
  95. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  96. /*
  97. * DDR Setup
  98. */
  99. #define CONFIG_VERY_BIG_RAM
  100. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  101. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  102. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  103. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  104. #define CONFIG_SYS_SPD_BUS_NUM 0
  105. #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  106. #define SPD_EEPROM_ADDRESS1 0x51
  107. #define SPD_EEPROM_ADDRESS2 0x52
  108. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  109. #define CTRL_INTLV_PREFERED cacheline
  110. /*
  111. * IFC Definitions
  112. */
  113. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  114. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  115. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  116. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  117. + 0x8000000) | \
  118. CSPR_PORT_SIZE_16 | \
  119. CSPR_MSEL_NOR | \
  120. CSPR_V)
  121. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  122. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  123. CSPR_PORT_SIZE_16 | \
  124. CSPR_MSEL_NOR | \
  125. CSPR_V)
  126. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  127. /* NOR Flash Timing Params */
  128. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  129. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  130. FTIM0_NOR_TEADC(0x5) | \
  131. FTIM0_NOR_TEAHC(0x5))
  132. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  133. FTIM1_NOR_TRAD_NOR(0x1A) |\
  134. FTIM1_NOR_TSEQRAD_NOR(0x13))
  135. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  136. FTIM2_NOR_TCH(0x4) | \
  137. FTIM2_NOR_TWPH(0x0E) | \
  138. FTIM2_NOR_TWP(0x1c))
  139. #define CONFIG_SYS_NOR_FTIM3 0x0
  140. #define CONFIG_SYS_FLASH_QUIET_TEST
  141. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  142. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  143. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  144. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  145. #define CONFIG_SYS_FLASH_EMPTY_INFO
  146. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  147. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  148. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  149. #define QIXIS_BASE 0xffdf0000
  150. #define QIXIS_LBMAP_SWITCH 6
  151. #define QIXIS_LBMAP_MASK 0x0f
  152. #define QIXIS_LBMAP_SHIFT 0
  153. #define QIXIS_LBMAP_DFLTBANK 0x00
  154. #define QIXIS_LBMAP_ALTBANK 0x04
  155. #define QIXIS_LBMAP_NAND 0x09
  156. #define QIXIS_LBMAP_SD 0x00
  157. #define QIXIS_RCW_SRC_NAND 0x104
  158. #define QIXIS_RCW_SRC_SD 0x040
  159. #define QIXIS_RST_CTL_RESET 0x83
  160. #define QIXIS_RST_FORCE_MEM 0x1
  161. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  162. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  163. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  164. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  165. #define CONFIG_SYS_CSPR3_EXT (0xf)
  166. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  167. | CSPR_PORT_SIZE_8 \
  168. | CSPR_MSEL_GPCM \
  169. | CSPR_V)
  170. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  171. #define CONFIG_SYS_CSOR3 0x0
  172. /* QIXIS Timing parameters for IFC CS3 */
  173. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  174. FTIM0_GPCM_TEADC(0x0e) | \
  175. FTIM0_GPCM_TEAHC(0x0e))
  176. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  177. FTIM1_GPCM_TRAD(0x3f))
  178. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  179. FTIM2_GPCM_TCH(0x8) | \
  180. FTIM2_GPCM_TWP(0x1f))
  181. #define CONFIG_SYS_CS3_FTIM3 0x0
  182. /* NAND Flash on IFC */
  183. #define CONFIG_SYS_NAND_BASE 0xff800000
  184. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  185. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  186. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  187. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  188. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  189. | CSPR_V)
  190. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  191. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  192. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  193. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  194. | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  195. | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  196. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  197. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  198. /* ONFI NAND Flash mode0 Timing Params */
  199. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  200. FTIM0_NAND_TWP(0x18) | \
  201. FTIM0_NAND_TWCHT(0x07) | \
  202. FTIM0_NAND_TWH(0x0a))
  203. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  204. FTIM1_NAND_TWBE(0x39) | \
  205. FTIM1_NAND_TRR(0x0e) | \
  206. FTIM1_NAND_TRP(0x18))
  207. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  208. FTIM2_NAND_TREH(0x0a) | \
  209. FTIM2_NAND_TWHRE(0x1e))
  210. #define CONFIG_SYS_NAND_FTIM3 0x0
  211. #define CONFIG_SYS_NAND_DDR_LAW 11
  212. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  213. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  214. #if defined(CONFIG_MTD_RAW_NAND)
  215. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  216. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  217. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  218. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  219. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  220. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  221. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  222. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  223. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  224. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  225. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  226. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  227. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  228. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  229. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  230. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  231. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  232. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  233. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  234. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  235. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  236. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  237. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  238. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  239. #else
  240. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  241. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  242. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  243. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  244. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  245. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  246. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  247. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  248. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  249. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  250. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  251. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  252. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  253. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  254. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  255. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  256. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  257. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  258. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  259. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  260. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  261. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  262. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  263. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  264. #endif
  265. #if defined(CONFIG_RAMBOOT_PBL)
  266. #define CONFIG_SYS_RAMBOOT
  267. #endif
  268. #ifdef CONFIG_SPL_BUILD
  269. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  270. #else
  271. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  272. #endif
  273. #define CONFIG_HWCONFIG
  274. /* define to use L1 as initial stack */
  275. #define CONFIG_L1_INIT_RAM
  276. #define CONFIG_SYS_INIT_RAM_LOCK
  277. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  278. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  279. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  280. /* The assembler doesn't like typecast */
  281. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  282. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  283. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  284. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  285. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  286. GENERATED_GBL_DATA_SIZE)
  287. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  288. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  289. /*
  290. * Serial Port
  291. */
  292. #define CONFIG_SYS_NS16550_SERIAL
  293. #define CONFIG_SYS_NS16550_REG_SIZE 1
  294. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  295. #define CONFIG_SYS_BAUDRATE_TABLE \
  296. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  297. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  298. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  299. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  300. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  301. /*
  302. * I2C
  303. */
  304. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  305. #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  306. #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  307. #define I2C_MUX_CH_DEFAULT 0x8
  308. #define I2C_MUX_CH_VOL_MONITOR 0xa
  309. /* Voltage monitor on channel 2*/
  310. #define I2C_VOL_MONITOR_ADDR 0x40
  311. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  312. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  313. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  314. /* The lowest and highest voltage allowed for T208xQDS */
  315. #define VDD_MV_MIN 819
  316. #define VDD_MV_MAX 1212
  317. /*
  318. * RapidIO
  319. */
  320. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  321. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  322. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  323. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  324. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  325. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  326. /*
  327. * for slave u-boot IMAGE instored in master memory space,
  328. * PHYS must be aligned based on the SIZE
  329. */
  330. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  331. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  332. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  333. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  334. /*
  335. * for slave UCODE and ENV instored in master memory space,
  336. * PHYS must be aligned based on the SIZE
  337. */
  338. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  339. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  340. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  341. /* slave core release by master*/
  342. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  343. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  344. /*
  345. * SRIO_PCIE_BOOT - SLAVE
  346. */
  347. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  348. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  349. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  350. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  351. #endif
  352. /*
  353. * eSPI - Enhanced SPI
  354. */
  355. /*
  356. * General PCI
  357. * Memory space is mapped 1-1, but I/O space must start from 0.
  358. */
  359. #define CONFIG_PCIE1 /* PCIE controller 1 */
  360. #define CONFIG_PCIE2 /* PCIE controller 2 */
  361. #define CONFIG_PCIE3 /* PCIE controller 3 */
  362. #define CONFIG_PCIE4 /* PCIE controller 4 */
  363. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  364. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  365. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  366. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  367. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  368. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  369. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  370. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  371. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  372. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  373. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  374. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  375. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  376. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  377. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  378. /* controller 4, Base address 203000 */
  379. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  380. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  381. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  382. #ifdef CONFIG_PCI
  383. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  384. #endif
  385. /* Qman/Bman */
  386. #ifndef CONFIG_NOBQFMAN
  387. #define CONFIG_SYS_BMAN_NUM_PORTALS 18
  388. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  389. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  390. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  391. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  392. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  393. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  394. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  395. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  396. CONFIG_SYS_BMAN_CENA_SIZE)
  397. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  398. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  399. #define CONFIG_SYS_QMAN_NUM_PORTALS 18
  400. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  401. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  402. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  403. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  404. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  405. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  406. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  407. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  408. CONFIG_SYS_QMAN_CENA_SIZE)
  409. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  410. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  411. #define CONFIG_SYS_DPAA_FMAN
  412. #define CONFIG_SYS_DPAA_PME
  413. #define CONFIG_SYS_PMAN
  414. #define CONFIG_SYS_DPAA_DCE
  415. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  416. #define CONFIG_SYS_INTERLAKEN
  417. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  418. #endif /* CONFIG_NOBQFMAN */
  419. #ifdef CONFIG_SYS_DPAA_FMAN
  420. #define RGMII_PHY1_ADDR 0x1
  421. #define RGMII_PHY2_ADDR 0x2
  422. #define FM1_10GEC1_PHY_ADDR 0x3
  423. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  424. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  425. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  426. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  427. #endif
  428. #ifdef CONFIG_FMAN_ENET
  429. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  430. #endif
  431. /*
  432. * SATA
  433. */
  434. #ifdef CONFIG_FSL_SATA_V2
  435. #define CONFIG_SATA1
  436. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  437. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  438. #define CONFIG_SATA2
  439. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  440. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  441. #define CONFIG_LBA48
  442. #endif
  443. /*
  444. * USB
  445. */
  446. #ifdef CONFIG_USB_EHCI_HCD
  447. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  448. #define CONFIG_HAS_FSL_DR_USB
  449. #endif
  450. /*
  451. * SDHC
  452. */
  453. #ifdef CONFIG_MMC
  454. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  455. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  456. #endif
  457. /*
  458. * Dynamic MTD Partition support with mtdparts
  459. */
  460. /*
  461. * Environment
  462. */
  463. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  464. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  465. /*
  466. * Miscellaneous configurable options
  467. */
  468. /*
  469. * For booting Linux, the board info and command line data
  470. * have to be in the first 64 MB of memory, since this is
  471. * the maximum mapped by the Linux kernel during initialization.
  472. */
  473. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  474. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  475. /*
  476. * Environment Configuration
  477. */
  478. #define CONFIG_ROOTPATH "/opt/nfsroot"
  479. #define CONFIG_BOOTFILE "uImage"
  480. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  481. #define __USB_PHY_TYPE utmi
  482. #define CONFIG_EXTRA_ENV_SETTINGS \
  483. "hwconfig=fsl_ddr:" \
  484. "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  485. "bank_intlv=auto;" \
  486. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  487. "netdev=eth0\0" \
  488. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  489. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  490. "tftpflash=tftpboot $loadaddr $uboot && " \
  491. "protect off $ubootaddr +$filesize && " \
  492. "erase $ubootaddr +$filesize && " \
  493. "cp.b $loadaddr $ubootaddr $filesize && " \
  494. "protect on $ubootaddr +$filesize && " \
  495. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  496. "consoledev=ttyS0\0" \
  497. "ramdiskaddr=2000000\0" \
  498. "ramdiskfile=t2080qds/ramdisk.uboot\0" \
  499. "fdtaddr=1e00000\0" \
  500. "fdtfile=t2080qds/t2080qds.dtb\0" \
  501. "bdev=sda3\0"
  502. /*
  503. * For emulation this causes u-boot to jump to the start of the
  504. * proof point app code automatically
  505. */
  506. #define PROOF_POINTS \
  507. "setenv bootargs root=/dev/$bdev rw " \
  508. "console=$consoledev,$baudrate $othbootargs;" \
  509. "cpu 1 release 0x29000000 - - -;" \
  510. "cpu 2 release 0x29000000 - - -;" \
  511. "cpu 3 release 0x29000000 - - -;" \
  512. "cpu 4 release 0x29000000 - - -;" \
  513. "cpu 5 release 0x29000000 - - -;" \
  514. "cpu 6 release 0x29000000 - - -;" \
  515. "cpu 7 release 0x29000000 - - -;" \
  516. "go 0x29000000"
  517. #define HVBOOT \
  518. "setenv bootargs config-addr=0x60000000; " \
  519. "bootm 0x01000000 - 0x00f00000"
  520. #define ALU \
  521. "setenv bootargs root=/dev/$bdev rw " \
  522. "console=$consoledev,$baudrate $othbootargs;" \
  523. "cpu 1 release 0x01000000 - - -;" \
  524. "cpu 2 release 0x01000000 - - -;" \
  525. "cpu 3 release 0x01000000 - - -;" \
  526. "cpu 4 release 0x01000000 - - -;" \
  527. "cpu 5 release 0x01000000 - - -;" \
  528. "cpu 6 release 0x01000000 - - -;" \
  529. "cpu 7 release 0x01000000 - - -;" \
  530. "go 0x01000000"
  531. #include <asm/fsl_secure_boot.h>
  532. #endif /* __T208xQDS_H */