T104xRDB.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020-2021 NXP
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #include <linux/stringify.h>
  9. /*
  10. * T104x RDB board configuration file
  11. */
  12. #include <asm/config_mpc85xx.h>
  13. #ifdef CONFIG_RAMBOOT_PBL
  14. #define CONFIG_SPL_FLUSH_IMAGE
  15. #define CONFIG_SPL_PAD_TO 0x40000
  16. #define CONFIG_SPL_MAX_SIZE 0x28000
  17. #ifdef CONFIG_SPL_BUILD
  18. #define CONFIG_SPL_SKIP_RELOCATE
  19. #define CONFIG_SPL_COMMON_INIT_DDR
  20. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  21. #endif
  22. #define RESET_VECTOR_OFFSET 0x27FFC
  23. #define BOOT_PAGE_OFFSET 0x27000
  24. #ifdef CONFIG_MTD_RAW_NAND
  25. #ifdef CONFIG_NXP_ESBC
  26. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  27. /*
  28. * HDR would be appended at end of image and copied to DDR along
  29. * with U-Boot image.
  30. */
  31. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
  32. CONFIG_U_BOOT_HDR_SIZE)
  33. #else
  34. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  35. #endif
  36. #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
  37. #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
  38. #endif
  39. #ifdef CONFIG_SPIFLASH
  40. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  41. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  42. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  43. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
  44. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
  45. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  46. #ifndef CONFIG_SPL_BUILD
  47. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  48. #endif
  49. #endif
  50. #ifdef CONFIG_SDCARD
  51. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  52. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  53. #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
  54. #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
  55. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  56. #ifndef CONFIG_SPL_BUILD
  57. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  58. #endif
  59. #endif
  60. #endif
  61. /* High Level Configuration Options */
  62. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  63. /* support deep sleep */
  64. #define CONFIG_DEEP_SLEEP
  65. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  66. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  67. #endif
  68. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  69. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  70. #define CONFIG_PCIE1 /* PCIE controller 1 */
  71. #define CONFIG_PCIE2 /* PCIE controller 2 */
  72. #define CONFIG_PCIE3 /* PCIE controller 3 */
  73. #define CONFIG_PCIE4 /* PCIE controller 4 */
  74. #if defined(CONFIG_SPIFLASH)
  75. #elif defined(CONFIG_MTD_RAW_NAND)
  76. #ifdef CONFIG_NXP_ESBC
  77. #define CONFIG_RAMBOOT_NAND
  78. #define CONFIG_BOOTSCRIPT_COPY_RAM
  79. #endif
  80. #endif
  81. /*
  82. * These can be toggled for performance analysis, otherwise use default.
  83. */
  84. #define CONFIG_SYS_CACHE_STASHING
  85. #define CONFIG_BACKSIDE_L2_CACHE
  86. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  87. #define CONFIG_BTB /* toggle branch predition */
  88. #ifdef CONFIG_DDR_ECC
  89. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  90. #endif
  91. #define CONFIG_ENABLE_36BIT_PHYS
  92. /*
  93. * Config the L3 Cache as L3 SRAM
  94. */
  95. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  96. /*
  97. * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
  98. * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
  99. * (CONFIG_SYS_INIT_L3_VADDR) will be different.
  100. */
  101. #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
  102. #define CONFIG_SYS_L3_SIZE 256 << 10
  103. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
  104. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  105. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  106. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  107. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  108. #define CONFIG_SYS_DCSRBAR 0xf0000000
  109. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  110. /*
  111. * DDR Setup
  112. */
  113. #define CONFIG_VERY_BIG_RAM
  114. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  115. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  116. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  117. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  118. #define CONFIG_SYS_SPD_BUS_NUM 0
  119. #define SPD_EEPROM_ADDRESS 0x51
  120. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  121. /*
  122. * IFC Definitions
  123. */
  124. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  125. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  126. #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
  127. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
  128. CSPR_PORT_SIZE_16 | \
  129. CSPR_MSEL_NOR | \
  130. CSPR_V)
  131. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  132. /*
  133. * TDM Definition
  134. */
  135. #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
  136. /* NOR Flash Timing Params */
  137. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  138. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  139. FTIM0_NOR_TEADC(0x5) | \
  140. FTIM0_NOR_TEAHC(0x5))
  141. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  142. FTIM1_NOR_TRAD_NOR(0x1A) |\
  143. FTIM1_NOR_TSEQRAD_NOR(0x13))
  144. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  145. FTIM2_NOR_TCH(0x4) | \
  146. FTIM2_NOR_TWPH(0x0E) | \
  147. FTIM2_NOR_TWP(0x1c))
  148. #define CONFIG_SYS_NOR_FTIM3 0x0
  149. #define CONFIG_SYS_FLASH_QUIET_TEST
  150. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  151. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  152. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  153. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  154. #define CONFIG_SYS_FLASH_EMPTY_INFO
  155. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  156. /* CPLD on IFC */
  157. #define CPLD_LBMAP_MASK 0x3F
  158. #define CPLD_BANK_SEL_MASK 0x07
  159. #define CPLD_BANK_OVERRIDE 0x40
  160. #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
  161. #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
  162. #define CPLD_LBMAP_RESET 0xFF
  163. #define CPLD_LBMAP_SHIFT 0x03
  164. #if defined(CONFIG_TARGET_T1042RDB_PI)
  165. #define CPLD_DIU_SEL_DFP 0x80
  166. #elif defined(CONFIG_TARGET_T1042D4RDB)
  167. #define CPLD_DIU_SEL_DFP 0xc0
  168. #endif
  169. #if defined(CONFIG_TARGET_T1040D4RDB)
  170. #define CPLD_INT_MASK_ALL 0xFF
  171. #define CPLD_INT_MASK_THERM 0x80
  172. #define CPLD_INT_MASK_DVI_DFP 0x40
  173. #define CPLD_INT_MASK_QSGMII1 0x20
  174. #define CPLD_INT_MASK_QSGMII2 0x10
  175. #define CPLD_INT_MASK_SGMI1 0x08
  176. #define CPLD_INT_MASK_SGMI2 0x04
  177. #define CPLD_INT_MASK_TDMR1 0x02
  178. #define CPLD_INT_MASK_TDMR2 0x01
  179. #endif
  180. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  181. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  182. #define CONFIG_SYS_CSPR2_EXT (0xf)
  183. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  184. | CSPR_PORT_SIZE_8 \
  185. | CSPR_MSEL_GPCM \
  186. | CSPR_V)
  187. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  188. #define CONFIG_SYS_CSOR2 0x0
  189. /* CPLD Timing parameters for IFC CS2 */
  190. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  191. FTIM0_GPCM_TEADC(0x0e) | \
  192. FTIM0_GPCM_TEAHC(0x0e))
  193. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  194. FTIM1_GPCM_TRAD(0x1f))
  195. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  196. FTIM2_GPCM_TCH(0x8) | \
  197. FTIM2_GPCM_TWP(0x1f))
  198. #define CONFIG_SYS_CS2_FTIM3 0x0
  199. /* NAND Flash on IFC */
  200. #define CONFIG_SYS_NAND_BASE 0xff800000
  201. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  202. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  203. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  204. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  205. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  206. | CSPR_V)
  207. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  208. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  209. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  210. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  211. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  212. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  213. | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
  214. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  215. /* ONFI NAND Flash mode0 Timing Params */
  216. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  217. FTIM0_NAND_TWP(0x18) | \
  218. FTIM0_NAND_TWCHT(0x07) | \
  219. FTIM0_NAND_TWH(0x0a))
  220. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  221. FTIM1_NAND_TWBE(0x39) | \
  222. FTIM1_NAND_TRR(0x0e) | \
  223. FTIM1_NAND_TRP(0x18))
  224. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  225. FTIM2_NAND_TREH(0x0a) | \
  226. FTIM2_NAND_TWHRE(0x1e))
  227. #define CONFIG_SYS_NAND_FTIM3 0x0
  228. #define CONFIG_SYS_NAND_DDR_LAW 11
  229. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  230. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  231. #if defined(CONFIG_MTD_RAW_NAND)
  232. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  233. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  234. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  235. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  236. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  237. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  238. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  239. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  240. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
  241. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  242. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  243. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  244. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  245. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  246. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  247. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  248. #else
  249. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  250. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  251. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  252. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  253. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  254. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  255. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  256. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  257. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  258. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  259. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  260. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  261. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  262. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  263. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  264. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  265. #endif
  266. #ifdef CONFIG_SPL_BUILD
  267. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  268. #else
  269. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  270. #endif
  271. #if defined(CONFIG_RAMBOOT_PBL)
  272. #define CONFIG_SYS_RAMBOOT
  273. #endif
  274. #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
  275. #if defined(CONFIG_MTD_RAW_NAND)
  276. #define CONFIG_A008044_WORKAROUND
  277. #endif
  278. #endif
  279. #define CONFIG_HWCONFIG
  280. /* define to use L1 as initial stack */
  281. #define CONFIG_L1_INIT_RAM
  282. #define CONFIG_SYS_INIT_RAM_LOCK
  283. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  284. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  285. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  286. /* The assembler doesn't like typecast */
  287. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  288. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  289. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  290. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  291. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  292. GENERATED_GBL_DATA_SIZE)
  293. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  294. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  295. /* Serial Port - controlled on board with jumper J8
  296. * open - index 2
  297. * shorted - index 1
  298. */
  299. #define CONFIG_SYS_NS16550_SERIAL
  300. #define CONFIG_SYS_NS16550_REG_SIZE 1
  301. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  302. #define CONFIG_SYS_BAUDRATE_TABLE \
  303. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  304. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  305. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  306. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  307. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  308. #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
  309. /* Video */
  310. #define CONFIG_FSL_DIU_FB
  311. #ifdef CONFIG_FSL_DIU_FB
  312. #define CONFIG_FSL_DIU_CH7301
  313. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  314. #define CONFIG_VIDEO_BMP_LOGO
  315. #endif
  316. #endif
  317. /* I2C */
  318. /* I2C bus multiplexer */
  319. #define I2C_MUX_PCA_ADDR 0x70
  320. #define I2C_MUX_CH_DEFAULT 0x8
  321. #if defined(CONFIG_TARGET_T1042RDB_PI) || \
  322. defined(CONFIG_TARGET_T1040D4RDB) || \
  323. defined(CONFIG_TARGET_T1042D4RDB)
  324. /* LDI/DVI Encoder for display */
  325. #define CONFIG_SYS_I2C_LDI_ADDR 0x38
  326. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  327. #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
  328. /*
  329. * RTC configuration
  330. */
  331. #define RTC
  332. #define CONFIG_RTC_DS1337 1
  333. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  334. /*DVI encoder*/
  335. #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
  336. #endif
  337. /*
  338. * eSPI - Enhanced SPI
  339. */
  340. /*
  341. * General PCI
  342. * Memory space is mapped 1-1, but I/O space must start from 0.
  343. */
  344. #ifdef CONFIG_PCI
  345. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  346. #ifdef CONFIG_PCIE1
  347. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  348. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  349. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  350. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  351. #endif
  352. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  353. #ifdef CONFIG_PCIE2
  354. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  355. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  356. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  357. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  358. #endif
  359. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  360. #ifdef CONFIG_PCIE3
  361. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  362. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  363. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  364. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  365. #endif
  366. /* controller 4, Base address 203000 */
  367. #ifdef CONFIG_PCIE4
  368. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
  369. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
  370. #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
  371. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  372. #endif
  373. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  374. #endif /* CONFIG_PCI */
  375. /* SATA */
  376. #define CONFIG_FSL_SATA_V2
  377. #ifdef CONFIG_FSL_SATA_V2
  378. #define CONFIG_SATA1
  379. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  380. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  381. #define CONFIG_LBA48
  382. #endif
  383. /*
  384. * USB
  385. */
  386. #define CONFIG_HAS_FSL_DR_USB
  387. #ifdef CONFIG_HAS_FSL_DR_USB
  388. #ifdef CONFIG_USB_EHCI_HCD
  389. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  390. #endif
  391. #endif
  392. #ifdef CONFIG_MMC
  393. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  394. #endif
  395. /* Qman/Bman */
  396. #ifndef CONFIG_NOBQFMAN
  397. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  398. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  399. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  400. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  401. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  402. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  403. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  404. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  405. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  406. CONFIG_SYS_BMAN_CENA_SIZE)
  407. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  408. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  409. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  410. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  411. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  412. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  413. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  414. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  415. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  416. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  417. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  418. CONFIG_SYS_QMAN_CENA_SIZE)
  419. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  420. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  421. #define CONFIG_SYS_DPAA_FMAN
  422. #define CONFIG_SYS_DPAA_PME
  423. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  424. #endif /* CONFIG_NOBQFMAN */
  425. #ifdef CONFIG_FMAN_ENET
  426. #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
  427. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
  428. #elif defined(CONFIG_TARGET_T1040D4RDB)
  429. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
  430. #elif defined(CONFIG_TARGET_T1042D4RDB)
  431. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
  432. #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
  433. #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
  434. #endif
  435. #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
  436. #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
  437. #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
  438. #else
  439. #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
  440. #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
  441. #endif
  442. /* Enable VSC9953 L2 Switch driver on T1040 SoC */
  443. #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
  444. #define CONFIG_VSC9953
  445. #ifdef CONFIG_TARGET_T1040RDB
  446. #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
  447. #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
  448. #else
  449. #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
  450. #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
  451. #endif
  452. #endif
  453. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  454. #endif
  455. /*
  456. * Environment
  457. */
  458. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  459. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  460. /*
  461. * Miscellaneous configurable options
  462. */
  463. /*
  464. * For booting Linux, the board info and command line data
  465. * have to be in the first 64 MB of memory, since this is
  466. * the maximum mapped by the Linux kernel during initialization.
  467. */
  468. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  469. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  470. /*
  471. * Dynamic MTD Partition support with mtdparts
  472. */
  473. /*
  474. * Environment Configuration
  475. */
  476. #define CONFIG_ROOTPATH "/opt/nfsroot"
  477. #define CONFIG_BOOTFILE "uImage"
  478. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  479. #define __USB_PHY_TYPE utmi
  480. #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
  481. #ifdef CONFIG_TARGET_T1040RDB
  482. #define FDTFILE "t1040rdb/t1040rdb.dtb"
  483. #elif defined(CONFIG_TARGET_T1042RDB_PI)
  484. #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
  485. #elif defined(CONFIG_TARGET_T1042RDB)
  486. #define FDTFILE "t1042rdb/t1042rdb.dtb"
  487. #elif defined(CONFIG_TARGET_T1040D4RDB)
  488. #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
  489. #elif defined(CONFIG_TARGET_T1042D4RDB)
  490. #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
  491. #endif
  492. #ifdef CONFIG_FSL_DIU_FB
  493. #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
  494. #else
  495. #define DIU_ENVIRONMENT
  496. #endif
  497. #define CONFIG_EXTRA_ENV_SETTINGS \
  498. "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
  499. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  500. "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  501. "netdev=eth0\0" \
  502. "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
  503. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  504. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  505. "tftpflash=tftpboot $loadaddr $uboot && " \
  506. "protect off $ubootaddr +$filesize && " \
  507. "erase $ubootaddr +$filesize && " \
  508. "cp.b $loadaddr $ubootaddr $filesize && " \
  509. "protect on $ubootaddr +$filesize && " \
  510. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  511. "consoledev=ttyS0\0" \
  512. "ramdiskaddr=2000000\0" \
  513. "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
  514. "fdtaddr=1e00000\0" \
  515. "fdtfile=" __stringify(FDTFILE) "\0" \
  516. "bdev=sda3\0"
  517. #include <asm/fsl_secure_boot.h>
  518. #endif /* __CONFIG_H */