P2041RDB.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020-2021 NXP
  5. */
  6. /*
  7. * P2041 RDB board configuration file
  8. * Also supports P2040 RDB
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. #ifdef CONFIG_RAMBOOT_PBL
  13. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  14. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  15. #endif
  16. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  17. /* Set 1M boot space */
  18. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  19. #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  20. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  21. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  22. #endif
  23. /* High Level Configuration Options */
  24. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  25. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  26. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  27. #endif
  28. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  29. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  30. #define CONFIG_PCIE1 /* PCIE controller 1 */
  31. #define CONFIG_PCIE2 /* PCIE controller 2 */
  32. #define CONFIG_PCIE3 /* PCIE controller 3 */
  33. #define CONFIG_SYS_SRIO
  34. #define CONFIG_SRIO1 /* SRIO port 1 */
  35. #define CONFIG_SRIO2 /* SRIO port 2 */
  36. #define CONFIG_SRIO_PCIE_BOOT_MASTER
  37. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  38. #if defined(CONFIG_SPIFLASH)
  39. #elif defined(CONFIG_SDCARD)
  40. #define CONFIG_FSL_FIXED_MMC_LOCATION
  41. #endif
  42. #ifndef __ASSEMBLY__
  43. #include <linux/stringify.h>
  44. #endif
  45. /*
  46. * These can be toggled for performance analysis, otherwise use default.
  47. */
  48. #define CONFIG_SYS_CACHE_STASHING
  49. #define CONFIG_BACKSIDE_L2_CACHE
  50. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  51. #define CONFIG_BTB /* toggle branch predition */
  52. #define CONFIG_ENABLE_36BIT_PHYS
  53. #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
  54. /*
  55. * Config the L3 Cache as L3 SRAM
  56. */
  57. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  58. #ifdef CONFIG_PHYS_64BIT
  59. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
  60. CONFIG_RAMBOOT_TEXT_BASE)
  61. #else
  62. #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  63. #endif
  64. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  65. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  66. #ifdef CONFIG_PHYS_64BIT
  67. #define CONFIG_SYS_DCSRBAR 0xf0000000
  68. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  69. #endif
  70. /* EEPROM */
  71. #define CONFIG_SYS_I2C_EEPROM_NXID
  72. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  73. /*
  74. * DDR Setup
  75. */
  76. #define CONFIG_VERY_BIG_RAM
  77. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  78. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  79. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  80. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  81. #define CONFIG_SYS_SPD_BUS_NUM 0
  82. #define SPD_EEPROM_ADDRESS 0x52
  83. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  84. /*
  85. * Local Bus Definitions
  86. */
  87. /* Set the local bus clock 1/8 of platform clock */
  88. #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
  89. /*
  90. * This board doesn't have a promjet connector.
  91. * However, it uses commone corenet board LAW and TLB.
  92. * It is necessary to use the same start address with proper offset.
  93. */
  94. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  95. #ifdef CONFIG_PHYS_64BIT
  96. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  97. #else
  98. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  99. #endif
  100. #define CONFIG_SYS_FLASH_BR_PRELIM \
  101. (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
  102. BR_PS_16 | BR_V)
  103. #define CONFIG_SYS_FLASH_OR_PRELIM \
  104. ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
  105. | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
  106. #define CONFIG_FSL_CPLD
  107. #define CPLD_BASE 0xffdf0000 /* CPLD registers */
  108. #ifdef CONFIG_PHYS_64BIT
  109. #define CPLD_BASE_PHYS 0xfffdf0000ull
  110. #else
  111. #define CPLD_BASE_PHYS CPLD_BASE
  112. #endif
  113. #define PIXIS_LBMAP_SWITCH 7
  114. #define PIXIS_LBMAP_MASK 0xf0
  115. #define PIXIS_LBMAP_SHIFT 4
  116. #define PIXIS_LBMAP_ALTBANK 0x40
  117. #define CONFIG_SYS_FLASH_QUIET_TEST
  118. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  119. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  120. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
  121. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
  122. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  123. #if defined(CONFIG_RAMBOOT_PBL)
  124. #define CONFIG_SYS_RAMBOOT
  125. #endif
  126. /* Nand Flash */
  127. #ifdef CONFIG_NAND_FSL_ELBC
  128. #define CONFIG_SYS_NAND_BASE 0xffa00000
  129. #ifdef CONFIG_PHYS_64BIT
  130. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  131. #else
  132. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  133. #endif
  134. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  135. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  136. /* NAND flash config */
  137. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  138. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  139. | BR_PS_8 /* Port Size = 8 bit */ \
  140. | BR_MS_FCM /* MSEL = FCM */ \
  141. | BR_V) /* valid */
  142. #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  143. | OR_FCM_PGS /* Large Page*/ \
  144. | OR_FCM_CSCT \
  145. | OR_FCM_CST \
  146. | OR_FCM_CHT \
  147. | OR_FCM_SCY_1 \
  148. | OR_FCM_TRLX \
  149. | OR_FCM_EHTR)
  150. #endif /* CONFIG_NAND_FSL_ELBC */
  151. #define CONFIG_SYS_FLASH_EMPTY_INFO
  152. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  153. #define CONFIG_HWCONFIG
  154. /* define to use L1 as initial stack */
  155. #define CONFIG_L1_INIT_RAM
  156. #define CONFIG_SYS_INIT_RAM_LOCK
  157. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  158. #ifdef CONFIG_PHYS_64BIT
  159. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  160. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  161. /* The assembler doesn't like typecast */
  162. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  163. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  164. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  165. #else
  166. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  167. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  168. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  169. #endif
  170. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  171. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  172. GENERATED_GBL_DATA_SIZE)
  173. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  174. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  175. /* Serial Port - controlled on board with jumper J8
  176. * open - index 2
  177. * shorted - index 1
  178. */
  179. #define CONFIG_SYS_NS16550_SERIAL
  180. #define CONFIG_SYS_NS16550_REG_SIZE 1
  181. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  182. #define CONFIG_SYS_BAUDRATE_TABLE \
  183. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  184. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  185. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  186. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  187. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  188. /* I2C */
  189. /*
  190. * RapidIO
  191. */
  192. #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  193. #ifdef CONFIG_PHYS_64BIT
  194. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  195. #else
  196. #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
  197. #endif
  198. #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  199. #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  200. #ifdef CONFIG_PHYS_64BIT
  201. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  202. #else
  203. #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
  204. #endif
  205. #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  206. /*
  207. * for slave u-boot IMAGE instored in master memory space,
  208. * PHYS must be aligned based on the SIZE
  209. */
  210. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  211. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  212. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
  213. #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  214. /*
  215. * for slave UCODE and ENV instored in master memory space,
  216. * PHYS must be aligned based on the SIZE
  217. */
  218. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
  219. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  220. #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  221. /* slave core release by master*/
  222. #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  223. #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  224. /*
  225. * SRIO_PCIE_BOOT - SLAVE
  226. */
  227. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  228. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  229. #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  230. (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  231. #endif
  232. /*
  233. * eSPI - Enhanced SPI
  234. */
  235. /*
  236. * General PCI
  237. * Memory space is mapped 1-1, but I/O space must start from 0.
  238. */
  239. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  240. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  241. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  242. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  243. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  244. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  245. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  246. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  247. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  248. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  249. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  250. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  251. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  252. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  253. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  254. /* Qman/Bman */
  255. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  256. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  257. #ifdef CONFIG_PHYS_64BIT
  258. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  259. #else
  260. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  261. #endif
  262. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  263. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  264. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  265. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  266. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  267. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  268. CONFIG_SYS_BMAN_CENA_SIZE)
  269. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  270. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  271. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  272. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  273. #ifdef CONFIG_PHYS_64BIT
  274. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  275. #else
  276. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  277. #endif
  278. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  279. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  280. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  281. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  282. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  283. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  284. CONFIG_SYS_QMAN_CENA_SIZE)
  285. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  286. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  287. #define CONFIG_SYS_DPAA_FMAN
  288. #define CONFIG_SYS_DPAA_PME
  289. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  290. #ifdef CONFIG_PCI
  291. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  292. #endif /* CONFIG_PCI */
  293. /* SATA */
  294. #define CONFIG_FSL_SATA_V2
  295. #ifdef CONFIG_FSL_SATA_V2
  296. #define CONFIG_SATA1
  297. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  298. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  299. #define CONFIG_SATA2
  300. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  301. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  302. #define CONFIG_LBA48
  303. #endif
  304. #ifdef CONFIG_FMAN_ENET
  305. #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
  306. #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
  307. #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
  308. #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
  309. #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
  310. #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
  311. #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
  312. #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
  313. #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
  314. #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
  315. #define CONFIG_SYS_TBIPA_VALUE 8
  316. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  317. #endif
  318. /*
  319. * Environment
  320. */
  321. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  322. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  323. /*
  324. * USB
  325. */
  326. #define CONFIG_HAS_FSL_DR_USB
  327. #define CONFIG_HAS_FSL_MPH_USB
  328. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  329. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  330. #endif
  331. #ifdef CONFIG_MMC
  332. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  333. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  334. #endif
  335. /*
  336. * Miscellaneous configurable options
  337. */
  338. /*
  339. * For booting Linux, the board info and command line data
  340. * have to be in the first 64 MB of memory, since this is
  341. * the maximum mapped by the Linux kernel during initialization.
  342. */
  343. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
  344. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  345. /*
  346. * Environment Configuration
  347. */
  348. #define CONFIG_ROOTPATH "/opt/nfsroot"
  349. #define CONFIG_BOOTFILE "uImage"
  350. #define CONFIG_UBOOTPATH u-boot.bin
  351. #define __USB_PHY_TYPE utmi
  352. #define CONFIG_EXTRA_ENV_SETTINGS \
  353. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  354. "bank_intlv=cs0_cs1\0" \
  355. "netdev=eth0\0" \
  356. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  357. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  358. "tftpflash=tftpboot $loadaddr $uboot && " \
  359. "protect off $ubootaddr +$filesize && " \
  360. "erase $ubootaddr +$filesize && " \
  361. "cp.b $loadaddr $ubootaddr $filesize && " \
  362. "protect on $ubootaddr +$filesize && " \
  363. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  364. "consoledev=ttyS0\0" \
  365. "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  366. "usb_dr_mode=host\0" \
  367. "ramdiskaddr=2000000\0" \
  368. "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
  369. "fdtaddr=1e00000\0" \
  370. "fdtfile=p2041rdb/p2041rdb.dtb\0" \
  371. "bdev=sda3\0"
  372. #include <asm/fsl_secure_boot.h>
  373. #endif /* __CONFIG_H */