P1010RDB.h 21 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * P010 RDB board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include <linux/stringify.h>
  12. #include <asm/config_mpc85xx.h>
  13. #ifdef CONFIG_SDCARD
  14. #define CONFIG_SPL_FLUSH_IMAGE
  15. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  16. #define CONFIG_SPL_PAD_TO 0x18000
  17. #define CONFIG_SPL_MAX_SIZE (96 * 1024)
  18. #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
  19. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  20. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  21. #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
  22. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  23. #ifdef CONFIG_SPL_BUILD
  24. #define CONFIG_SPL_COMMON_INIT_DDR
  25. #endif
  26. #endif
  27. #ifdef CONFIG_SPIFLASH
  28. #ifdef CONFIG_NXP_ESBC
  29. #define CONFIG_RAMBOOT_SPIFLASH
  30. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  31. #else
  32. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  33. #define CONFIG_SPL_FLUSH_IMAGE
  34. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  35. #define CONFIG_SPL_PAD_TO 0x18000
  36. #define CONFIG_SPL_MAX_SIZE (96 * 1024)
  37. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
  38. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  39. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  40. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
  41. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  42. #ifdef CONFIG_SPL_BUILD
  43. #define CONFIG_SPL_COMMON_INIT_DDR
  44. #endif
  45. #endif
  46. #endif
  47. #ifdef CONFIG_MTD_RAW_NAND
  48. #ifdef CONFIG_NXP_ESBC
  49. #define CONFIG_SPL_INIT_MINIMAL
  50. #define CONFIG_SPL_FLUSH_IMAGE
  51. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  52. #define CONFIG_SPL_MAX_SIZE 8192
  53. #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
  54. #define CONFIG_SPL_RELOC_STACK 0x00100000
  55. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
  56. #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
  57. #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
  58. #else
  59. #ifdef CONFIG_TPL_BUILD
  60. #define CONFIG_SPL_FLUSH_IMAGE
  61. #define CONFIG_SPL_NAND_INIT
  62. #define CONFIG_SPL_COMMON_INIT_DDR
  63. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  64. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  65. #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
  66. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  67. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  68. #elif defined(CONFIG_SPL_BUILD)
  69. #define CONFIG_SPL_INIT_MINIMAL
  70. #define CONFIG_SPL_NAND_MINIMAL
  71. #define CONFIG_SPL_FLUSH_IMAGE
  72. #define CONFIG_SPL_MAX_SIZE 8192
  73. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  74. #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
  75. #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
  76. #endif
  77. #define CONFIG_SPL_PAD_TO 0x20000
  78. #define CONFIG_TPL_PAD_TO 0x20000
  79. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  80. #endif
  81. #endif
  82. #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
  83. #define CONFIG_RAMBOOT_NAND
  84. #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
  85. #endif
  86. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  87. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  88. #endif
  89. #ifdef CONFIG_TPL_BUILD
  90. #define CONFIG_SYS_MONITOR_BASE 0xD0001000
  91. #elif defined(CONFIG_SPL_BUILD)
  92. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  93. #else
  94. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  95. #endif
  96. /* High Level Configuration Options */
  97. #if defined(CONFIG_PCI)
  98. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  99. #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  100. /*
  101. * PCI Windows
  102. * Memory space is mapped 1-1, but I/O space must start from 0.
  103. */
  104. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  105. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  106. #ifdef CONFIG_PHYS_64BIT
  107. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  108. #else
  109. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  110. #endif
  111. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  112. #ifdef CONFIG_PHYS_64BIT
  113. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  114. #else
  115. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  116. #endif
  117. /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  118. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  119. #ifdef CONFIG_PHYS_64BIT
  120. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  121. #else
  122. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  123. #endif
  124. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  125. #ifdef CONFIG_PHYS_64BIT
  126. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  127. #else
  128. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  129. #endif
  130. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  131. #endif
  132. #define CONFIG_HWCONFIG
  133. /*
  134. * These can be toggled for performance analysis, otherwise use default.
  135. */
  136. #define CONFIG_L2_CACHE /* toggle L2 cache */
  137. #define CONFIG_BTB /* toggle branch predition */
  138. #define CONFIG_ENABLE_36BIT_PHYS
  139. /* DDR Setup */
  140. #define CONFIG_SYS_DDR_RAW_TIMING
  141. #define CONFIG_SYS_SPD_BUS_NUM 1
  142. #define SPD_EEPROM_ADDRESS 0x52
  143. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  144. #ifndef __ASSEMBLY__
  145. extern unsigned long get_sdram_size(void);
  146. #endif
  147. #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
  148. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  149. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  150. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  151. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  152. /* DDR3 Controller Settings */
  153. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  154. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  155. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  156. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  157. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  158. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  159. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  160. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  161. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  162. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  163. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  164. #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
  165. #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
  166. #define CONFIG_SYS_DDR_TIMING_4 0x00000001
  167. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  168. #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
  169. #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
  170. #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
  171. #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
  172. #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
  173. #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
  174. #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
  175. #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
  176. #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
  177. /* settings for DDR3 at 667MT/s */
  178. #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
  179. #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
  180. #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
  181. #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
  182. #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
  183. #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
  184. #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
  185. #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
  186. #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
  187. #define CONFIG_SYS_CCSRBAR 0xffe00000
  188. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  189. /* Don't relocate CCSRBAR while in NAND_SPL */
  190. #ifdef CONFIG_SPL_BUILD
  191. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  192. #endif
  193. /*
  194. * Memory map
  195. *
  196. * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
  197. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
  198. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  199. *
  200. * Localbus non-cacheable
  201. * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
  202. * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
  203. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  204. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  205. */
  206. /*
  207. * IFC Definitions
  208. */
  209. /* NOR Flash on IFC */
  210. #define CONFIG_SYS_FLASH_BASE 0xee000000
  211. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
  212. #ifdef CONFIG_PHYS_64BIT
  213. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  214. #else
  215. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  216. #endif
  217. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  218. CSPR_PORT_SIZE_16 | \
  219. CSPR_MSEL_NOR | \
  220. CSPR_V)
  221. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
  222. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
  223. /* NOR Flash Timing Params */
  224. #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
  225. FTIM0_NOR_TEADC(0x5) | \
  226. FTIM0_NOR_TEAHC(0x5)
  227. #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
  228. FTIM1_NOR_TRAD_NOR(0x0f)
  229. #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
  230. FTIM2_NOR_TCH(0x4) | \
  231. FTIM2_NOR_TWP(0x1c)
  232. #define CONFIG_SYS_NOR_FTIM3 0x0
  233. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  234. #define CONFIG_SYS_FLASH_QUIET_TEST
  235. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  236. #undef CONFIG_SYS_FLASH_CHECKSUM
  237. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  238. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  239. /* CFI for NOR Flash */
  240. #define CONFIG_SYS_FLASH_EMPTY_INFO
  241. /* NAND Flash on IFC */
  242. #define CONFIG_SYS_NAND_BASE 0xff800000
  243. #ifdef CONFIG_PHYS_64BIT
  244. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  245. #else
  246. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  247. #endif
  248. #define CONFIG_MTD_PARTITION
  249. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  250. | CSPR_PORT_SIZE_8 \
  251. | CSPR_MSEL_NAND \
  252. | CSPR_V)
  253. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  254. #if defined(CONFIG_TARGET_P1010RDB_PA)
  255. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  256. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  257. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  258. | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
  259. | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
  260. | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
  261. | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
  262. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  263. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  264. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  265. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  266. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  267. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  268. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  269. | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
  270. #endif
  271. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  272. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  273. #if defined(CONFIG_TARGET_P1010RDB_PA)
  274. /* NAND Flash Timing Params */
  275. #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
  276. FTIM0_NAND_TWP(0x0C) | \
  277. FTIM0_NAND_TWCHT(0x04) | \
  278. FTIM0_NAND_TWH(0x05)
  279. #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
  280. FTIM1_NAND_TWBE(0x1d) | \
  281. FTIM1_NAND_TRR(0x07) | \
  282. FTIM1_NAND_TRP(0x0c)
  283. #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
  284. FTIM2_NAND_TREH(0x05) | \
  285. FTIM2_NAND_TWHRE(0x0f)
  286. #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
  287. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  288. /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
  289. /* ONFI NAND Flash mode0 Timing Params */
  290. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
  291. FTIM0_NAND_TWP(0x18) | \
  292. FTIM0_NAND_TWCHT(0x07) | \
  293. FTIM0_NAND_TWH(0x0a))
  294. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
  295. FTIM1_NAND_TWBE(0x39) | \
  296. FTIM1_NAND_TRR(0x0e) | \
  297. FTIM1_NAND_TRP(0x18))
  298. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  299. FTIM2_NAND_TREH(0x0a) | \
  300. FTIM2_NAND_TWHRE(0x1e))
  301. #define CONFIG_SYS_NAND_FTIM3 0x0
  302. #endif
  303. #define CONFIG_SYS_NAND_DDR_LAW 11
  304. /* Set up IFC registers for boot location NOR/NAND */
  305. #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
  306. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  307. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  308. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  309. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  310. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  311. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  312. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  313. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  314. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  315. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  316. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  317. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  318. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  319. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  320. #else
  321. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  322. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  323. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  324. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  325. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  326. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  327. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  328. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  329. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  330. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  331. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  332. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  333. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  334. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  335. #endif
  336. /* CPLD on IFC */
  337. #define CONFIG_SYS_CPLD_BASE 0xffb00000
  338. #ifdef CONFIG_PHYS_64BIT
  339. #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
  340. #else
  341. #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  342. #endif
  343. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  344. | CSPR_PORT_SIZE_8 \
  345. | CSPR_MSEL_GPCM \
  346. | CSPR_V)
  347. #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
  348. #define CONFIG_SYS_CSOR3 0x0
  349. /* CPLD Timing parameters for IFC CS3 */
  350. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  351. FTIM0_GPCM_TEADC(0x0e) | \
  352. FTIM0_GPCM_TEAHC(0x0e))
  353. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  354. FTIM1_GPCM_TRAD(0x1f))
  355. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  356. FTIM2_GPCM_TCH(0x8) | \
  357. FTIM2_GPCM_TWP(0x1f))
  358. #define CONFIG_SYS_CS3_FTIM3 0x0
  359. #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
  360. defined(CONFIG_RAMBOOT_NAND)
  361. #define CONFIG_SYS_RAMBOOT
  362. #else
  363. #undef CONFIG_SYS_RAMBOOT
  364. #endif
  365. #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  366. #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
  367. #define CONFIG_A003399_NOR_WORKAROUND
  368. #endif
  369. #endif
  370. #define CONFIG_SYS_INIT_RAM_LOCK
  371. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  372. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
  373. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
  374. - GENERATED_GBL_DATA_SIZE)
  375. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  376. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  377. /*
  378. * Config the L2 Cache as L2 SRAM
  379. */
  380. #if defined(CONFIG_SPL_BUILD)
  381. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  382. #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
  383. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  384. #define CONFIG_SYS_L2_SIZE (256 << 10)
  385. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  386. #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
  387. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  388. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
  389. #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
  390. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
  391. #elif defined(CONFIG_MTD_RAW_NAND)
  392. #ifdef CONFIG_TPL_BUILD
  393. #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
  394. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  395. #define CONFIG_SYS_L2_SIZE (256 << 10)
  396. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  397. #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
  398. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  399. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  400. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  401. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  402. #else
  403. #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
  404. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  405. #define CONFIG_SYS_L2_SIZE (256 << 10)
  406. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  407. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
  408. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  409. #endif
  410. #endif
  411. #endif
  412. /* Serial Port */
  413. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  414. #define CONFIG_SYS_NS16550_SERIAL
  415. #define CONFIG_SYS_NS16550_REG_SIZE 1
  416. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  417. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  418. #define CONFIG_NS16550_MIN_FUNCTIONS
  419. #endif
  420. #define CONFIG_SYS_BAUDRATE_TABLE \
  421. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  422. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  423. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  424. /* I2C */
  425. #define I2C_PCA9557_ADDR1 0x18
  426. #define I2C_PCA9557_ADDR2 0x19
  427. #define I2C_PCA9557_BUS_NUM 0
  428. /* I2C EEPROM */
  429. #if defined(CONFIG_TARGET_P1010RDB_PB)
  430. #ifdef CONFIG_ID_EEPROM
  431. #define CONFIG_SYS_I2C_EEPROM_NXID
  432. #endif
  433. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  434. #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
  435. #endif
  436. /* enable read and write access to EEPROM */
  437. /* RTC */
  438. #define CONFIG_RTC_PT7C4338
  439. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  440. /*
  441. * SPI interface will not be available in case of NAND boot SPI CS0 will be
  442. * used for SLIC
  443. */
  444. #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
  445. /* eSPI - Enhanced SPI */
  446. #endif
  447. #if defined(CONFIG_TSEC_ENET)
  448. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  449. #define CONFIG_TSEC1 1
  450. #define CONFIG_TSEC1_NAME "eTSEC1"
  451. #define CONFIG_TSEC2 1
  452. #define CONFIG_TSEC2_NAME "eTSEC2"
  453. #define CONFIG_TSEC3 1
  454. #define CONFIG_TSEC3_NAME "eTSEC3"
  455. #define TSEC1_PHY_ADDR 1
  456. #define TSEC2_PHY_ADDR 0
  457. #define TSEC3_PHY_ADDR 2
  458. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  459. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  460. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  461. #define TSEC1_PHYIDX 0
  462. #define TSEC2_PHYIDX 0
  463. #define TSEC3_PHYIDX 0
  464. #define CONFIG_ETHPRIME "eTSEC1"
  465. /* TBI PHY configuration for SGMII mode */
  466. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  467. TBICR_PHY_RESET \
  468. | TBICR_ANEG_ENABLE \
  469. | TBICR_FULL_DUPLEX \
  470. | TBICR_SPEED1_SET \
  471. )
  472. #endif /* CONFIG_TSEC_ENET */
  473. /* SATA */
  474. #define CONFIG_FSL_SATA_V2
  475. #ifdef CONFIG_FSL_SATA
  476. #define CONFIG_SATA1
  477. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  478. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  479. #define CONFIG_SATA2
  480. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  481. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  482. #define CONFIG_LBA48
  483. #endif /* #ifdef CONFIG_FSL_SATA */
  484. #ifdef CONFIG_MMC
  485. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  486. #endif
  487. #define CONFIG_HAS_FSL_DR_USB
  488. #if defined(CONFIG_HAS_FSL_DR_USB)
  489. #ifdef CONFIG_USB_EHCI_HCD
  490. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  491. #endif
  492. #endif
  493. /*
  494. * Environment
  495. */
  496. #if defined(CONFIG_SDCARD)
  497. #define CONFIG_FSL_FIXED_MMC_LOCATION
  498. #elif defined(CONFIG_MTD_RAW_NAND)
  499. #ifdef CONFIG_TPL_BUILD
  500. #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  501. #else
  502. #if defined(CONFIG_TARGET_P1010RDB_PA)
  503. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
  504. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  505. #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
  506. #endif
  507. #endif
  508. #endif
  509. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  510. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  511. #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
  512. || defined(CONFIG_FSL_SATA)
  513. #endif
  514. /*
  515. * Miscellaneous configurable options
  516. */
  517. /*
  518. * For booting Linux, the board info and command line data
  519. * have to be in the first 64 MB of memory, since this is
  520. * the maximum mapped by the Linux kernel during initialization.
  521. */
  522. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
  523. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  524. /*
  525. * Environment Configuration
  526. */
  527. #if defined(CONFIG_TSEC_ENET)
  528. #define CONFIG_HAS_ETH0
  529. #define CONFIG_HAS_ETH1
  530. #define CONFIG_HAS_ETH2
  531. #endif
  532. #define CONFIG_ROOTPATH "/opt/nfsroot"
  533. #define CONFIG_BOOTFILE "uImage"
  534. #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
  535. #define CONFIG_EXTRA_ENV_SETTINGS \
  536. "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
  537. "netdev=eth0\0" \
  538. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  539. "loadaddr=1000000\0" \
  540. "consoledev=ttyS0\0" \
  541. "ramdiskaddr=2000000\0" \
  542. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  543. "fdtaddr=1e00000\0" \
  544. "fdtfile=p1010rdb.dtb\0" \
  545. "bdev=sda1\0" \
  546. "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
  547. "othbootargs=ramdisk_size=600000\0" \
  548. "usbfatboot=setenv bootargs root=/dev/ram rw " \
  549. "console=$consoledev,$baudrate $othbootargs; " \
  550. "usb start;" \
  551. "fatload usb 0:2 $loadaddr $bootfile;" \
  552. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  553. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  554. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  555. "usbext2boot=setenv bootargs root=/dev/ram rw " \
  556. "console=$consoledev,$baudrate $othbootargs; " \
  557. "usb start;" \
  558. "ext2load usb 0:4 $loadaddr $bootfile;" \
  559. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  560. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  561. "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
  562. CONFIG_BOOTMODE
  563. #if defined(CONFIG_TARGET_P1010RDB_PA)
  564. #define CONFIG_BOOTMODE \
  565. "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
  566. "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
  567. "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
  568. "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
  569. "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
  570. "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
  571. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  572. #define CONFIG_BOOTMODE \
  573. "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
  574. "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
  575. "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
  576. "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
  577. "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
  578. "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
  579. "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
  580. "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
  581. "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
  582. "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
  583. #endif
  584. #include <asm/fsl_secure_boot.h>
  585. #endif /* __CONFIG_H */