MPC837XERDB.h 9.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  4. * Kevin Lam <kevin.lam@freescale.com>
  5. * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
  6. */
  7. #ifndef __CONFIG_H
  8. #define __CONFIG_H
  9. #include <linux/stringify.h>
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #define CONFIG_E300 1 /* E300 family */
  14. #define CONFIG_HWCONFIG
  15. /*
  16. * On-board devices
  17. */
  18. #define CONFIG_VSC7385_ENET
  19. /* System performance - define the value i.e. CONFIG_SYS_XXX
  20. */
  21. /* System Clock Configuration Register */
  22. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
  23. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
  24. #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
  25. /*
  26. * System IO Config
  27. */
  28. #define CONFIG_SYS_SICRH 0x08200000
  29. #define CONFIG_SYS_SICRL 0x00000000
  30. /*
  31. * Output Buffer Impedance
  32. */
  33. #define CONFIG_SYS_OBIR 0x30100000
  34. /*
  35. * Device configurations
  36. */
  37. /* Vitesse 7385 */
  38. #ifdef CONFIG_VSC7385_ENET
  39. #define CONFIG_TSEC2
  40. /* The flash address and size of the VSC7385 firmware image */
  41. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  42. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  43. #endif
  44. /*
  45. * DDR Setup
  46. */
  47. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  48. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
  49. #define CONFIG_SYS_83XX_DDR_USES_CS0
  50. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
  51. #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
  52. /*
  53. * Manually set up DDR parameters
  54. */
  55. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  56. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
  57. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  58. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  59. | CSCONFIG_ROW_BIT_13 \
  60. | CSCONFIG_COL_BIT_10)
  61. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  62. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  63. | (0 << TIMING_CFG0_WRT_SHIFT) \
  64. | (0 << TIMING_CFG0_RRT_SHIFT) \
  65. | (0 << TIMING_CFG0_WWT_SHIFT) \
  66. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  67. | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  68. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  69. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  70. /* 0x00260802 */ /* DDR400 */
  71. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  72. | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  73. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  74. | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  75. | (13 << TIMING_CFG1_REFREC_SHIFT) \
  76. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  77. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  78. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  79. /* 0x3937d322 */
  80. #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  81. | (5 << TIMING_CFG2_CPO_SHIFT) \
  82. | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  83. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  84. | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  85. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  86. | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
  87. /* 0x02984cc8 */
  88. #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
  89. | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  90. /* 0x06090100 */
  91. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  92. | SDRAM_CFG_SDRAM_TYPE_DDR2)
  93. /* 0x43000000 */
  94. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
  95. #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
  96. | (0x0442 << SDRAM_MODE_SD_SHIFT))
  97. /* 0x04400442 */ /* DDR400 */
  98. #define CONFIG_SYS_DDR_MODE2 0x00000000
  99. /*
  100. * Memory test
  101. */
  102. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  103. /*
  104. * The reserved memory
  105. */
  106. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  107. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  108. #define CONFIG_SYS_RAMBOOT
  109. #else
  110. #undef CONFIG_SYS_RAMBOOT
  111. #endif
  112. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  113. /*
  114. * Initial RAM Base Address Setup
  115. */
  116. #define CONFIG_SYS_INIT_RAM_LOCK 1
  117. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  118. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  119. #define CONFIG_SYS_GBL_DATA_OFFSET \
  120. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  121. /*
  122. * FLASH on the Local Bus
  123. */
  124. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  125. #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
  126. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  127. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  128. #undef CONFIG_SYS_FLASH_CHECKSUM
  129. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  130. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  131. /*
  132. * NAND Flash on the Local Bus
  133. */
  134. #define CONFIG_SYS_NAND_BASE 0xE0600000
  135. /* Vitesse 7385 */
  136. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  137. /*
  138. * Serial Port
  139. */
  140. #define CONFIG_SYS_NS16550_SERIAL
  141. #define CONFIG_SYS_NS16550_REG_SIZE 1
  142. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  143. #define CONFIG_SYS_BAUDRATE_TABLE \
  144. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  145. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  146. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  147. /* SERDES */
  148. #define CONFIG_FSL_SERDES
  149. #define CONFIG_FSL_SERDES1 0xe3000
  150. #define CONFIG_FSL_SERDES2 0xe3100
  151. /* I2C */
  152. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  153. /*
  154. * Config on-board RTC
  155. */
  156. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  157. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  158. /*
  159. * General PCI
  160. * Addresses are mapped 1-1.
  161. */
  162. #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
  163. #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
  164. #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
  165. #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
  166. #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
  167. #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
  168. #define CONFIG_SYS_PCI_IO_BASE 0x00000000
  169. #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
  170. #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
  171. #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
  172. #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
  173. #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
  174. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  175. #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
  176. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
  177. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
  178. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
  179. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  180. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  181. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
  182. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  183. #define CONFIG_SYS_PCIE2_BASE 0xC0000000
  184. #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
  185. #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
  186. #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
  187. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
  188. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
  189. #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
  190. #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
  191. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
  192. #ifdef CONFIG_PCI
  193. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  194. #endif /* CONFIG_PCI */
  195. /*
  196. * TSEC
  197. */
  198. #ifdef CONFIG_TSEC_ENET
  199. #define CONFIG_GMII /* MII PHY management */
  200. #define CONFIG_TSEC1
  201. #ifdef CONFIG_TSEC1
  202. #define CONFIG_HAS_ETH0
  203. #define CONFIG_TSEC1_NAME "TSEC0"
  204. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  205. #define TSEC1_PHY_ADDR 2
  206. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  207. #define TSEC1_PHYIDX 0
  208. #endif
  209. #ifdef CONFIG_TSEC2
  210. #define CONFIG_HAS_ETH1
  211. #define CONFIG_TSEC2_NAME "TSEC1"
  212. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  213. #define TSEC2_PHY_ADDR 0x1c
  214. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  215. #define TSEC2_PHYIDX 0
  216. #endif
  217. /* Options are: TSEC[0-1] */
  218. #define CONFIG_ETHPRIME "TSEC0"
  219. #endif
  220. /*
  221. * SATA
  222. */
  223. #define CONFIG_SATA1
  224. #define CONFIG_SYS_SATA1_OFFSET 0x18000
  225. #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
  226. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  227. #define CONFIG_SATA2
  228. #define CONFIG_SYS_SATA2_OFFSET 0x19000
  229. #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
  230. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  231. #ifdef CONFIG_FSL_SATA
  232. #define CONFIG_LBA48
  233. #endif
  234. /*
  235. * Environment
  236. */
  237. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  238. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  239. /*
  240. * BOOTP options
  241. */
  242. #define CONFIG_BOOTP_BOOTFILESIZE
  243. #ifdef CONFIG_MMC
  244. #define CONFIG_FSL_ESDHC_PIN_MUX
  245. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  246. #endif
  247. /*
  248. * Miscellaneous configurable options
  249. */
  250. /*
  251. * For booting Linux, the board info and command line data
  252. * have to be in the first 256 MB of memory, since this is
  253. * the maximum mapped by the Linux kernel during initialization.
  254. */
  255. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  256. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  257. /*
  258. * Environment Configuration
  259. */
  260. #define CONFIG_HAS_FSL_DR_USB
  261. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  262. #define CONFIG_NETDEV "eth1"
  263. #define CONFIG_HOSTNAME "mpc837x_rdb"
  264. #define CONFIG_ROOTPATH "/nfsroot"
  265. #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
  266. #define CONFIG_BOOTFILE "uImage"
  267. /* U-Boot image on TFTP server */
  268. #define CONFIG_UBOOTPATH "u-boot.bin"
  269. #define CONFIG_FDTFILE "mpc8379_rdb.dtb"
  270. #define CONFIG_EXTRA_ENV_SETTINGS \
  271. "netdev=" CONFIG_NETDEV "\0" \
  272. "uboot=" CONFIG_UBOOTPATH "\0" \
  273. "tftpflash=tftp $loadaddr $uboot;" \
  274. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  275. " +$filesize; " \
  276. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  277. " +$filesize; " \
  278. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  279. " $filesize; " \
  280. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  281. " +$filesize; " \
  282. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  283. " $filesize\0" \
  284. "fdtaddr=780000\0" \
  285. "fdtfile=" CONFIG_FDTFILE "\0" \
  286. "ramdiskaddr=1000000\0" \
  287. "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
  288. "console=ttyS0\0" \
  289. "setbootargs=setenv bootargs " \
  290. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  291. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  292. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  293. "$netdev:off " \
  294. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  295. #endif /* __CONFIG_H */