sbc8641d.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
  4. * Copyright 2007 Embedded Specialties, Inc.
  5. * Joe Hamman joe.hamman@embeddedspecialties.com
  6. *
  7. * Copyright 2004 Freescale Semiconductor.
  8. * Jeff Brown
  9. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  10. *
  11. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  12. */
  13. #include <common.h>
  14. #include <command.h>
  15. #include <init.h>
  16. #include <log.h>
  17. #include <pci.h>
  18. #include <asm/global_data.h>
  19. #include <asm/processor.h>
  20. #include <asm/immap_86xx.h>
  21. #include <asm/fsl_pci.h>
  22. #include <fsl_ddr_sdram.h>
  23. #include <asm/fsl_serdes.h>
  24. #include <linux/delay.h>
  25. #include <linux/libfdt.h>
  26. #include <fdt_support.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. long int fixed_sdram (void);
  29. int board_early_init_f (void)
  30. {
  31. return 0;
  32. }
  33. int checkboard (void)
  34. {
  35. puts ("Board: Wind River SBC8641D\n");
  36. return 0;
  37. }
  38. int dram_init(void)
  39. {
  40. long dram_size = 0;
  41. #if defined(CONFIG_SPD_EEPROM)
  42. dram_size = fsl_ddr_sdram();
  43. #else
  44. dram_size = fixed_sdram ();
  45. #endif
  46. debug(" DDR: ");
  47. gd->ram_size = dram_size;
  48. return 0;
  49. }
  50. #if defined(CONFIG_SYS_DRAM_TEST)
  51. int testdram(void)
  52. {
  53. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  54. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  55. uint *p;
  56. puts ("SDRAM test phase 1:\n");
  57. for (p = pstart; p < pend; p++)
  58. *p = 0xaaaaaaaa;
  59. for (p = pstart; p < pend; p++) {
  60. if (*p != 0xaaaaaaaa) {
  61. printf ("SDRAM test fails at: %08x\n", (uint) p);
  62. return 1;
  63. }
  64. }
  65. puts ("SDRAM test phase 2:\n");
  66. for (p = pstart; p < pend; p++)
  67. *p = 0x55555555;
  68. for (p = pstart; p < pend; p++) {
  69. if (*p != 0x55555555) {
  70. printf ("SDRAM test fails at: %08x\n", (uint) p);
  71. return 1;
  72. }
  73. }
  74. puts ("SDRAM test passed.\n");
  75. return 0;
  76. }
  77. #endif
  78. #if !defined(CONFIG_SPD_EEPROM)
  79. /*
  80. * Fixed sdram init -- doesn't use serial presence detect.
  81. */
  82. long int fixed_sdram (void)
  83. {
  84. #if !defined(CONFIG_SYS_RAMBOOT)
  85. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  86. volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
  87. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  88. ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
  89. ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
  90. ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
  91. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  92. ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
  93. ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
  94. ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
  95. ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  96. ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  97. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  98. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  99. ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
  100. ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
  101. ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  102. ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  103. ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
  104. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  105. ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  106. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  107. asm ("sync;isync");
  108. udelay(500);
  109. ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
  110. asm ("sync; isync");
  111. udelay(500);
  112. ddr = &immap->im_ddr2;
  113. ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
  114. ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
  115. ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
  116. ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
  117. ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
  118. ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
  119. ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
  120. ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
  121. ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
  122. ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
  123. ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
  124. ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
  125. ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
  126. ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
  127. ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
  128. ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
  129. ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
  130. ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
  131. ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
  132. ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
  133. asm ("sync;isync");
  134. udelay(500);
  135. ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
  136. asm ("sync; isync");
  137. udelay(500);
  138. #endif
  139. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  140. }
  141. #endif /* !defined(CONFIG_SPD_EEPROM) */
  142. #if defined(CONFIG_PCI)
  143. /*
  144. * Initialize PCI Devices, report devices found.
  145. */
  146. void pci_init_board(void)
  147. {
  148. fsl_pcie_init_board(0);
  149. }
  150. #endif /* CONFIG_PCI */
  151. #if defined(CONFIG_OF_BOARD_SETUP)
  152. int ft_board_setup(void *blob, struct bd_info *bd)
  153. {
  154. ft_cpu_setup(blob, bd);
  155. FT_FSL_PCI_SETUP;
  156. return 0;
  157. }
  158. #endif
  159. void sbc8641d_reset_board (void)
  160. {
  161. puts ("Resetting board....\n");
  162. }
  163. /*
  164. * get_board_sys_clk
  165. * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
  166. */
  167. unsigned long get_board_sys_clk (ulong dummy)
  168. {
  169. int i;
  170. ulong val = 0;
  171. i = 5;
  172. i &= 0x07;
  173. switch (i) {
  174. case 0:
  175. val = 33000000;
  176. break;
  177. case 1:
  178. val = 40000000;
  179. break;
  180. case 2:
  181. val = 50000000;
  182. break;
  183. case 3:
  184. val = 66000000;
  185. break;
  186. case 4:
  187. val = 83000000;
  188. break;
  189. case 5:
  190. val = 100000000;
  191. break;
  192. case 6:
  193. val = 134000000;
  194. break;
  195. case 7:
  196. val = 166000000;
  197. break;
  198. }
  199. return val;
  200. }
  201. void board_reset(void)
  202. {
  203. #ifdef CONFIG_SYS_RESET_ADDRESS
  204. ulong addr = CONFIG_SYS_RESET_ADDRESS;
  205. /* flush and disable I/D cache */
  206. __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
  207. __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
  208. __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
  209. __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
  210. __asm__ __volatile__ ("sync");
  211. __asm__ __volatile__ ("mtspr 1008, 4");
  212. __asm__ __volatile__ ("isync");
  213. __asm__ __volatile__ ("sync");
  214. __asm__ __volatile__ ("mtspr 1008, 5");
  215. __asm__ __volatile__ ("isync");
  216. __asm__ __volatile__ ("sync");
  217. /*
  218. * SRR0 has system reset vector, SRR1 has default MSR value
  219. * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
  220. */
  221. __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
  222. __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
  223. __asm__ __volatile__ ("mtspr 27, 4");
  224. __asm__ __volatile__ ("rfi");
  225. #endif
  226. }