immap_86xx.h 59 KB

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  1. /*
  2. * MPC86xx Internal Memory Map
  3. *
  4. * Copyright 2004, 2011 Freescale Semiconductor
  5. * Jeff Brown (Jeffrey@freescale.com)
  6. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  7. *
  8. */
  9. #ifndef __IMMAP_86xx__
  10. #define __IMMAP_86xx__
  11. #include <fsl_immap.h>
  12. #include <asm/types.h>
  13. #include <asm/fsl_dma.h>
  14. #include <asm/fsl_lbc.h>
  15. #include <asm/fsl_i2c.h>
  16. /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
  17. typedef struct ccsr_local_mcm {
  18. uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
  19. char res1[4];
  20. uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
  21. char res2[4];
  22. uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
  23. char res3[12];
  24. uint bptr; /* 0x20 - Boot Page Translation Register */
  25. char res4[3044];
  26. uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
  27. char res5[4];
  28. uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
  29. char res6[20];
  30. uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
  31. char res7[4];
  32. uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
  33. char res8[20];
  34. uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
  35. char res9[4];
  36. uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
  37. char res10[20];
  38. uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
  39. char res11[4];
  40. uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
  41. char res12[20];
  42. uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
  43. char res13[4];
  44. uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
  45. char res14[20];
  46. uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
  47. char res15[4];
  48. uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
  49. char res16[20];
  50. uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
  51. char res17[4];
  52. uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
  53. char res18[20];
  54. uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
  55. char res19[4];
  56. uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
  57. char res20[20];
  58. uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
  59. char res21[4];
  60. uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
  61. char res22[20];
  62. uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
  63. char res23[4];
  64. uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
  65. char res24[716];
  66. uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */
  67. char res25[4];
  68. uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
  69. char res26[4];
  70. uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
  71. char res27[44];
  72. uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
  73. uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
  74. uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
  75. uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
  76. char res28[16];
  77. uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
  78. uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
  79. uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
  80. char res29[3476];
  81. uint edr; /* 0x1e00 - MCM Error Detect Register */
  82. char res30[4];
  83. uint eer; /* 0x1e08 - MCM Error Enable Register */
  84. uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */
  85. uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */
  86. uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */
  87. char res31[488];
  88. } ccsr_local_mcm_t;
  89. /* Daul I2C Registers(0x3000-0x4000) */
  90. typedef struct ccsr_i2c {
  91. struct fsl_i2c_base i2c[2];
  92. u8 res[4096 - 2 * sizeof(struct fsl_i2c_base)];
  93. } ccsr_i2c_t;
  94. /* DUART Registers(0x4000-0x5000) */
  95. typedef struct ccsr_duart {
  96. char res1[1280];
  97. u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
  98. u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
  99. u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
  100. u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
  101. u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
  102. u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
  103. u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
  104. u_char uscr1; /* 0x4507 - UART1 Scratch Register */
  105. char res2[8];
  106. u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
  107. char res3[239];
  108. u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
  109. u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
  110. u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
  111. u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
  112. u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
  113. u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
  114. u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
  115. u_char uscr2; /* 0x4607 - UART2 Scratch Register */
  116. char res4[8];
  117. u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
  118. char res5[2543];
  119. } ccsr_duart_t;
  120. /* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
  121. typedef struct ccsr_pex {
  122. uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
  123. uint cfg_data; /* 0x8004 - PEX Configuration Data Register */
  124. char res1[4];
  125. uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */
  126. char res2[16];
  127. uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */
  128. uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
  129. uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */
  130. uint pm_command; /* 0x802c - PEX PM Command register */
  131. char res3[3016];
  132. uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */
  133. uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */
  134. uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
  135. uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
  136. char res4[8];
  137. uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
  138. char res5[12];
  139. uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
  140. uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
  141. uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
  142. char res6[4];
  143. uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
  144. char res7[12];
  145. uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
  146. uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
  147. uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
  148. char res8[4];
  149. uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
  150. char res9[12];
  151. uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
  152. uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
  153. uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
  154. char res10[4];
  155. uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
  156. char res11[12];
  157. uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
  158. uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
  159. uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
  160. char res12[4];
  161. uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
  162. char res13[12];
  163. char res14[256];
  164. uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */
  165. char res15[4];
  166. uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
  167. uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
  168. uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
  169. char res16[12];
  170. uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */
  171. char res17[4];
  172. uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
  173. uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
  174. uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
  175. char res18[12];
  176. uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */
  177. char res19[4];
  178. uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
  179. uint piwbear1;
  180. uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
  181. char res20[12];
  182. uint pedr; /* 0x8e00 - PEX Error Detect Register */
  183. char res21[4];
  184. uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */
  185. char res22[4];
  186. uint pecdr; /* 0x8e10 - PEX Error Disable Register */
  187. char res23[12];
  188. uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */
  189. char res24[4];
  190. uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */
  191. uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */
  192. uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */
  193. uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */
  194. char res25[452];
  195. char res26[4];
  196. } ccsr_pex_t;
  197. /* Hyper Transport Register Block (0xA000-0xB000) */
  198. typedef struct ccsr_ht {
  199. uint hcfg_addr; /* 0xa000 - HT Configuration Address register */
  200. uint hcfg_data; /* 0xa004 - HT Configuration Data register */
  201. char res1[3064];
  202. uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */
  203. char res2[12];
  204. uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
  205. char res3[12];
  206. uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
  207. char res4[4];
  208. uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
  209. char res5[4];
  210. uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
  211. char res6[12];
  212. uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
  213. char res7[4];
  214. uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
  215. char res8[4];
  216. uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
  217. char res9[12];
  218. uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
  219. char res10[4];
  220. uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
  221. char res11[4];
  222. uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
  223. char res12[12];
  224. uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
  225. char res13[4];
  226. uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
  227. char res14[4];
  228. uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
  229. char res15[236];
  230. uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
  231. char res16[4];
  232. uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
  233. char res17[4];
  234. uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
  235. char res18[12];
  236. uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
  237. char res19[4];
  238. uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
  239. char res20[4];
  240. uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
  241. char res21[12];
  242. uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
  243. char res22[4];
  244. uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
  245. char res23[4];
  246. uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
  247. char res24[12];
  248. uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
  249. char res25[4];
  250. uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
  251. char res26[4];
  252. uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
  253. char res27[12];
  254. uint hedr; /* 0xae00 - HT Error Detect register */
  255. char res28[4];
  256. uint heier; /* 0xae08 - HT Error Interrupt Enable register */
  257. char res29[4];
  258. uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
  259. char res30[12];
  260. uint hecsr; /* 0xae20 - HT Error Capture Status register */
  261. char res31[4];
  262. uint hec0; /* 0xae28 - HT Error Capture 0 register */
  263. uint hec1; /* 0xae2c - HT Error Capture 1 register */
  264. uint hec2; /* 0xae30 - HT Error Capture 2 register */
  265. char res32[460];
  266. } ccsr_ht_t;
  267. /* DMA Registers(0x2_1000-0x2_2000) */
  268. typedef struct ccsr_dma {
  269. char res1[256];
  270. struct fsl_dma dma[4];
  271. uint dgsr; /* 0x21300 - DMA General Status Register */
  272. char res2[3324];
  273. } ccsr_dma_t;
  274. /* tsec1-4: 24000-28000 */
  275. typedef struct ccsr_tsec {
  276. uint id; /* 0x24000 - Controller ID Register */
  277. char res1[12];
  278. uint ievent; /* 0x24010 - Interrupt Event Register */
  279. uint imask; /* 0x24014 - Interrupt Mask Register */
  280. uint edis; /* 0x24018 - Error Disabled Register */
  281. char res2[4];
  282. uint ecntrl; /* 0x24020 - Ethernet Control Register */
  283. char res2_1[4];
  284. uint ptv; /* 0x24028 - Pause Time Value Register */
  285. uint dmactrl; /* 0x2402c - DMA Control Register */
  286. uint tbipa; /* 0x24030 - TBI PHY Address Register */
  287. char res3[88];
  288. uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
  289. char res4[8];
  290. uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
  291. uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
  292. char res4_1[4];
  293. uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */
  294. uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */
  295. char res5[84];
  296. uint tctrl; /* 0x24100 - Transmit Control Register */
  297. uint tstat; /* 0x24104 - Transmit Status Register */
  298. uint dfvlan; /* 0x24108 - Default VLAN control word */
  299. char res6[4];
  300. uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
  301. uint tqueue; /* 0x24114 - Transmit Queue Control Register */
  302. char res7[40];
  303. uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
  304. uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
  305. char res8[52];
  306. uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
  307. char res9[4];
  308. uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
  309. char res10[4];
  310. uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
  311. char res11[4];
  312. uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
  313. char res12[4];
  314. uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
  315. char res13[4];
  316. uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
  317. char res14[4];
  318. uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
  319. char res15[4];
  320. uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
  321. char res16[4];
  322. uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
  323. char res17[64];
  324. uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
  325. uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
  326. char res18[4];
  327. uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
  328. char res19[4];
  329. uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
  330. char res20[4];
  331. uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
  332. char res21[4];
  333. uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
  334. char res22[4];
  335. uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
  336. char res23[4];
  337. uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
  338. char res24[4];
  339. uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
  340. char res25[192];
  341. uint rctrl; /* 0x24300 - Receive Control Register */
  342. uint rstat; /* 0x24304 - Receive Status Register */
  343. char res26[8];
  344. uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */
  345. uint rqueue; /* 0x24314 - Receive queue control register */
  346. char res27[24];
  347. uint rbifx; /* 0x24330 - Receive bit field extract control Register */
  348. uint rqfar; /* 0x24334 - Receive queue filing table address Register */
  349. uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
  350. uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
  351. uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
  352. char res28[56];
  353. uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
  354. char res29[4];
  355. uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
  356. char res30[4];
  357. uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
  358. char res31[4];
  359. uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
  360. char res32[4];
  361. uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
  362. char res33[4];
  363. uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
  364. char res34[4];
  365. uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
  366. char res35[4];
  367. uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
  368. char res36[4];
  369. uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
  370. char res37[64];
  371. uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
  372. uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
  373. char res38[4];
  374. uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
  375. char res39[4];
  376. uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
  377. char res40[4];
  378. uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
  379. char res41[4];
  380. uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
  381. char res42[4];
  382. uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
  383. char res43[4];
  384. uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
  385. char res44[4];
  386. uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
  387. char res45[192];
  388. uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
  389. uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
  390. uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
  391. uint hafdup; /* 0x2450c - Half Duplex Register */
  392. uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
  393. char res46[12];
  394. uint miimcfg; /* 0x24520 - MII Management Configuration Register */
  395. uint miimcom; /* 0x24524 - MII Management Command Register */
  396. uint miimadd; /* 0x24528 - MII Management Address Register */
  397. uint miimcon; /* 0x2452c - MII Management Control Register */
  398. uint miimstat; /* 0x24530 - MII Management Status Register */
  399. uint miimind; /* 0x24534 - MII Management Indicator Register */
  400. uint ifctrl; /* 0x24538 - Interface Contrl Register */
  401. uint ifstat; /* 0x2453c - Interface Status Register */
  402. uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
  403. uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
  404. uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
  405. uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
  406. uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
  407. uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
  408. uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
  409. uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
  410. uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
  411. uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
  412. uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
  413. uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
  414. uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
  415. uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
  416. uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
  417. uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
  418. uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
  419. uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
  420. uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
  421. uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
  422. uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
  423. uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
  424. uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
  425. uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
  426. uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
  427. uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
  428. uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
  429. uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
  430. uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
  431. uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
  432. uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
  433. uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
  434. char res48[192];
  435. uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
  436. uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
  437. uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
  438. uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
  439. uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
  440. uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
  441. uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
  442. uint rbyt; /* 0x2469c - Receive Byte Counter */
  443. uint rpkt; /* 0x246a0 - Receive Packet Counter */
  444. uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
  445. uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
  446. uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
  447. uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
  448. uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
  449. uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
  450. uint raln; /* 0x246bc - Receive Alignment Error Counter */
  451. uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
  452. uint rcde; /* 0x246c4 - Receive Code Error Counter */
  453. uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
  454. uint rund; /* 0x246cc - Receive Undersize Packet Counter */
  455. uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
  456. uint rfrg; /* 0x246d4 - Receive Fragments Counter */
  457. uint rjbr; /* 0x246d8 - Receive Jabber Counter */
  458. uint rdrp; /* 0x246dc - Receive Drop Counter */
  459. uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
  460. uint tpkt; /* 0x246e4 - Transmit Packet Counter */
  461. uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
  462. uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
  463. uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
  464. uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
  465. uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
  466. uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
  467. uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
  468. uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
  469. uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
  470. uint tncl; /* 0x2470c - Transmit Total Collision Counter */
  471. char res49[4];
  472. uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
  473. uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
  474. uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
  475. uint txcf; /* 0x24720 - Transmit Control Frame Counter */
  476. uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
  477. uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
  478. uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
  479. uint car1; /* 0x24730 - Carry Register One */
  480. uint car2; /* 0x24734 - Carry Register Two */
  481. uint cam1; /* 0x24738 - Carry Mask Register One */
  482. uint cam2; /* 0x2473c - Carry Mask Register Two */
  483. uint rrej; /* 0x24740 - Receive filer rejected packet counter */
  484. char res50[188];
  485. uint iaddr0; /* 0x24800 - Indivdual address register 0 */
  486. uint iaddr1; /* 0x24804 - Indivdual address register 1 */
  487. uint iaddr2; /* 0x24808 - Indivdual address register 2 */
  488. uint iaddr3; /* 0x2480c - Indivdual address register 3 */
  489. uint iaddr4; /* 0x24810 - Indivdual address register 4 */
  490. uint iaddr5; /* 0x24814 - Indivdual address register 5 */
  491. uint iaddr6; /* 0x24818 - Indivdual address register 6 */
  492. uint iaddr7; /* 0x2481c - Indivdual address register 7 */
  493. char res51[96];
  494. uint gaddr0; /* 0x24880 - Global address register 0 */
  495. uint gaddr1; /* 0x24884 - Global address register 1 */
  496. uint gaddr2; /* 0x24888 - Global address register 2 */
  497. uint gaddr3; /* 0x2488c - Global address register 3 */
  498. uint gaddr4; /* 0x24890 - Global address register 4 */
  499. uint gaddr5; /* 0x24894 - Global address register 5 */
  500. uint gaddr6; /* 0x24898 - Global address register 6 */
  501. uint gaddr7; /* 0x2489c - Global address register 7 */
  502. char res52[352];
  503. uint fifocfg; /* 0x24A00 - FIFO interface configuration register */
  504. char res53[500];
  505. uint attr; /* 0x24BF8 - DMA Attribute register */
  506. uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */
  507. char res54[1024];
  508. } ccsr_tsec_t;
  509. /* PIC Registers(0x4_0000-0x6_1000) */
  510. typedef struct ccsr_pic {
  511. char res1[64];
  512. uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
  513. char res2[12];
  514. uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
  515. char res3[12];
  516. uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
  517. char res4[12];
  518. uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
  519. char res5[12];
  520. uint ctpr; /* 0x40080 - Current Task Priority Register */
  521. char res6[12];
  522. uint whoami; /* 0x40090 - Who Am I Register */
  523. char res7[12];
  524. uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
  525. char res8[12];
  526. uint eoi; /* 0x400b0 - End Of Interrupt Register */
  527. char res9[3916];
  528. uint frr; /* 0x41000 - Feature Reporting Register */
  529. char res10[28];
  530. uint gcr; /* 0x41020 - Global Configuration Register */
  531. #define MPC86xx_PICGCR_RST 0x80000000
  532. #define MPC86xx_PICGCR_MODE 0x20000000
  533. char res11[92];
  534. uint vir; /* 0x41080 - Vendor Identification Register */
  535. char res12[12];
  536. uint pir; /* 0x41090 - Processor Initialization Register */
  537. char res13[12];
  538. uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
  539. char res14[12];
  540. uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
  541. char res15[12];
  542. uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
  543. char res16[12];
  544. uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
  545. char res17[12];
  546. uint svr; /* 0x410e0 - Spurious Vector Register */
  547. char res18[12];
  548. uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
  549. char res19[12];
  550. uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
  551. char res20[12];
  552. uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
  553. char res21[12];
  554. uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
  555. char res22[12];
  556. uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
  557. char res23[12];
  558. uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
  559. char res24[12];
  560. uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
  561. char res25[12];
  562. uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
  563. char res26[12];
  564. uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
  565. char res27[12];
  566. uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
  567. char res28[12];
  568. uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
  569. char res29[12];
  570. uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
  571. char res30[12];
  572. uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
  573. char res31[12];
  574. uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
  575. char res32[12];
  576. uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
  577. char res33[12];
  578. uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
  579. char res34[12];
  580. uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
  581. char res35[268];
  582. uint tcr; /* 0x41300 - Timer Control Register */
  583. char res36[12];
  584. uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
  585. char res37[12];
  586. uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
  587. char res38[12];
  588. uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
  589. char res39[12];
  590. uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
  591. char res40[12];
  592. uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */
  593. char res41[12];
  594. uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */
  595. char res42[12];
  596. uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */
  597. char res43[12];
  598. uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */
  599. char res44[12];
  600. uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */
  601. char res45[12];
  602. uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */
  603. char res46[12];
  604. uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */
  605. char res47[12];
  606. uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */
  607. char res48[60];
  608. uint msgr0; /* 0x41400 - Message Register 0 */
  609. char res49[12];
  610. uint msgr1; /* 0x41410 - Message Register 1 */
  611. char res50[12];
  612. uint msgr2; /* 0x41420 - Message Register 2 */
  613. char res51[12];
  614. uint msgr3; /* 0x41430 - Message Register 3 */
  615. char res52[204];
  616. uint mer; /* 0x41500 - Message Enable Register */
  617. char res53[12];
  618. uint msr; /* 0x41510 - Message Status Register */
  619. char res54[60140];
  620. uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
  621. char res55[12];
  622. uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
  623. char res56[12];
  624. uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
  625. char res57[12];
  626. uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
  627. char res58[12];
  628. uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
  629. char res59[12];
  630. uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
  631. char res60[12];
  632. uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
  633. char res61[12];
  634. uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
  635. char res62[12];
  636. uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
  637. char res63[12];
  638. uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
  639. char res64[12];
  640. uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
  641. char res65[12];
  642. uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
  643. char res66[12];
  644. uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
  645. char res67[12];
  646. uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
  647. char res68[12];
  648. uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
  649. char res69[12];
  650. uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
  651. char res70[12];
  652. uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
  653. char res71[12];
  654. uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
  655. char res72[12];
  656. uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
  657. char res73[12];
  658. uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
  659. char res74[12];
  660. uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
  661. char res75[12];
  662. uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
  663. char res76[12];
  664. uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
  665. char res77[12];
  666. uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
  667. char res78[140];
  668. uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
  669. char res79[12];
  670. uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
  671. char res80[12];
  672. uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
  673. char res81[12];
  674. uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
  675. char res82[12];
  676. uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
  677. char res83[12];
  678. uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
  679. char res84[12];
  680. uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
  681. char res85[12];
  682. uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
  683. char res86[12];
  684. uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
  685. char res87[12];
  686. uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
  687. char res88[12];
  688. uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
  689. char res89[12];
  690. uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
  691. char res90[12];
  692. uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
  693. char res91[12];
  694. uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
  695. char res92[12];
  696. uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
  697. char res93[12];
  698. uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
  699. char res94[12];
  700. uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
  701. char res95[12];
  702. uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
  703. char res96[12];
  704. uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
  705. char res97[12];
  706. uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
  707. char res98[12];
  708. uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
  709. char res99[12];
  710. uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
  711. char res100[12];
  712. uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
  713. char res101[12];
  714. uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
  715. char res102[12];
  716. uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
  717. char res103[12];
  718. uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
  719. char res104[12];
  720. uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
  721. char res105[12];
  722. uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
  723. char res106[12];
  724. uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
  725. char res107[12];
  726. uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
  727. char res108[12];
  728. uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
  729. char res109[12];
  730. uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
  731. char res110[12];
  732. uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
  733. char res111[12];
  734. uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
  735. char res112[12];
  736. uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
  737. char res113[12];
  738. uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
  739. char res114[12];
  740. uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
  741. char res115[12];
  742. uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
  743. char res116[12];
  744. uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
  745. char res117[12];
  746. uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
  747. char res118[12];
  748. uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
  749. char res119[12];
  750. uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
  751. char res120[12];
  752. uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
  753. char res121[12];
  754. uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
  755. char res122[12];
  756. uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
  757. char res123[12];
  758. uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
  759. char res124[12];
  760. uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
  761. char res125[12];
  762. uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
  763. char res126[12];
  764. uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
  765. char res127[12];
  766. uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
  767. char res128[12];
  768. uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
  769. char res129[12];
  770. uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
  771. char res130[12];
  772. uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
  773. char res131[12];
  774. uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
  775. char res132[12];
  776. uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
  777. char res133[12];
  778. uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
  779. char res134[12];
  780. uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
  781. char res135[12];
  782. uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
  783. char res136[12];
  784. uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
  785. char res137[12];
  786. uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
  787. char res138[12];
  788. uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
  789. char res139[12];
  790. uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
  791. char res140[12];
  792. uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
  793. char res141[12];
  794. uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
  795. char res142[4108];
  796. uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
  797. char res143[12];
  798. uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
  799. char res144[12];
  800. uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
  801. char res145[12];
  802. uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
  803. char res146[12];
  804. uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
  805. char res147[12];
  806. uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
  807. char res148[12];
  808. uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
  809. char res149[12];
  810. uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
  811. char res150[59852];
  812. uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
  813. char res151[12];
  814. uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
  815. char res152[12];
  816. uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
  817. char res153[12];
  818. uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
  819. char res154[12];
  820. uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
  821. char res155[12];
  822. uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
  823. char res156[12];
  824. uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
  825. char res157[12];
  826. uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
  827. char res158[3916];
  828. } ccsr_pic_t;
  829. /* RapidIO Registers(0xc_0000-0xe_0000) */
  830. typedef struct ccsr_rio {
  831. uint didcar; /* 0xc0000 - Device Identity Capability Register */
  832. uint dicar; /* 0xc0004 - Device Information Capability Register */
  833. uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
  834. uint aicar; /* 0xc000c - Assembly Information Capability Register */
  835. uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
  836. uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
  837. uint socar; /* 0xc0018 - Source Operations Capability Register */
  838. uint docar; /* 0xc001c - Destination Operations Capability Register */
  839. char res1[32];
  840. uint msr; /* 0xc0040 - Mailbox Command And Status Register */
  841. uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
  842. char res2[4];
  843. uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
  844. char res3[12];
  845. uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
  846. uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
  847. char res4[4];
  848. uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
  849. uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
  850. char res5[144];
  851. uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
  852. char res6[28];
  853. uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
  854. uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
  855. char res7[20];
  856. uint pgccsr; /* 0xc013c - Port General Command and Status Register */
  857. uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
  858. uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
  859. uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
  860. char res8[12];
  861. uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
  862. uint pccsr; /* 0xc015c - Port Control Command and Status Register */
  863. char res9[1184];
  864. uint erbh; /* 0xc0600 - Error Reporting Block Header Register */
  865. char res10[4];
  866. uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */
  867. uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */
  868. char res11[4];
  869. uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */
  870. uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */
  871. uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */
  872. char res12[32];
  873. uint edcsr; /* 0xc0640 - Port 0 error detect status register */
  874. uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */
  875. uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */
  876. uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
  877. uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */
  878. uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */
  879. uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */
  880. char res13[12];
  881. uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */
  882. uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/
  883. char res14[63892];
  884. uint llcr; /* 0xd0004 - Logical Layer Configuration Register */
  885. char res15[12];
  886. uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */
  887. char res16[12];
  888. uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
  889. char res17[92];
  890. uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
  891. char res18[124];
  892. uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
  893. char res19[28];
  894. uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
  895. char res20[12];
  896. uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */
  897. char res21[12];
  898. uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
  899. char res22[20];
  900. uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */
  901. char res23[4];
  902. uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */
  903. char res24[2716];
  904. uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
  905. uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
  906. char res25[8];
  907. uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
  908. char res26[12];
  909. uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
  910. uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
  911. uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
  912. char res27[4];
  913. uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
  914. uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
  915. uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
  916. uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
  917. uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
  918. uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
  919. uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
  920. char res28[4];
  921. uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
  922. uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
  923. uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
  924. uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
  925. uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
  926. uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
  927. uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
  928. char res29[4];
  929. uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
  930. uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
  931. uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
  932. uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
  933. uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
  934. uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
  935. uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
  936. char res30[4];
  937. uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
  938. uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
  939. uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
  940. uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
  941. uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
  942. uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
  943. uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
  944. char res31[4];
  945. uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
  946. uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
  947. uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
  948. uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
  949. uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
  950. uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
  951. uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
  952. char res32[4];
  953. uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
  954. uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
  955. uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
  956. uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
  957. uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
  958. uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
  959. uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
  960. char res33[4];
  961. uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
  962. uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
  963. uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
  964. uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
  965. uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
  966. uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
  967. uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
  968. char res34[4];
  969. uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
  970. uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
  971. uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
  972. uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
  973. char res35[64];
  974. uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
  975. uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
  976. char res36[4];
  977. uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
  978. char res37[12];
  979. uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
  980. char res38[4];
  981. uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
  982. char res39[4];
  983. uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
  984. char res40[12];
  985. uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
  986. char res41[4];
  987. uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
  988. char res42[4];
  989. uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
  990. char res43[12];
  991. uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
  992. char res44[4];
  993. uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
  994. char res45[4];
  995. uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
  996. char res46[12];
  997. uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
  998. char res47[12];
  999. uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
  1000. char res48[12];
  1001. uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
  1002. uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
  1003. uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
  1004. uint pecr; /* 0xd0e0c - Port Error Control Register */
  1005. uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
  1006. uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
  1007. uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
  1008. char res49[4];
  1009. uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
  1010. char res50[4];
  1011. uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
  1012. uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
  1013. char res51[8656];
  1014. uint omr; /* 0xd3000 - Outbound Mode Register */
  1015. uint osr; /* 0xd3004 - Outbound Status Register */
  1016. uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
  1017. uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
  1018. uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */
  1019. uint osar; /* 0xd3014 - Outbound Unit Source Address Register */
  1020. uint odpr; /* 0xd3018 - Outbound Destination Port Register */
  1021. uint odatr; /* 0xd301c - Outbound Destination Attributes Register */
  1022. uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */
  1023. uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
  1024. uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
  1025. uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */
  1026. uint omgr; /* 0xd3030 - Outbound Multicast Group Register */
  1027. uint omlr; /* 0xd3034 - Outbound Multicast List Register */
  1028. char res52[40];
  1029. uint imr; /* 0xd3060 - Outbound Mode Register */
  1030. uint isr; /* 0xd3064 - Inbound Status Register */
  1031. uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
  1032. uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
  1033. uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
  1034. uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
  1035. uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
  1036. char res53[900];
  1037. uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */
  1038. uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */
  1039. char res54[16];
  1040. uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */
  1041. uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */
  1042. char res55[12];
  1043. uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
  1044. char res56[48];
  1045. uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */
  1046. uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */
  1047. uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
  1048. uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
  1049. uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
  1050. uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
  1051. uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
  1052. char res57[100];
  1053. uint pwmr; /* 0xd34e0 - Port-Write Mode Register */
  1054. uint pwsr; /* 0xd34e4 - Port-Write Status Register */
  1055. uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
  1056. uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */
  1057. char res58[51984];
  1058. } ccsr_rio_t;
  1059. /* Global Utilities Register Block(0xe_0000-0xf_ffff) */
  1060. typedef struct ccsr_gur {
  1061. uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
  1062. uint porbmsr; /* 0xe0004 - POR boot mode status register */
  1063. uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
  1064. uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
  1065. uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
  1066. char res1[12];
  1067. uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
  1068. char res2[12];
  1069. uint gpiocr; /* 0xe0030 - GPIO control register */
  1070. char res3[12];
  1071. uint gpoutdr; /* 0xe0040 - General-purpose output data register */
  1072. char res4[12];
  1073. uint gpindr; /* 0xe0050 - General-purpose input data register */
  1074. char res5[12];
  1075. uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
  1076. char res6[12];
  1077. uint devdisr; /* 0xe0070 - Device disable control */
  1078. char res7[12];
  1079. uint powmgtcsr; /* 0xe0080 - Power management status and control register */
  1080. char res8[12];
  1081. uint mcpsumr; /* 0xe0090 - Machine check summary register */
  1082. uint rstrscr; /* 0xe0094 - Reset request status and control register */
  1083. char res9[8];
  1084. uint pvr; /* 0xe00a0 - Processor version register */
  1085. uint svr; /* 0xe00a4 - System version register */
  1086. char res10a[8];
  1087. uint rstcr; /* 0xe00b0 - Reset control register */
  1088. char res10b[1868];
  1089. uint clkdvdr; /* 0xe0800 - Clock Divide register */
  1090. char res10c[796];
  1091. uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */
  1092. char res10d[4];
  1093. uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */
  1094. char res10e[724];
  1095. uint clkocr; /* 0xe0e00 - Clock out select register */
  1096. char res11[12];
  1097. uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
  1098. char res12[12];
  1099. uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
  1100. char res13a[224];
  1101. uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */
  1102. char res13b[4];
  1103. uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */
  1104. char res14[24];
  1105. uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
  1106. char res15a[24];
  1107. uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */
  1108. uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */
  1109. char res16[184];
  1110. } ccsr_gur_t;
  1111. #define MPC8610_PORBMSR_HA 0x00070000
  1112. #define MPC8610_PORBMSR_HA_SHIFT 16
  1113. #define MPC8641_PORBMSR_HA 0x00060000
  1114. #define MPC8641_PORBMSR_HA_SHIFT 17
  1115. #define MPC8610_PORDEVSR_IO_SEL 0x00380000
  1116. #define MPC8610_PORDEVSR_IO_SEL_SHIFT 19
  1117. #define MPC8641_PORDEVSR_IO_SEL 0x000F0000
  1118. #define MPC8641_PORDEVSR_IO_SEL_SHIFT 16
  1119. #define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
  1120. #define MPC86xx_DEVDISR_PCIEX1 0x80000000
  1121. #define MPC86xx_DEVDISR_PCIEX2 0x40000000
  1122. #define MPC86xx_DEVDISR_PCI1 0x80000000
  1123. #define MPC86xx_DEVDISR_PCIE1 0x40000000
  1124. #define MPC86xx_DEVDISR_PCIE2 0x20000000
  1125. #define MPC86xx_DEVDISR_SRIO 0x00080000
  1126. #define MPC86xx_DEVDISR_RMSG 0x00040000
  1127. #define MPC86xx_DEVDISR_CPU0 0x00008000
  1128. #define MPC86xx_DEVDISR_CPU1 0x00004000
  1129. #define MPC86xx_RSTCR_HRST_REQ 0x00000002
  1130. /*
  1131. * Watchdog register block(0xe_4000-0xe_4fff)
  1132. */
  1133. typedef struct ccsr_wdt {
  1134. uint res0;
  1135. uint swcrr; /* System watchdog control register */
  1136. uint swcnr; /* System watchdog count register */
  1137. char res1[2];
  1138. ushort swsrr; /* System watchdog service register */
  1139. char res2[4080];
  1140. } ccsr_wdt_t;
  1141. typedef struct immap {
  1142. ccsr_local_mcm_t im_local_mcm;
  1143. struct ccsr_ddr im_ddr1;
  1144. ccsr_i2c_t im_i2c;
  1145. ccsr_duart_t im_duart;
  1146. fsl_lbc_t im_lbc;
  1147. struct ccsr_ddr im_ddr2;
  1148. char res1[4096];
  1149. ccsr_pex_t im_pex1;
  1150. ccsr_pex_t im_pex2;
  1151. ccsr_ht_t im_ht;
  1152. char res2[90112];
  1153. ccsr_dma_t im_dma;
  1154. char res3[8192];
  1155. ccsr_tsec_t im_tsec1;
  1156. ccsr_tsec_t im_tsec2;
  1157. ccsr_tsec_t im_tsec3;
  1158. ccsr_tsec_t im_tsec4;
  1159. char res4[98304];
  1160. ccsr_pic_t im_pic;
  1161. char res5[389120];
  1162. ccsr_rio_t im_rio;
  1163. ccsr_gur_t im_gur;
  1164. char res6[12288];
  1165. ccsr_wdt_t im_wdt;
  1166. } immap_t;
  1167. extern immap_t *immr;
  1168. #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
  1169. #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
  1170. #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
  1171. #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
  1172. #define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
  1173. #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
  1174. #define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
  1175. #define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET)
  1176. #define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
  1177. #ifdef CONFIG_ARCH_MPC8610
  1178. #define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000
  1179. #else
  1180. #define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000
  1181. #endif
  1182. #define CONFIG_SYS_MPC86xx_PCIE2_OFFSET 0x9000
  1183. #define CONFIG_SYS_PCI1_ADDR \
  1184. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET)
  1185. #define CONFIG_SYS_PCI2_ADDR \
  1186. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET)
  1187. #define CONFIG_SYS_PCIE1_ADDR \
  1188. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET)
  1189. #define CONFIG_SYS_PCIE2_ADDR \
  1190. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET)
  1191. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  1192. #define CONFIG_SYS_MDIO1_OFFSET 0x24000
  1193. #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
  1194. #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  1195. #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
  1196. #endif /*__IMMAP_86xx__*/