mp.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2010 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <asm/global_data.h>
  8. #include <asm/processor.h>
  9. #include <asm/mmu.h>
  10. #include <ioports.h>
  11. #include <lmb.h>
  12. #include <asm/io.h>
  13. #include <asm/mp.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. int cpu_reset(u32 nr)
  16. {
  17. /* dummy function so common/cmd_mp.c will build
  18. * should be implemented in the future, when cpu_release()
  19. * is supported. Be aware there may be a similiar bug
  20. * as exists on MPC85xx w/its PIC having a timing window
  21. * associated to resetting the core */
  22. return 1;
  23. }
  24. int cpu_status(u32 nr)
  25. {
  26. /* dummy function so common/cmd_mp.c will build */
  27. return 0;
  28. }
  29. int cpu_disable(u32 nr)
  30. {
  31. volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
  32. volatile ccsr_gur_t *gur = &immap->im_gur;
  33. switch (nr) {
  34. case 0:
  35. setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
  36. break;
  37. case 1:
  38. setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
  39. break;
  40. default:
  41. printf("Invalid cpu number for disable %d\n", nr);
  42. return 1;
  43. }
  44. return 0;
  45. }
  46. int is_core_disabled(int nr) {
  47. immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
  48. ccsr_gur_t *gur = &immap->im_gur;
  49. u32 devdisr = in_be32(&gur->devdisr);
  50. switch (nr) {
  51. case 0:
  52. return (devdisr & MPC86xx_DEVDISR_CPU0);
  53. case 1:
  54. return (devdisr & MPC86xx_DEVDISR_CPU1);
  55. default:
  56. printf("Invalid cpu number for disable %d\n", nr);
  57. }
  58. return 0;
  59. }
  60. int cpu_release(u32 nr, int argc, char *const argv[])
  61. {
  62. /* dummy function so common/cmd_mp.c will build
  63. * should be implemented in the future */
  64. return 1;
  65. }
  66. u32 determine_mp_bootpg(unsigned int *pagesize)
  67. {
  68. if (pagesize)
  69. *pagesize = 4096;
  70. /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
  71. if ((u64)gd->ram_size > 0xfffff000)
  72. return (0xfff00000);
  73. return (gd->ram_size - (1024 * 1024));
  74. }
  75. void cpu_mp_lmb_reserve(struct lmb *lmb)
  76. {
  77. u32 bootpg = determine_mp_bootpg(NULL);
  78. /* tell u-boot we stole a page */
  79. lmb_reserve(lmb, bootpg, 4096);
  80. }
  81. /*
  82. * Copy the code for other cpus to execute into an
  83. * aligned location accessible via BPTR
  84. */
  85. void setup_mp(void)
  86. {
  87. extern ulong __secondary_start_page;
  88. ulong fixup = (ulong)&__secondary_start_page;
  89. u32 bootpg = determine_mp_bootpg(NULL);
  90. u32 bootpg_va;
  91. if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
  92. /* We're not covered by the DDR mapping, set up BAT */
  93. write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
  94. BATU_VS | BATU_VP,
  95. bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
  96. bootpg_va = CONFIG_SYS_SCRATCH_VA;
  97. } else {
  98. bootpg_va = bootpg;
  99. }
  100. memcpy((void *)bootpg_va, (void *)fixup, 4096);
  101. flush_cache(bootpg_va, 4096);
  102. /* remove the temporary BAT mapping */
  103. if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
  104. write_bat(DBAT7, 0, 0);
  105. /* If the physical location of bootpg is not at fff00000, set BPTR */
  106. if (bootpg != 0xfff00000)
  107. out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
  108. (bootpg >> 12));
  109. }